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0ebc4cda BH |
1 | /* |
2 | * This file contains the 64-bit "server" PowerPC variant | |
3 | * of the low level exception handling including exception | |
4 | * vectors, exception return, part of the slb and stab | |
5 | * handling and other fixed offset specific things. | |
6 | * | |
7 | * This file is meant to be #included from head_64.S due to | |
25985edc | 8 | * position dependent assembly. |
0ebc4cda BH |
9 | * |
10 | * Most of this originates from head_64.S and thus has the same | |
11 | * copyright history. | |
12 | * | |
13 | */ | |
14 | ||
8aa34ab8 | 15 | #include <asm/exception-64s.h> |
46f52210 | 16 | #include <asm/ptrace.h> |
8aa34ab8 | 17 | |
0ebc4cda BH |
18 | /* |
19 | * We layout physical memory as follows: | |
20 | * 0x0000 - 0x00ff : Secondary processor spin code | |
21 | * 0x0100 - 0x2fff : pSeries Interrupt prologs | |
22 | * 0x3000 - 0x5fff : interrupt support, iSeries and common interrupt prologs | |
23 | * 0x6000 - 0x6fff : Initial (CPU0) segment table | |
24 | * 0x7000 - 0x7fff : FWNMI data area | |
25 | * 0x8000 - : Early init and support code | |
26 | */ | |
27 | ||
0ebc4cda BH |
28 | /* |
29 | * This is the start of the interrupt handlers for pSeries | |
30 | * This code runs with relocation off. | |
31 | * Code from here to __end_interrupts gets copied down to real | |
32 | * address 0x100 when we are running a relocatable kernel. | |
33 | * Therefore any relative branches in this section must only | |
34 | * branch to labels in this section. | |
35 | */ | |
36 | . = 0x100 | |
37 | .globl __start_interrupts | |
38 | __start_interrupts: | |
39 | ||
40 | STD_EXCEPTION_PSERIES(0x100, system_reset) | |
41 | ||
42 | . = 0x200 | |
43 | _machine_check_pSeries: | |
44 | HMT_MEDIUM | |
842f2fed | 45 | DO_KVM 0x200 |
ee43eb78 | 46 | mtspr SPRN_SPRG_SCRATCH0,r13 /* save r13 */ |
a5d4f3ad | 47 | EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common, EXC_STD) |
0ebc4cda BH |
48 | |
49 | . = 0x300 | |
50 | .globl data_access_pSeries | |
51 | data_access_pSeries: | |
52 | HMT_MEDIUM | |
842f2fed | 53 | DO_KVM 0x300 |
ee43eb78 | 54 | mtspr SPRN_SPRG_SCRATCH0,r13 |
0ebc4cda | 55 | BEGIN_FTR_SECTION |
2dd60d79 | 56 | GET_PACA(r13) |
c5a8c0c9 BH |
57 | std r9,PACA_EXSLB+EX_R9(r13) |
58 | std r10,PACA_EXSLB+EX_R10(r13) | |
59 | mfspr r10,SPRN_DAR | |
60 | mfspr r9,SPRN_DSISR | |
61 | srdi r10,r10,60 | |
62 | rlwimi r10,r9,16,0x20 | |
63 | mfcr r9 | |
64 | cmpwi r10,0x2c | |
0ebc4cda | 65 | beq do_stab_bolted_pSeries |
c5a8c0c9 BH |
66 | ld r10,PACA_EXSLB+EX_R10(r13) |
67 | std r11,PACA_EXGEN+EX_R11(r13) | |
68 | ld r11,PACA_EXSLB+EX_R9(r13) | |
69 | std r12,PACA_EXGEN+EX_R12(r13) | |
70 | mfspr r12,SPRN_SPRG_SCRATCH0 | |
71 | std r10,PACA_EXGEN+EX_R10(r13) | |
72 | std r11,PACA_EXGEN+EX_R9(r13) | |
73 | std r12,PACA_EXGEN+EX_R13(r13) | |
a5d4f3ad | 74 | EXCEPTION_PROLOG_PSERIES_1(data_access_common, EXC_STD) |
c5a8c0c9 | 75 | FTR_SECTION_ELSE |
a5d4f3ad | 76 | EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common, EXC_STD) |
c5a8c0c9 | 77 | ALT_FTR_SECTION_END_IFCLR(CPU_FTR_SLB) |
0ebc4cda BH |
78 | |
79 | . = 0x380 | |
80 | .globl data_access_slb_pSeries | |
81 | data_access_slb_pSeries: | |
82 | HMT_MEDIUM | |
842f2fed | 83 | DO_KVM 0x380 |
ee43eb78 | 84 | mtspr SPRN_SPRG_SCRATCH0,r13 |
2dd60d79 | 85 | GET_PACA(r13) |
0ebc4cda BH |
86 | std r3,PACA_EXSLB+EX_R3(r13) |
87 | mfspr r3,SPRN_DAR | |
88 | std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */ | |
89 | mfcr r9 | |
90 | #ifdef __DISABLED__ | |
91 | /* Keep that around for when we re-implement dynamic VSIDs */ | |
92 | cmpdi r3,0 | |
93 | bge slb_miss_user_pseries | |
94 | #endif /* __DISABLED__ */ | |
95 | std r10,PACA_EXSLB+EX_R10(r13) | |
96 | std r11,PACA_EXSLB+EX_R11(r13) | |
97 | std r12,PACA_EXSLB+EX_R12(r13) | |
ee43eb78 | 98 | mfspr r10,SPRN_SPRG_SCRATCH0 |
0ebc4cda BH |
99 | std r10,PACA_EXSLB+EX_R13(r13) |
100 | mfspr r12,SPRN_SRR1 /* and SRR1 */ | |
101 | #ifndef CONFIG_RELOCATABLE | |
102 | b .slb_miss_realmode | |
103 | #else | |
104 | /* | |
105 | * We can't just use a direct branch to .slb_miss_realmode | |
106 | * because the distance from here to there depends on where | |
107 | * the kernel ends up being put. | |
108 | */ | |
109 | mfctr r11 | |
110 | ld r10,PACAKBASE(r13) | |
111 | LOAD_HANDLER(r10, .slb_miss_realmode) | |
112 | mtctr r10 | |
113 | bctr | |
114 | #endif | |
115 | ||
116 | STD_EXCEPTION_PSERIES(0x400, instruction_access) | |
117 | ||
118 | . = 0x480 | |
119 | .globl instruction_access_slb_pSeries | |
120 | instruction_access_slb_pSeries: | |
121 | HMT_MEDIUM | |
842f2fed | 122 | DO_KVM 0x480 |
ee43eb78 | 123 | mtspr SPRN_SPRG_SCRATCH0,r13 |
2dd60d79 | 124 | GET_PACA(r13) |
0ebc4cda BH |
125 | std r3,PACA_EXSLB+EX_R3(r13) |
126 | mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */ | |
127 | std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */ | |
128 | mfcr r9 | |
129 | #ifdef __DISABLED__ | |
130 | /* Keep that around for when we re-implement dynamic VSIDs */ | |
131 | cmpdi r3,0 | |
132 | bge slb_miss_user_pseries | |
133 | #endif /* __DISABLED__ */ | |
134 | std r10,PACA_EXSLB+EX_R10(r13) | |
135 | std r11,PACA_EXSLB+EX_R11(r13) | |
136 | std r12,PACA_EXSLB+EX_R12(r13) | |
ee43eb78 | 137 | mfspr r10,SPRN_SPRG_SCRATCH0 |
0ebc4cda BH |
138 | std r10,PACA_EXSLB+EX_R13(r13) |
139 | mfspr r12,SPRN_SRR1 /* and SRR1 */ | |
140 | #ifndef CONFIG_RELOCATABLE | |
141 | b .slb_miss_realmode | |
142 | #else | |
143 | mfctr r11 | |
144 | ld r10,PACAKBASE(r13) | |
145 | LOAD_HANDLER(r10, .slb_miss_realmode) | |
146 | mtctr r10 | |
147 | bctr | |
148 | #endif | |
149 | ||
a5d4f3ad BH |
150 | . = 0x500; |
151 | .globl hardware_interrupt_pSeries | |
152 | hardware_interrupt_pSeries: | |
153 | BEGIN_FTR_SECTION | |
154 | MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt, EXC_STD) | |
155 | FTR_SECTION_ELSE | |
156 | MASKABLE_EXCEPTION_PSERIES(0x502, hardware_interrupt, EXC_HV) | |
157 | ALT_FTR_SECTION_END_IFCLR(CPU_FTR_HVMODE_206) | |
158 | ||
0ebc4cda BH |
159 | STD_EXCEPTION_PSERIES(0x600, alignment) |
160 | STD_EXCEPTION_PSERIES(0x700, program_check) | |
161 | STD_EXCEPTION_PSERIES(0x800, fp_unavailable) | |
a5d4f3ad BH |
162 | |
163 | . = 0x900; | |
164 | .globl decrementer_pSeries | |
165 | decrementer_pSeries: | |
166 | MASKABLE_EXCEPTION_PSERIES(0x900, decrementer, EXC_STD) | |
167 | ||
0ebc4cda BH |
168 | STD_EXCEPTION_PSERIES(0xa00, trap_0a) |
169 | STD_EXCEPTION_PSERIES(0xb00, trap_0b) | |
170 | ||
171 | . = 0xc00 | |
172 | .globl system_call_pSeries | |
173 | system_call_pSeries: | |
174 | HMT_MEDIUM | |
842f2fed | 175 | DO_KVM 0xc00 |
0ebc4cda BH |
176 | BEGIN_FTR_SECTION |
177 | cmpdi r0,0x1ebe | |
178 | beq- 1f | |
179 | END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) | |
180 | mr r9,r13 | |
2dd60d79 | 181 | GET_PACA(r13) |
0ebc4cda BH |
182 | mfspr r11,SPRN_SRR0 |
183 | ld r12,PACAKBASE(r13) | |
184 | ld r10,PACAKMSR(r13) | |
185 | LOAD_HANDLER(r12, system_call_entry) | |
186 | mtspr SPRN_SRR0,r12 | |
187 | mfspr r12,SPRN_SRR1 | |
188 | mtspr SPRN_SRR1,r10 | |
189 | rfid | |
190 | b . /* prevent speculative execution */ | |
191 | ||
192 | /* Fast LE/BE switch system call */ | |
193 | 1: mfspr r12,SPRN_SRR1 | |
194 | xori r12,r12,MSR_LE | |
195 | mtspr SPRN_SRR1,r12 | |
196 | rfid /* return to userspace */ | |
197 | b . | |
198 | ||
199 | STD_EXCEPTION_PSERIES(0xd00, single_step) | |
200 | STD_EXCEPTION_PSERIES(0xe00, trap_0e) | |
201 | ||
202 | /* We need to deal with the Altivec unavailable exception | |
203 | * here which is at 0xf20, thus in the middle of the | |
204 | * prolog code of the PerformanceMonitor one. A little | |
205 | * trickery is thus necessary | |
206 | */ | |
c86e2ead | 207 | performance_monitor_pSeries_1: |
0ebc4cda | 208 | . = 0xf00 |
842f2fed | 209 | DO_KVM 0xf00 |
0ebc4cda BH |
210 | b performance_monitor_pSeries |
211 | ||
c86e2ead | 212 | altivec_unavailable_pSeries_1: |
0ebc4cda | 213 | . = 0xf20 |
842f2fed | 214 | DO_KVM 0xf20 |
0ebc4cda BH |
215 | b altivec_unavailable_pSeries |
216 | ||
c86e2ead | 217 | vsx_unavailable_pSeries_1: |
0ebc4cda | 218 | . = 0xf40 |
842f2fed | 219 | DO_KVM 0xf40 |
0ebc4cda BH |
220 | b vsx_unavailable_pSeries |
221 | ||
222 | #ifdef CONFIG_CBE_RAS | |
a5d4f3ad | 223 | HSTD_EXCEPTION_PSERIES(0x1202, cbe_system_error) |
0ebc4cda BH |
224 | #endif /* CONFIG_CBE_RAS */ |
225 | STD_EXCEPTION_PSERIES(0x1300, instruction_breakpoint) | |
226 | #ifdef CONFIG_CBE_RAS | |
a5d4f3ad | 227 | HSTD_EXCEPTION_PSERIES(0x1602, cbe_maintenance) |
0ebc4cda BH |
228 | #endif /* CONFIG_CBE_RAS */ |
229 | STD_EXCEPTION_PSERIES(0x1700, altivec_assist) | |
230 | #ifdef CONFIG_CBE_RAS | |
a5d4f3ad | 231 | HSTD_EXCEPTION_PSERIES(0x1802, cbe_thermal) |
0ebc4cda BH |
232 | #endif /* CONFIG_CBE_RAS */ |
233 | ||
234 | . = 0x3000 | |
235 | ||
236 | /*** pSeries interrupt support ***/ | |
237 | ||
238 | /* moved from 0xf00 */ | |
239 | STD_EXCEPTION_PSERIES(., performance_monitor) | |
240 | STD_EXCEPTION_PSERIES(., altivec_unavailable) | |
241 | STD_EXCEPTION_PSERIES(., vsx_unavailable) | |
242 | ||
243 | /* | |
244 | * An interrupt came in while soft-disabled; clear EE in SRR1, | |
245 | * clear paca->hard_enabled and return. | |
246 | */ | |
247 | masked_interrupt: | |
248 | stb r10,PACAHARDIRQEN(r13) | |
249 | mtcrf 0x80,r9 | |
250 | ld r9,PACA_EXGEN+EX_R9(r13) | |
251 | mfspr r10,SPRN_SRR1 | |
252 | rldicl r10,r10,48,1 /* clear MSR_EE */ | |
253 | rotldi r10,r10,16 | |
254 | mtspr SPRN_SRR1,r10 | |
255 | ld r10,PACA_EXGEN+EX_R10(r13) | |
ee43eb78 | 256 | mfspr r13,SPRN_SPRG_SCRATCH0 |
0ebc4cda BH |
257 | rfid |
258 | b . | |
259 | ||
a5d4f3ad BH |
260 | masked_Hinterrupt: |
261 | stb r10,PACAHARDIRQEN(r13) | |
262 | mtcrf 0x80,r9 | |
263 | ld r9,PACA_EXGEN+EX_R9(r13) | |
264 | mfspr r10,SPRN_HSRR1 | |
265 | rldicl r10,r10,48,1 /* clear MSR_EE */ | |
266 | rotldi r10,r10,16 | |
267 | mtspr SPRN_HSRR1,r10 | |
268 | ld r10,PACA_EXGEN+EX_R10(r13) | |
269 | mfspr r13,SPRN_SPRG_HSCRATCH0 | |
270 | hrfid | |
271 | b . | |
272 | ||
0ebc4cda BH |
273 | .align 7 |
274 | do_stab_bolted_pSeries: | |
c5a8c0c9 BH |
275 | std r11,PACA_EXSLB+EX_R11(r13) |
276 | std r12,PACA_EXSLB+EX_R12(r13) | |
277 | mfspr r10,SPRN_SPRG_SCRATCH0 | |
278 | std r10,PACA_EXSLB+EX_R13(r13) | |
a5d4f3ad | 279 | EXCEPTION_PROLOG_PSERIES_1(.do_stab_bolted, EXC_STD) |
0ebc4cda BH |
280 | |
281 | #ifdef CONFIG_PPC_PSERIES | |
282 | /* | |
283 | * Vectors for the FWNMI option. Share common code. | |
284 | */ | |
285 | .globl system_reset_fwnmi | |
286 | .align 7 | |
287 | system_reset_fwnmi: | |
288 | HMT_MEDIUM | |
ee43eb78 | 289 | mtspr SPRN_SPRG_SCRATCH0,r13 /* save r13 */ |
a5d4f3ad | 290 | EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common, EXC_STD) |
0ebc4cda BH |
291 | |
292 | .globl machine_check_fwnmi | |
293 | .align 7 | |
294 | machine_check_fwnmi: | |
295 | HMT_MEDIUM | |
ee43eb78 | 296 | mtspr SPRN_SPRG_SCRATCH0,r13 /* save r13 */ |
a5d4f3ad | 297 | EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common, EXC_STD) |
0ebc4cda BH |
298 | |
299 | #endif /* CONFIG_PPC_PSERIES */ | |
300 | ||
301 | #ifdef __DISABLED__ | |
302 | /* | |
303 | * This is used for when the SLB miss handler has to go virtual, | |
304 | * which doesn't happen for now anymore but will once we re-implement | |
305 | * dynamic VSIDs for shared page tables | |
306 | */ | |
307 | slb_miss_user_pseries: | |
308 | std r10,PACA_EXGEN+EX_R10(r13) | |
309 | std r11,PACA_EXGEN+EX_R11(r13) | |
310 | std r12,PACA_EXGEN+EX_R12(r13) | |
ee43eb78 | 311 | mfspr r10,SPRG_SCRATCH0 |
0ebc4cda BH |
312 | ld r11,PACA_EXSLB+EX_R9(r13) |
313 | ld r12,PACA_EXSLB+EX_R3(r13) | |
314 | std r10,PACA_EXGEN+EX_R13(r13) | |
315 | std r11,PACA_EXGEN+EX_R9(r13) | |
316 | std r12,PACA_EXGEN+EX_R3(r13) | |
317 | clrrdi r12,r13,32 | |
318 | mfmsr r10 | |
319 | mfspr r11,SRR0 /* save SRR0 */ | |
320 | ori r12,r12,slb_miss_user_common@l /* virt addr of handler */ | |
321 | ori r10,r10,MSR_IR|MSR_DR|MSR_RI | |
322 | mtspr SRR0,r12 | |
323 | mfspr r12,SRR1 /* and SRR1 */ | |
324 | mtspr SRR1,r10 | |
325 | rfid | |
326 | b . /* prevent spec. execution */ | |
327 | #endif /* __DISABLED__ */ | |
328 | ||
a58ddea5 AG |
329 | /* KVM's trampoline code needs to be close to the interrupt handlers */ |
330 | ||
331 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER | |
332 | #include "../kvm/book3s_rmhandlers.S" | |
333 | #endif | |
334 | ||
0ebc4cda BH |
335 | .align 7 |
336 | .globl __end_interrupts | |
337 | __end_interrupts: | |
338 | ||
339 | /* | |
340 | * Code from here down to __end_handlers is invoked from the | |
341 | * exception prologs above. Because the prologs assemble the | |
342 | * addresses of these handlers using the LOAD_HANDLER macro, | |
343 | * which uses an addi instruction, these handlers must be in | |
344 | * the first 32k of the kernel image. | |
345 | */ | |
346 | ||
347 | /*** Common interrupt handlers ***/ | |
348 | ||
349 | STD_EXCEPTION_COMMON(0x100, system_reset, .system_reset_exception) | |
350 | ||
351 | /* | |
352 | * Machine check is different because we use a different | |
353 | * save area: PACA_EXMC instead of PACA_EXGEN. | |
354 | */ | |
355 | .align 7 | |
356 | .globl machine_check_common | |
357 | machine_check_common: | |
358 | EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC) | |
359 | FINISH_NAP | |
360 | DISABLE_INTS | |
361 | bl .save_nvgprs | |
362 | addi r3,r1,STACK_FRAME_OVERHEAD | |
363 | bl .machine_check_exception | |
364 | b .ret_from_except | |
365 | ||
366 | STD_EXCEPTION_COMMON_LITE(0x900, decrementer, .timer_interrupt) | |
367 | STD_EXCEPTION_COMMON(0xa00, trap_0a, .unknown_exception) | |
368 | STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception) | |
369 | STD_EXCEPTION_COMMON(0xd00, single_step, .single_step_exception) | |
370 | STD_EXCEPTION_COMMON(0xe00, trap_0e, .unknown_exception) | |
371 | STD_EXCEPTION_COMMON_IDLE(0xf00, performance_monitor, .performance_monitor_exception) | |
372 | STD_EXCEPTION_COMMON(0x1300, instruction_breakpoint, .instruction_breakpoint_exception) | |
373 | #ifdef CONFIG_ALTIVEC | |
374 | STD_EXCEPTION_COMMON(0x1700, altivec_assist, .altivec_assist_exception) | |
375 | #else | |
376 | STD_EXCEPTION_COMMON(0x1700, altivec_assist, .unknown_exception) | |
377 | #endif | |
378 | #ifdef CONFIG_CBE_RAS | |
379 | STD_EXCEPTION_COMMON(0x1200, cbe_system_error, .cbe_system_error_exception) | |
380 | STD_EXCEPTION_COMMON(0x1600, cbe_maintenance, .cbe_maintenance_exception) | |
381 | STD_EXCEPTION_COMMON(0x1800, cbe_thermal, .cbe_thermal_exception) | |
382 | #endif /* CONFIG_CBE_RAS */ | |
383 | ||
384 | .align 7 | |
385 | system_call_entry: | |
386 | b system_call_common | |
387 | ||
388 | /* | |
389 | * Here we have detected that the kernel stack pointer is bad. | |
390 | * R9 contains the saved CR, r13 points to the paca, | |
391 | * r10 contains the (bad) kernel stack pointer, | |
392 | * r11 and r12 contain the saved SRR0 and SRR1. | |
393 | * We switch to using an emergency stack, save the registers there, | |
394 | * and call kernel_bad_stack(), which panics. | |
395 | */ | |
396 | bad_stack: | |
397 | ld r1,PACAEMERGSP(r13) | |
398 | subi r1,r1,64+INT_FRAME_SIZE | |
399 | std r9,_CCR(r1) | |
400 | std r10,GPR1(r1) | |
401 | std r11,_NIP(r1) | |
402 | std r12,_MSR(r1) | |
403 | mfspr r11,SPRN_DAR | |
404 | mfspr r12,SPRN_DSISR | |
405 | std r11,_DAR(r1) | |
406 | std r12,_DSISR(r1) | |
407 | mflr r10 | |
408 | mfctr r11 | |
409 | mfxer r12 | |
410 | std r10,_LINK(r1) | |
411 | std r11,_CTR(r1) | |
412 | std r12,_XER(r1) | |
413 | SAVE_GPR(0,r1) | |
414 | SAVE_GPR(2,r1) | |
415 | SAVE_4GPRS(3,r1) | |
416 | SAVE_2GPRS(7,r1) | |
417 | SAVE_10GPRS(12,r1) | |
418 | SAVE_10GPRS(22,r1) | |
419 | lhz r12,PACA_TRAP_SAVE(r13) | |
420 | std r12,_TRAP(r1) | |
421 | addi r11,r1,INT_FRAME_SIZE | |
422 | std r11,0(r1) | |
423 | li r12,0 | |
424 | std r12,0(r11) | |
425 | ld r2,PACATOC(r13) | |
426 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
427 | bl .kernel_bad_stack | |
428 | b 1b | |
429 | ||
430 | /* | |
431 | * Here r13 points to the paca, r9 contains the saved CR, | |
432 | * SRR0 and SRR1 are saved in r11 and r12, | |
433 | * r9 - r13 are saved in paca->exgen. | |
434 | */ | |
435 | .align 7 | |
436 | .globl data_access_common | |
437 | data_access_common: | |
438 | mfspr r10,SPRN_DAR | |
439 | std r10,PACA_EXGEN+EX_DAR(r13) | |
440 | mfspr r10,SPRN_DSISR | |
441 | stw r10,PACA_EXGEN+EX_DSISR(r13) | |
442 | EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN) | |
443 | ld r3,PACA_EXGEN+EX_DAR(r13) | |
444 | lwz r4,PACA_EXGEN+EX_DSISR(r13) | |
445 | li r5,0x300 | |
446 | b .do_hash_page /* Try to handle as hpte fault */ | |
447 | ||
448 | .align 7 | |
449 | .globl instruction_access_common | |
450 | instruction_access_common: | |
451 | EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN) | |
452 | ld r3,_NIP(r1) | |
453 | andis. r4,r12,0x5820 | |
454 | li r5,0x400 | |
455 | b .do_hash_page /* Try to handle as hpte fault */ | |
456 | ||
457 | /* | |
458 | * Here is the common SLB miss user that is used when going to virtual | |
459 | * mode for SLB misses, that is currently not used | |
460 | */ | |
461 | #ifdef __DISABLED__ | |
462 | .align 7 | |
463 | .globl slb_miss_user_common | |
464 | slb_miss_user_common: | |
465 | mflr r10 | |
466 | std r3,PACA_EXGEN+EX_DAR(r13) | |
467 | stw r9,PACA_EXGEN+EX_CCR(r13) | |
468 | std r10,PACA_EXGEN+EX_LR(r13) | |
469 | std r11,PACA_EXGEN+EX_SRR0(r13) | |
470 | bl .slb_allocate_user | |
471 | ||
472 | ld r10,PACA_EXGEN+EX_LR(r13) | |
473 | ld r3,PACA_EXGEN+EX_R3(r13) | |
474 | lwz r9,PACA_EXGEN+EX_CCR(r13) | |
475 | ld r11,PACA_EXGEN+EX_SRR0(r13) | |
476 | mtlr r10 | |
477 | beq- slb_miss_fault | |
478 | ||
479 | andi. r10,r12,MSR_RI /* check for unrecoverable exception */ | |
480 | beq- unrecov_user_slb | |
481 | mfmsr r10 | |
482 | ||
483 | .machine push | |
484 | .machine "power4" | |
485 | mtcrf 0x80,r9 | |
486 | .machine pop | |
487 | ||
488 | clrrdi r10,r10,2 /* clear RI before setting SRR0/1 */ | |
489 | mtmsrd r10,1 | |
490 | ||
491 | mtspr SRR0,r11 | |
492 | mtspr SRR1,r12 | |
493 | ||
494 | ld r9,PACA_EXGEN+EX_R9(r13) | |
495 | ld r10,PACA_EXGEN+EX_R10(r13) | |
496 | ld r11,PACA_EXGEN+EX_R11(r13) | |
497 | ld r12,PACA_EXGEN+EX_R12(r13) | |
498 | ld r13,PACA_EXGEN+EX_R13(r13) | |
499 | rfid | |
500 | b . | |
501 | ||
502 | slb_miss_fault: | |
503 | EXCEPTION_PROLOG_COMMON(0x380, PACA_EXGEN) | |
504 | ld r4,PACA_EXGEN+EX_DAR(r13) | |
505 | li r5,0 | |
506 | std r4,_DAR(r1) | |
507 | std r5,_DSISR(r1) | |
508 | b handle_page_fault | |
509 | ||
510 | unrecov_user_slb: | |
511 | EXCEPTION_PROLOG_COMMON(0x4200, PACA_EXGEN) | |
512 | DISABLE_INTS | |
513 | bl .save_nvgprs | |
514 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
515 | bl .unrecoverable_exception | |
516 | b 1b | |
517 | ||
518 | #endif /* __DISABLED__ */ | |
519 | ||
520 | ||
521 | /* | |
522 | * r13 points to the PACA, r9 contains the saved CR, | |
523 | * r12 contain the saved SRR1, SRR0 is still ready for return | |
524 | * r3 has the faulting address | |
525 | * r9 - r13 are saved in paca->exslb. | |
526 | * r3 is saved in paca->slb_r3 | |
527 | * We assume we aren't going to take any exceptions during this procedure. | |
528 | */ | |
529 | _GLOBAL(slb_miss_realmode) | |
530 | mflr r10 | |
531 | #ifdef CONFIG_RELOCATABLE | |
532 | mtctr r11 | |
533 | #endif | |
534 | ||
535 | stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */ | |
536 | std r10,PACA_EXSLB+EX_LR(r13) /* save LR */ | |
537 | ||
538 | bl .slb_allocate_realmode | |
539 | ||
540 | /* All done -- return from exception. */ | |
541 | ||
542 | ld r10,PACA_EXSLB+EX_LR(r13) | |
543 | ld r3,PACA_EXSLB+EX_R3(r13) | |
544 | lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */ | |
545 | #ifdef CONFIG_PPC_ISERIES | |
546 | BEGIN_FW_FTR_SECTION | |
547 | ld r11,PACALPPACAPTR(r13) | |
548 | ld r11,LPPACASRR0(r11) /* get SRR0 value */ | |
549 | END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) | |
550 | #endif /* CONFIG_PPC_ISERIES */ | |
551 | ||
552 | mtlr r10 | |
553 | ||
554 | andi. r10,r12,MSR_RI /* check for unrecoverable exception */ | |
555 | beq- 2f | |
556 | ||
557 | .machine push | |
558 | .machine "power4" | |
559 | mtcrf 0x80,r9 | |
560 | mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */ | |
561 | .machine pop | |
562 | ||
563 | #ifdef CONFIG_PPC_ISERIES | |
564 | BEGIN_FW_FTR_SECTION | |
565 | mtspr SPRN_SRR0,r11 | |
566 | mtspr SPRN_SRR1,r12 | |
567 | END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) | |
568 | #endif /* CONFIG_PPC_ISERIES */ | |
569 | ld r9,PACA_EXSLB+EX_R9(r13) | |
570 | ld r10,PACA_EXSLB+EX_R10(r13) | |
571 | ld r11,PACA_EXSLB+EX_R11(r13) | |
572 | ld r12,PACA_EXSLB+EX_R12(r13) | |
573 | ld r13,PACA_EXSLB+EX_R13(r13) | |
574 | rfid | |
575 | b . /* prevent speculative execution */ | |
576 | ||
577 | 2: | |
578 | #ifdef CONFIG_PPC_ISERIES | |
579 | BEGIN_FW_FTR_SECTION | |
580 | b unrecov_slb | |
581 | END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) | |
582 | #endif /* CONFIG_PPC_ISERIES */ | |
583 | mfspr r11,SPRN_SRR0 | |
584 | ld r10,PACAKBASE(r13) | |
585 | LOAD_HANDLER(r10,unrecov_slb) | |
586 | mtspr SPRN_SRR0,r10 | |
587 | ld r10,PACAKMSR(r13) | |
588 | mtspr SPRN_SRR1,r10 | |
589 | rfid | |
590 | b . | |
591 | ||
592 | unrecov_slb: | |
593 | EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB) | |
594 | DISABLE_INTS | |
595 | bl .save_nvgprs | |
596 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
597 | bl .unrecoverable_exception | |
598 | b 1b | |
599 | ||
600 | .align 7 | |
601 | .globl hardware_interrupt_common | |
602 | .globl hardware_interrupt_entry | |
603 | hardware_interrupt_common: | |
604 | EXCEPTION_PROLOG_COMMON(0x500, PACA_EXGEN) | |
605 | FINISH_NAP | |
606 | hardware_interrupt_entry: | |
607 | DISABLE_INTS | |
608 | BEGIN_FTR_SECTION | |
609 | bl .ppc64_runlatch_on | |
610 | END_FTR_SECTION_IFSET(CPU_FTR_CTRL) | |
611 | addi r3,r1,STACK_FRAME_OVERHEAD | |
612 | bl .do_IRQ | |
613 | b .ret_from_except_lite | |
614 | ||
615 | #ifdef CONFIG_PPC_970_NAP | |
616 | power4_fixup_nap: | |
617 | andc r9,r9,r10 | |
618 | std r9,TI_LOCAL_FLAGS(r11) | |
619 | ld r10,_LINK(r1) /* make idle task do the */ | |
620 | std r10,_NIP(r1) /* equivalent of a blr */ | |
621 | blr | |
622 | #endif | |
623 | ||
624 | .align 7 | |
625 | .globl alignment_common | |
626 | alignment_common: | |
627 | mfspr r10,SPRN_DAR | |
628 | std r10,PACA_EXGEN+EX_DAR(r13) | |
629 | mfspr r10,SPRN_DSISR | |
630 | stw r10,PACA_EXGEN+EX_DSISR(r13) | |
631 | EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN) | |
632 | ld r3,PACA_EXGEN+EX_DAR(r13) | |
633 | lwz r4,PACA_EXGEN+EX_DSISR(r13) | |
634 | std r3,_DAR(r1) | |
635 | std r4,_DSISR(r1) | |
636 | bl .save_nvgprs | |
637 | addi r3,r1,STACK_FRAME_OVERHEAD | |
638 | ENABLE_INTS | |
639 | bl .alignment_exception | |
640 | b .ret_from_except | |
641 | ||
642 | .align 7 | |
643 | .globl program_check_common | |
644 | program_check_common: | |
645 | EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN) | |
646 | bl .save_nvgprs | |
647 | addi r3,r1,STACK_FRAME_OVERHEAD | |
648 | ENABLE_INTS | |
649 | bl .program_check_exception | |
650 | b .ret_from_except | |
651 | ||
652 | .align 7 | |
653 | .globl fp_unavailable_common | |
654 | fp_unavailable_common: | |
655 | EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN) | |
656 | bne 1f /* if from user, just load it up */ | |
657 | bl .save_nvgprs | |
658 | addi r3,r1,STACK_FRAME_OVERHEAD | |
659 | ENABLE_INTS | |
660 | bl .kernel_fp_unavailable_exception | |
661 | BUG_OPCODE | |
662 | 1: bl .load_up_fpu | |
663 | b fast_exception_return | |
664 | ||
665 | .align 7 | |
666 | .globl altivec_unavailable_common | |
667 | altivec_unavailable_common: | |
668 | EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN) | |
669 | #ifdef CONFIG_ALTIVEC | |
670 | BEGIN_FTR_SECTION | |
671 | beq 1f | |
672 | bl .load_up_altivec | |
673 | b fast_exception_return | |
674 | 1: | |
675 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |
676 | #endif | |
677 | bl .save_nvgprs | |
678 | addi r3,r1,STACK_FRAME_OVERHEAD | |
679 | ENABLE_INTS | |
680 | bl .altivec_unavailable_exception | |
681 | b .ret_from_except | |
682 | ||
683 | .align 7 | |
684 | .globl vsx_unavailable_common | |
685 | vsx_unavailable_common: | |
686 | EXCEPTION_PROLOG_COMMON(0xf40, PACA_EXGEN) | |
687 | #ifdef CONFIG_VSX | |
688 | BEGIN_FTR_SECTION | |
689 | bne .load_up_vsx | |
690 | 1: | |
691 | END_FTR_SECTION_IFSET(CPU_FTR_VSX) | |
692 | #endif | |
693 | bl .save_nvgprs | |
694 | addi r3,r1,STACK_FRAME_OVERHEAD | |
695 | ENABLE_INTS | |
696 | bl .vsx_unavailable_exception | |
697 | b .ret_from_except | |
698 | ||
699 | .align 7 | |
700 | .globl __end_handlers | |
701 | __end_handlers: | |
702 | ||
703 | /* | |
704 | * Return from an exception with minimal checks. | |
705 | * The caller is assumed to have done EXCEPTION_PROLOG_COMMON. | |
706 | * If interrupts have been enabled, or anything has been | |
707 | * done that might have changed the scheduling status of | |
708 | * any task or sent any task a signal, you should use | |
709 | * ret_from_except or ret_from_except_lite instead of this. | |
710 | */ | |
711 | fast_exc_return_irq: /* restores irq state too */ | |
712 | ld r3,SOFTE(r1) | |
713 | TRACE_AND_RESTORE_IRQ(r3); | |
714 | ld r12,_MSR(r1) | |
715 | rldicl r4,r12,49,63 /* get MSR_EE to LSB */ | |
716 | stb r4,PACAHARDIRQEN(r13) /* restore paca->hard_enabled */ | |
717 | b 1f | |
718 | ||
719 | .globl fast_exception_return | |
720 | fast_exception_return: | |
721 | ld r12,_MSR(r1) | |
722 | 1: ld r11,_NIP(r1) | |
723 | andi. r3,r12,MSR_RI /* check if RI is set */ | |
724 | beq- unrecov_fer | |
725 | ||
726 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING | |
727 | andi. r3,r12,MSR_PR | |
728 | beq 2f | |
729 | ACCOUNT_CPU_USER_EXIT(r3, r4) | |
730 | 2: | |
731 | #endif | |
732 | ||
733 | ld r3,_CCR(r1) | |
734 | ld r4,_LINK(r1) | |
735 | ld r5,_CTR(r1) | |
736 | ld r6,_XER(r1) | |
737 | mtcr r3 | |
738 | mtlr r4 | |
739 | mtctr r5 | |
740 | mtxer r6 | |
741 | REST_GPR(0, r1) | |
742 | REST_8GPRS(2, r1) | |
743 | ||
744 | mfmsr r10 | |
745 | rldicl r10,r10,48,1 /* clear EE */ | |
746 | rldicr r10,r10,16,61 /* clear RI (LE is 0 already) */ | |
747 | mtmsrd r10,1 | |
748 | ||
749 | mtspr SPRN_SRR1,r12 | |
750 | mtspr SPRN_SRR0,r11 | |
751 | REST_4GPRS(10, r1) | |
752 | ld r1,GPR1(r1) | |
753 | rfid | |
754 | b . /* prevent speculative execution */ | |
755 | ||
756 | unrecov_fer: | |
757 | bl .save_nvgprs | |
758 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
759 | bl .unrecoverable_exception | |
760 | b 1b | |
761 | ||
762 | ||
763 | /* | |
764 | * Hash table stuff | |
765 | */ | |
766 | .align 7 | |
767 | _STATIC(do_hash_page) | |
768 | std r3,_DAR(r1) | |
769 | std r4,_DSISR(r1) | |
770 | ||
9c7cc234 | 771 | andis. r0,r4,0xa410 /* weird error? */ |
0ebc4cda | 772 | bne- handle_page_fault /* if not, try to insert a HPTE */ |
9c7cc234 P |
773 | andis. r0,r4,DSISR_DABRMATCH@h |
774 | bne- handle_dabr_fault | |
775 | ||
0ebc4cda BH |
776 | BEGIN_FTR_SECTION |
777 | andis. r0,r4,0x0020 /* Is it a segment table fault? */ | |
778 | bne- do_ste_alloc /* If so handle it */ | |
779 | END_FTR_SECTION_IFCLR(CPU_FTR_SLB) | |
780 | ||
9c1e1052 PM |
781 | clrrdi r11,r1,THREAD_SHIFT |
782 | lwz r0,TI_PREEMPT(r11) /* If we're in an "NMI" */ | |
783 | andis. r0,r0,NMI_MASK@h /* (i.e. an irq when soft-disabled) */ | |
784 | bne 77f /* then don't call hash_page now */ | |
785 | ||
0ebc4cda BH |
786 | /* |
787 | * On iSeries, we soft-disable interrupts here, then | |
788 | * hard-enable interrupts so that the hash_page code can spin on | |
789 | * the hash_table_lock without problems on a shared processor. | |
790 | */ | |
791 | DISABLE_INTS | |
792 | ||
793 | /* | |
794 | * Currently, trace_hardirqs_off() will be called by DISABLE_INTS | |
795 | * and will clobber volatile registers when irq tracing is enabled | |
796 | * so we need to reload them. It may be possible to be smarter here | |
797 | * and move the irq tracing elsewhere but let's keep it simple for | |
798 | * now | |
799 | */ | |
800 | #ifdef CONFIG_TRACE_IRQFLAGS | |
801 | ld r3,_DAR(r1) | |
802 | ld r4,_DSISR(r1) | |
803 | ld r5,_TRAP(r1) | |
804 | ld r12,_MSR(r1) | |
805 | clrrdi r5,r5,4 | |
806 | #endif /* CONFIG_TRACE_IRQFLAGS */ | |
807 | /* | |
808 | * We need to set the _PAGE_USER bit if MSR_PR is set or if we are | |
809 | * accessing a userspace segment (even from the kernel). We assume | |
810 | * kernel addresses always have the high bit set. | |
811 | */ | |
812 | rlwinm r4,r4,32-25+9,31-9,31-9 /* DSISR_STORE -> _PAGE_RW */ | |
813 | rotldi r0,r3,15 /* Move high bit into MSR_PR posn */ | |
814 | orc r0,r12,r0 /* MSR_PR | ~high_bit */ | |
815 | rlwimi r4,r0,32-13,30,30 /* becomes _PAGE_USER access bit */ | |
816 | ori r4,r4,1 /* add _PAGE_PRESENT */ | |
817 | rlwimi r4,r5,22+2,31-2,31-2 /* Set _PAGE_EXEC if trap is 0x400 */ | |
818 | ||
819 | /* | |
820 | * r3 contains the faulting address | |
821 | * r4 contains the required access permissions | |
822 | * r5 contains the trap number | |
823 | * | |
824 | * at return r3 = 0 for success | |
825 | */ | |
826 | bl .hash_page /* build HPTE if possible */ | |
827 | cmpdi r3,0 /* see if hash_page succeeded */ | |
828 | ||
829 | BEGIN_FW_FTR_SECTION | |
830 | /* | |
831 | * If we had interrupts soft-enabled at the point where the | |
832 | * DSI/ISI occurred, and an interrupt came in during hash_page, | |
833 | * handle it now. | |
834 | * We jump to ret_from_except_lite rather than fast_exception_return | |
835 | * because ret_from_except_lite will check for and handle pending | |
836 | * interrupts if necessary. | |
837 | */ | |
838 | beq 13f | |
839 | END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) | |
840 | ||
841 | BEGIN_FW_FTR_SECTION | |
842 | /* | |
843 | * Here we have interrupts hard-disabled, so it is sufficient | |
844 | * to restore paca->{soft,hard}_enable and get out. | |
845 | */ | |
846 | beq fast_exc_return_irq /* Return from exception on success */ | |
847 | END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES) | |
848 | ||
849 | /* For a hash failure, we don't bother re-enabling interrupts */ | |
850 | ble- 12f | |
851 | ||
852 | /* | |
853 | * hash_page couldn't handle it, set soft interrupt enable back | |
df9ee292 | 854 | * to what it was before the trap. Note that .arch_local_irq_restore |
0ebc4cda BH |
855 | * handles any interrupts pending at this point. |
856 | */ | |
857 | ld r3,SOFTE(r1) | |
858 | TRACE_AND_RESTORE_IRQ_PARTIAL(r3, 11f) | |
df9ee292 | 859 | bl .arch_local_irq_restore |
0ebc4cda BH |
860 | b 11f |
861 | ||
9c7cc234 P |
862 | /* We have a data breakpoint exception - handle it */ |
863 | handle_dabr_fault: | |
5aae8a53 | 864 | bl .save_nvgprs |
9c7cc234 P |
865 | ld r4,_DAR(r1) |
866 | ld r5,_DSISR(r1) | |
867 | addi r3,r1,STACK_FRAME_OVERHEAD | |
868 | bl .do_dabr | |
869 | b .ret_from_except_lite | |
870 | ||
0ebc4cda BH |
871 | /* Here we have a page fault that hash_page can't handle. */ |
872 | handle_page_fault: | |
873 | ENABLE_INTS | |
874 | 11: ld r4,_DAR(r1) | |
875 | ld r5,_DSISR(r1) | |
876 | addi r3,r1,STACK_FRAME_OVERHEAD | |
877 | bl .do_page_fault | |
878 | cmpdi r3,0 | |
879 | beq+ 13f | |
880 | bl .save_nvgprs | |
881 | mr r5,r3 | |
882 | addi r3,r1,STACK_FRAME_OVERHEAD | |
883 | lwz r4,_DAR(r1) | |
884 | bl .bad_page_fault | |
885 | b .ret_from_except | |
886 | ||
887 | 13: b .ret_from_except_lite | |
888 | ||
889 | /* We have a page fault that hash_page could handle but HV refused | |
890 | * the PTE insertion | |
891 | */ | |
892 | 12: bl .save_nvgprs | |
893 | mr r5,r3 | |
894 | addi r3,r1,STACK_FRAME_OVERHEAD | |
895 | ld r4,_DAR(r1) | |
896 | bl .low_hash_fault | |
897 | b .ret_from_except | |
898 | ||
9c1e1052 PM |
899 | /* |
900 | * We come here as a result of a DSI at a point where we don't want | |
901 | * to call hash_page, such as when we are accessing memory (possibly | |
902 | * user memory) inside a PMU interrupt that occurred while interrupts | |
903 | * were soft-disabled. We want to invoke the exception handler for | |
904 | * the access, or panic if there isn't a handler. | |
905 | */ | |
906 | 77: bl .save_nvgprs | |
907 | mr r4,r3 | |
908 | addi r3,r1,STACK_FRAME_OVERHEAD | |
909 | li r5,SIGSEGV | |
910 | bl .bad_page_fault | |
911 | b .ret_from_except | |
912 | ||
0ebc4cda BH |
913 | /* here we have a segment miss */ |
914 | do_ste_alloc: | |
915 | bl .ste_allocate /* try to insert stab entry */ | |
916 | cmpdi r3,0 | |
917 | bne- handle_page_fault | |
918 | b fast_exception_return | |
919 | ||
920 | /* | |
921 | * r13 points to the PACA, r9 contains the saved CR, | |
922 | * r11 and r12 contain the saved SRR0 and SRR1. | |
923 | * r9 - r13 are saved in paca->exslb. | |
924 | * We assume we aren't going to take any exceptions during this procedure. | |
925 | * We assume (DAR >> 60) == 0xc. | |
926 | */ | |
927 | .align 7 | |
928 | _GLOBAL(do_stab_bolted) | |
929 | stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */ | |
930 | std r11,PACA_EXSLB+EX_SRR0(r13) /* save SRR0 in exc. frame */ | |
931 | ||
932 | /* Hash to the primary group */ | |
933 | ld r10,PACASTABVIRT(r13) | |
934 | mfspr r11,SPRN_DAR | |
935 | srdi r11,r11,28 | |
936 | rldimi r10,r11,7,52 /* r10 = first ste of the group */ | |
937 | ||
938 | /* Calculate VSID */ | |
939 | /* This is a kernel address, so protovsid = ESID */ | |
940 | ASM_VSID_SCRAMBLE(r11, r9, 256M) | |
941 | rldic r9,r11,12,16 /* r9 = vsid << 12 */ | |
942 | ||
943 | /* Search the primary group for a free entry */ | |
944 | 1: ld r11,0(r10) /* Test valid bit of the current ste */ | |
945 | andi. r11,r11,0x80 | |
946 | beq 2f | |
947 | addi r10,r10,16 | |
948 | andi. r11,r10,0x70 | |
949 | bne 1b | |
950 | ||
951 | /* Stick for only searching the primary group for now. */ | |
952 | /* At least for now, we use a very simple random castout scheme */ | |
953 | /* Use the TB as a random number ; OR in 1 to avoid entry 0 */ | |
954 | mftb r11 | |
955 | rldic r11,r11,4,57 /* r11 = (r11 << 4) & 0x70 */ | |
956 | ori r11,r11,0x10 | |
957 | ||
958 | /* r10 currently points to an ste one past the group of interest */ | |
959 | /* make it point to the randomly selected entry */ | |
960 | subi r10,r10,128 | |
961 | or r10,r10,r11 /* r10 is the entry to invalidate */ | |
962 | ||
963 | isync /* mark the entry invalid */ | |
964 | ld r11,0(r10) | |
965 | rldicl r11,r11,56,1 /* clear the valid bit */ | |
966 | rotldi r11,r11,8 | |
967 | std r11,0(r10) | |
968 | sync | |
969 | ||
970 | clrrdi r11,r11,28 /* Get the esid part of the ste */ | |
971 | slbie r11 | |
972 | ||
973 | 2: std r9,8(r10) /* Store the vsid part of the ste */ | |
974 | eieio | |
975 | ||
976 | mfspr r11,SPRN_DAR /* Get the new esid */ | |
977 | clrrdi r11,r11,28 /* Permits a full 32b of ESID */ | |
978 | ori r11,r11,0x90 /* Turn on valid and kp */ | |
979 | std r11,0(r10) /* Put new entry back into the stab */ | |
980 | ||
981 | sync | |
982 | ||
983 | /* All done -- return from exception. */ | |
984 | lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */ | |
985 | ld r11,PACA_EXSLB+EX_SRR0(r13) /* get saved SRR0 */ | |
986 | ||
987 | andi. r10,r12,MSR_RI | |
988 | beq- unrecov_slb | |
989 | ||
990 | mtcrf 0x80,r9 /* restore CR */ | |
991 | ||
992 | mfmsr r10 | |
993 | clrrdi r10,r10,2 | |
994 | mtmsrd r10,1 | |
995 | ||
996 | mtspr SPRN_SRR0,r11 | |
997 | mtspr SPRN_SRR1,r12 | |
998 | ld r9,PACA_EXSLB+EX_R9(r13) | |
999 | ld r10,PACA_EXSLB+EX_R10(r13) | |
1000 | ld r11,PACA_EXSLB+EX_R11(r13) | |
1001 | ld r12,PACA_EXSLB+EX_R12(r13) | |
1002 | ld r13,PACA_EXSLB+EX_R13(r13) | |
1003 | rfid | |
1004 | b . /* prevent speculative execution */ | |
1005 | ||
0ebc4cda BH |
1006 | #ifdef CONFIG_PPC_PSERIES |
1007 | /* | |
1008 | * Data area reserved for FWNMI option. | |
1009 | * This address (0x7000) is fixed by the RPA. | |
1010 | */ | |
1011 | .= 0x7000 | |
1012 | .globl fwnmi_data_area | |
1013 | fwnmi_data_area: | |
1014 | #endif /* CONFIG_PPC_PSERIES */ | |
1015 | ||
1016 | /* iSeries does not use the FWNMI stuff, so it is safe to put | |
1017 | * this here, even if we later allow kernels that will boot on | |
1018 | * both pSeries and iSeries */ | |
1019 | #ifdef CONFIG_PPC_ISERIES | |
1020 | . = LPARMAP_PHYS | |
1021 | .globl xLparMap | |
1022 | xLparMap: | |
1023 | .quad HvEsidsToMap /* xNumberEsids */ | |
1024 | .quad HvRangesToMap /* xNumberRanges */ | |
1025 | .quad STAB0_PAGE /* xSegmentTableOffs */ | |
1026 | .zero 40 /* xRsvd */ | |
1027 | /* xEsids (HvEsidsToMap entries of 2 quads) */ | |
1028 | .quad PAGE_OFFSET_ESID /* xKernelEsid */ | |
1029 | .quad PAGE_OFFSET_VSID /* xKernelVsid */ | |
1030 | .quad VMALLOC_START_ESID /* xKernelEsid */ | |
1031 | .quad VMALLOC_START_VSID /* xKernelVsid */ | |
1032 | /* xRanges (HvRangesToMap entries of 3 quads) */ | |
1033 | .quad HvPagesToMap /* xPages */ | |
1034 | .quad 0 /* xOffset */ | |
1035 | .quad PAGE_OFFSET_VSID << (SID_SHIFT - HW_PAGE_SHIFT) /* xVPN */ | |
1036 | ||
1037 | #endif /* CONFIG_PPC_ISERIES */ | |
1038 | ||
1039 | #ifdef CONFIG_PPC_PSERIES | |
1040 | . = 0x8000 | |
1041 | #endif /* CONFIG_PPC_PSERIES */ | |
84493804 BH |
1042 | |
1043 | /* | |
1044 | * Space for CPU0's segment table. | |
1045 | * | |
1046 | * On iSeries, the hypervisor must fill in at least one entry before | |
1047 | * we get control (with relocate on). The address is given to the hv | |
1048 | * as a page number (see xLparMap above), so this must be at a | |
1049 | * fixed address (the linker can't compute (u64)&initial_stab >> | |
1050 | * PAGE_SHIFT). | |
1051 | */ | |
1052 | . = STAB0_OFFSET /* 0x8000 */ | |
1053 | .globl initial_stab | |
1054 | initial_stab: | |
1055 | .space 4096 |