[mirror_ubuntu-zesty-kernel.git] / drivers / hwtracing / coresight / coresight-etm4x.h

/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#ifndef _CORESIGHT_CORESIGHT_ETM_H
#define _CORESIGHT_CORESIGHT_ETM_H

#include <asm/local.h>
#include <linux/spinlock.h>
#include "coresight-priv.h"

/*
 * Device registers:
 * 0x000 - 0x2FC: Trace		registers
 * 0x300 - 0x314: Management	registers
 * 0x318 - 0xEFC: Trace		registers
 * 0xF00: Management		registers
 * 0xFA0 - 0xFA4: Trace		registers
 * 0xFA8 - 0xFFC: Management	registers
 */
/* Trace registers (0x000-0x2FC) */
/* Main control and configuration registers */
#define TRCPRGCTLR			0x004
#define TRCPROCSELR			0x008
#define TRCSTATR			0x00C
#define TRCCONFIGR			0x010
#define TRCAUXCTLR			0x018
#define TRCEVENTCTL0R			0x020
#define TRCEVENTCTL1R			0x024
#define TRCSTALLCTLR			0x02C
#define TRCTSCTLR			0x030
#define TRCSYNCPR			0x034
#define TRCCCCTLR			0x038
#define TRCBBCTLR			0x03C
#define TRCTRACEIDR			0x040
#define TRCQCTLR			0x044
/* Filtering control registers */
#define TRCVICTLR			0x080
#define TRCVIIECTLR			0x084
#define TRCVISSCTLR			0x088
#define TRCVIPCSSCTLR			0x08C
#define TRCVDCTLR			0x0A0
#define TRCVDSACCTLR			0x0A4
#define TRCVDARCCTLR			0x0A8
/* Derived resources registers */
#define TRCSEQEVRn(n)			(0x100 + (n * 4))
#define TRCSEQRSTEVR			0x118
#define TRCSEQSTR			0x11C
#define TRCEXTINSELR			0x120
#define TRCCNTRLDVRn(n)			(0x140 + (n * 4))
#define TRCCNTCTLRn(n)			(0x150 + (n * 4))
#define TRCCNTVRn(n)			(0x160 + (n * 4))
/* ID registers */
#define TRCIDR8				0x180
#define TRCIDR9				0x184
#define TRCIDR10			0x188
#define TRCIDR11			0x18C
#define TRCIDR12			0x190
#define TRCIDR13			0x194
#define TRCIMSPEC0			0x1C0
#define TRCIMSPECn(n)			(0x1C0 + (n * 4))
#define TRCIDR0				0x1E0
#define TRCIDR1				0x1E4
#define TRCIDR2				0x1E8
#define TRCIDR3				0x1EC
#define TRCIDR4				0x1F0
#define TRCIDR5				0x1F4
#define TRCIDR6				0x1F8
#define TRCIDR7				0x1FC
/* Resource selection registers */
#define TRCRSCTLRn(n)			(0x200 + (n * 4))
/* Single-shot comparator registers */
#define TRCSSCCRn(n)			(0x280 + (n * 4))
#define TRCSSCSRn(n)			(0x2A0 + (n * 4))
#define TRCSSPCICRn(n)			(0x2C0 + (n * 4))
/* Management registers (0x300-0x314) */
#define TRCOSLAR			0x300
#define TRCOSLSR			0x304
#define TRCPDCR				0x310
#define TRCPDSR				0x314
/* Trace registers (0x318-0xEFC) */
/* Comparator registers */
#define TRCACVRn(n)			(0x400 + (n * 8))
#define TRCACATRn(n)			(0x480 + (n * 8))
#define TRCDVCVRn(n)			(0x500 + (n * 16))
#define TRCDVCMRn(n)			(0x580 + (n * 16))
#define TRCCIDCVRn(n)			(0x600 + (n * 8))
#define TRCVMIDCVRn(n)			(0x640 + (n * 8))
#define TRCCIDCCTLR0			0x680
#define TRCCIDCCTLR1			0x684
#define TRCVMIDCCTLR0			0x688
#define TRCVMIDCCTLR1			0x68C
/* Management register (0xF00) */
/* Integration control registers */
#define TRCITCTRL			0xF00
/* Trace registers (0xFA0-0xFA4) */
/* Claim tag registers */
#define TRCCLAIMSET			0xFA0
#define TRCCLAIMCLR			0xFA4
/* Management registers (0xFA8-0xFFC) */
#define TRCDEVAFF0			0xFA8
#define TRCDEVAFF1			0xFAC
#define TRCLAR				0xFB0
#define TRCLSR				0xFB4
#define TRCAUTHSTATUS			0xFB8
#define TRCDEVARCH			0xFBC
#define TRCDEVID			0xFC8
#define TRCDEVTYPE			0xFCC
#define TRCPIDR4			0xFD0
#define TRCPIDR5			0xFD4
#define TRCPIDR6			0xFD8
#define TRCPIDR7			0xFDC
#define TRCPIDR0			0xFE0
#define TRCPIDR1			0xFE4
#define TRCPIDR2			0xFE8
#define TRCPIDR3			0xFEC
#define TRCCIDR0			0xFF0
#define TRCCIDR1			0xFF4
#define TRCCIDR2			0xFF8
#define TRCCIDR3			0xFFC

/* ETMv4 resources */
#define ETM_MAX_NR_PE			8
#define ETMv4_MAX_CNTR			4
#define ETM_MAX_SEQ_STATES		4
#define ETM_MAX_EXT_INP_SEL		4
#define ETM_MAX_EXT_INP			256
#define ETM_MAX_EXT_OUT			4
#define ETM_MAX_SINGLE_ADDR_CMP		16
#define ETM_MAX_ADDR_RANGE_CMP		(ETM_MAX_SINGLE_ADDR_CMP / 2)
#define ETM_MAX_DATA_VAL_CMP		8
#define ETMv4_MAX_CTXID_CMP		8
#define ETM_MAX_VMID_CMP		8
#define ETM_MAX_PE_CMP			8
#define ETM_MAX_RES_SEL			16
#define ETM_MAX_SS_CMP			8

#define ETM_ARCH_V4			0x40
#define ETMv4_SYNC_MASK			0x1F
#define ETM_CYC_THRESHOLD_MASK		0xFFF
#define ETMv4_EVENT_MASK		0xFF
#define ETM_CNTR_MAX_VAL		0xFFFF
#define ETM_TRACEID_MASK		0x3f

/* ETMv4 programming modes */
#define ETM_MODE_EXCLUDE		BIT(0)
#define ETM_MODE_LOAD			BIT(1)
#define ETM_MODE_STORE			BIT(2)
#define ETM_MODE_LOAD_STORE		BIT(3)
#define ETM_MODE_BB			BIT(4)
#define ETMv4_MODE_CYCACC		BIT(5)
#define ETMv4_MODE_CTXID		BIT(6)
#define ETM_MODE_VMID			BIT(7)
#define ETM_MODE_COND(val)		BMVAL(val, 8, 10)
#define ETMv4_MODE_TIMESTAMP		BIT(11)
#define ETM_MODE_RETURNSTACK		BIT(12)
#define ETM_MODE_QELEM(val)		BMVAL(val, 13, 14)
#define ETM_MODE_DATA_TRACE_ADDR	BIT(15)
#define ETM_MODE_DATA_TRACE_VAL		BIT(16)
#define ETM_MODE_ISTALL			BIT(17)
#define ETM_MODE_DSTALL			BIT(18)
#define ETM_MODE_ATB_TRIGGER		BIT(19)
#define ETM_MODE_LPOVERRIDE		BIT(20)
#define ETM_MODE_ISTALL_EN		BIT(21)
#define ETM_MODE_DSTALL_EN		BIT(22)
#define ETM_MODE_INSTPRIO		BIT(23)
#define ETM_MODE_NOOVERFLOW		BIT(24)
#define ETM_MODE_TRACE_RESET		BIT(25)
#define ETM_MODE_TRACE_ERR		BIT(26)
#define ETM_MODE_VIEWINST_STARTSTOP	BIT(27)
#define ETMv4_MODE_ALL			(GENMASK(27, 0) | \
					 ETM_MODE_EXCL_KERN | \
					 ETM_MODE_EXCL_USER)

#define TRCSTATR_IDLE_BIT		0
#define ETM_DEFAULT_ADDR_COMP		0

/* PowerDown Control Register bits */
#define TRCPDCR_PU			BIT(3)

/* secure state access levels */
#define ETM_EXLEVEL_S_APP		BIT(8)
#define ETM_EXLEVEL_S_OS		BIT(9)
#define ETM_EXLEVEL_S_NA		BIT(10)
#define ETM_EXLEVEL_S_HYP		BIT(11)
/* non-secure state access levels */
#define ETM_EXLEVEL_NS_APP		BIT(12)
#define ETM_EXLEVEL_NS_OS		BIT(13)
#define ETM_EXLEVEL_NS_HYP		BIT(14)
#define ETM_EXLEVEL_NS_NA		BIT(15)

/**
 * struct etmv4_config - configuration information related to an ETMv4
 * @mode:	Controls various modes supported by this ETM.
 * @pe_sel:	Controls which PE to trace.
 * @cfg:	Controls the tracing options.
 * @eventctrl0: Controls the tracing of arbitrary events.
 * @eventctrl1: Controls the behavior of the events that @event_ctrl0 selects.
 * @stallctl:	If functionality that prevents trace unit buffer overflows
 *		is available.
 * @ts_ctrl:	Controls the insertion of global timestamps in the
 *		trace streams.
 * @syncfreq:	Controls how often trace synchronization requests occur.
 *		the TRCCCCTLR register.
 * @ccctlr:	Sets the threshold value for cycle counting.
 * @vinst_ctrl:	Controls instruction trace filtering.
 * @viiectlr:	Set or read, the address range comparators.
 * @vissctlr:	Set, or read, the single address comparators that control the
 *		ViewInst start-stop logic.
 * @vipcssctlr:	Set, or read, which PE comparator inputs can control the
 *		ViewInst start-stop logic.
 * @seq_idx:	Sequencor index selector.
 * @seq_ctrl:	Control for the sequencer state transition control register.
 * @seq_rst:	Moves the sequencer to state 0 when a programmed event occurs.
 * @seq_state:	Set, or read the sequencer state.
 * @cntr_idx:	Counter index seletor.
 * @cntrldvr:	Sets or returns the reload count value for a counter.
 * @cntr_ctrl:	Controls the operation of a counter.
 * @cntr_val:	Sets or returns the value for a counter.
 * @res_idx:	Resource index selector.
 * @res_ctrl:	Controls the selection of the resources in the trace unit.
 * @ss_ctrl:	Controls the corresponding single-shot comparator resource.
 * @ss_status:	The status of the corresponding single-shot comparator.
 * @ss_pe_cmp:	Selects the PE comparator inputs for Single-shot control.
 * @addr_idx:	Address comparator index selector.
 * @addr_val:	Value for address comparator.
 * @addr_acc:	Address comparator access type.
 * @addr_type:	Current status of the comparator register.
 * @ctxid_idx:	Context ID index selector.
 * @ctxid_pid:	Value of the context ID comparator.
 * @ctxid_vpid:	Virtual PID seen by users if PID namespace is enabled, otherwise
 *		the same value of ctxid_pid.
 * @ctxid_mask0:Context ID comparator mask for comparator 0-3.
 * @ctxid_mask1:Context ID comparator mask for comparator 4-7.
 * @vmid_idx:	VM ID index selector.
 * @vmid_val:	Value of the VM ID comparator.
 * @vmid_mask0:	VM ID comparator mask for comparator 0-3.
 * @vmid_mask1:	VM ID comparator mask for comparator 4-7.
 * @ext_inp:	External input selection.
 */
struct etmv4_config {
	u32				mode;
	u32				pe_sel;
	u32				cfg;
	u32				eventctrl0;
	u32				eventctrl1;
	u32				stall_ctrl;
	u32				ts_ctrl;
	u32				syncfreq;
	u32				ccctlr;
	u32				bb_ctrl;
	u32				vinst_ctrl;
	u32				viiectlr;
	u32				vissctlr;
	u32				vipcssctlr;
	u8				seq_idx;
	u32				seq_ctrl[ETM_MAX_SEQ_STATES];
	u32				seq_rst;
	u32				seq_state;
	u8				cntr_idx;
	u32				cntrldvr[ETMv4_MAX_CNTR];
	u32				cntr_ctrl[ETMv4_MAX_CNTR];
	u32				cntr_val[ETMv4_MAX_CNTR];
	u8				res_idx;
	u32				res_ctrl[ETM_MAX_RES_SEL];
	u32				ss_ctrl[ETM_MAX_SS_CMP];
	u32				ss_status[ETM_MAX_SS_CMP];
	u32				ss_pe_cmp[ETM_MAX_SS_CMP];
	u8				addr_idx;
	u64				addr_val[ETM_MAX_SINGLE_ADDR_CMP];
	u64				addr_acc[ETM_MAX_SINGLE_ADDR_CMP];
	u8				addr_type[ETM_MAX_SINGLE_ADDR_CMP];
	u8				ctxid_idx;
	u64				ctxid_pid[ETMv4_MAX_CTXID_CMP];
	u64				ctxid_vpid[ETMv4_MAX_CTXID_CMP];
	u32				ctxid_mask0;
	u32				ctxid_mask1;
	u8				vmid_idx;
	u64				vmid_val[ETM_MAX_VMID_CMP];
	u32				vmid_mask0;
	u32				vmid_mask1;
	u32				ext_inp;
};

/**
 * struct etm4_drvdata - specifics associated to an ETM component
 * @base:       Memory mapped base address for this component.
 * @dev:        The device entity associated to this component.
 * @csdev:      Component vitals needed by the framework.
 * @spinlock:   Only one at a time pls.
 * @mode:	This tracer's mode, i.e sysFS, Perf or disabled.
 * @cpu:        The cpu this component is affined to.
 * @arch:       ETM version number.
 * @nr_pe:	The number of processing entity available for tracing.
 * @nr_pe_cmp:	The number of processing entity comparator inputs that are
 *		available for tracing.
 * @nr_addr_cmp:Number of pairs of address comparators available
 *		as found in ETMIDR4 0-3.
 * @nr_cntr:    Number of counters as found in ETMIDR5 bit 28-30.
 * @nr_ext_inp: Number of external input.
 * @numcidc:	Number of contextID comparators.
 * @numvmidc:	Number of VMID comparators.
 * @nrseqstate: The number of sequencer states that are implemented.
 * @nr_event:	Indicates how many events the trace unit support.
 * @nr_resource:The number of resource selection pairs available for tracing.
 * @nr_ss_cmp:	Number of single-shot comparator controls that are available.
 * @trcid:	value of the current ID for this component.
 * @trcid_size: Indicates the trace ID width.
 * @ts_size:	Global timestamp size field.
 * @ctxid_size:	Size of the context ID field to consider.
 * @vmid_size:	Size of the VM ID comparator to consider.
 * @ccsize:	Indicates the size of the cycle counter in bits.
 * @ccitmin:	minimum value that can be programmed in
 * @s_ex_level:	In secure state, indicates whether instruction tracing is
 *		supported for the corresponding Exception level.
 * @ns_ex_level:In non-secure state, indicates whether instruction tracing is
 *		supported for the corresponding Exception level.
 * @sticky_enable: true if ETM base configuration has been done.
 * @boot_enable:True if we should start tracing at boot time.
 * @os_unlock:  True if access to management registers is allowed.
 * @instrp0:	Tracing of load and store instructions
 *		as P0 elements is supported.
 * @trcbb:	Indicates if the trace unit supports branch broadcast tracing.
 * @trccond:	If the trace unit supports conditional
 *		instruction tracing.
 * @retstack:	Indicates if the implementation supports a return stack.
 * @trccci:	Indicates if the trace unit supports cycle counting
 *		for instruction.
 * @q_support:	Q element support characteristics.
 * @trc_error:	Whether a trace unit can trace a system
 *		error exception.
 * @syncpr:	Indicates if an implementation has a fixed
 *		synchronization period.
 * @stall_ctrl:	Enables trace unit functionality that prevents trace
 *		unit buffer overflows.
 * @sysstall:	Does the system support stall control of the PE?
 * @nooverflow:	Indicate if overflow prevention is supported.
 * @atbtrig:	If the implementation can support ATB triggers
 * @lpoverride:	If the implementation can support low-power state over.
 * @config:	structure holding configuration parameters.
 */
struct etmv4_drvdata {
	void __iomem			*base;
	struct device			*dev;
	struct coresight_device		*csdev;
	spinlock_t			spinlock;
	local_t				mode;
	int				cpu;
	u8				arch;
	u8				nr_pe;
	u8				nr_pe_cmp;
	u8				nr_addr_cmp;
	u8				nr_cntr;
	u8				nr_ext_inp;
	u8				numcidc;
	u8				numvmidc;
	u8				nrseqstate;
	u8				nr_event;
	u8				nr_resource;
	u8				nr_ss_cmp;
	u8				trcid;
	u8				trcid_size;
	u8				ts_size;
	u8				ctxid_size;
	u8				vmid_size;
	u8				ccsize;
	u8				ccitmin;
	u8				s_ex_level;
	u8				ns_ex_level;
	u8				q_support;
	bool				sticky_enable;
	bool				boot_enable;
	bool				os_unlock;
	bool				instrp0;
	bool				trcbb;
	bool				trccond;
	bool				retstack;
	bool				trccci;
	bool				trc_error;
	bool				syncpr;
	bool				stallctl;
	bool				sysstall;
	bool				nooverflow;
	bool				atbtrig;
	bool				lpoverride;
	struct etmv4_config		config;
};

/* Address comparator access types */
enum etm_addr_acctype {
	ETM_INSTR_ADDR,
	ETM_DATA_LOAD_ADDR,
	ETM_DATA_STORE_ADDR,
	ETM_DATA_LOAD_STORE_ADDR,
};

/* Address comparator context types */
enum etm_addr_ctxtype {
	ETM_CTX_NONE,
	ETM_CTX_CTXID,
	ETM_CTX_VMID,
	ETM_CTX_CTXID_VMID,
};

enum etm_addr_type {
	ETM_ADDR_TYPE_NONE,
	ETM_ADDR_TYPE_SINGLE,
	ETM_ADDR_TYPE_RANGE,
	ETM_ADDR_TYPE_START,
	ETM_ADDR_TYPE_STOP,
};

extern const struct attribute_group *coresight_etmv4_groups[];
void etm4_config_trace_mode(struct etmv4_config *config);
#endif
Commit	Line	Data
2e1cdfe1 PP	1	/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
	2	*
	3	* This program is free software; you can redistribute it and/or modify
	4	* it under the terms of the GNU General Public License version 2 and
	5	* only version 2 as published by the Free Software Foundation.
	6	*
	7	* This program is distributed in the hope that it will be useful,
	8	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	9	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	10	* GNU General Public License for more details.
	11	*/
	12
	13	#ifndef _CORESIGHT_CORESIGHT_ETM_H
	14	#define _CORESIGHT_CORESIGHT_ETM_H
	15
c38a9ec2	16	#include <asm/local.h>
2e1cdfe1 PP	17	#include <linux/spinlock.h>
	18	#include "coresight-priv.h"
	19
	20	/*
	21	* Device registers:
	22	* 0x000 - 0x2FC: Trace registers
	23	* 0x300 - 0x314: Management registers
	24	* 0x318 - 0xEFC: Trace registers
	25	* 0xF00: Management registers
	26	* 0xFA0 - 0xFA4: Trace registers
	27	* 0xFA8 - 0xFFC: Management registers
	28	*/
	29	/* Trace registers (0x000-0x2FC) */
	30	/* Main control and configuration registers */
	31	#define TRCPRGCTLR 0x004
	32	#define TRCPROCSELR 0x008
	33	#define TRCSTATR 0x00C
	34	#define TRCCONFIGR 0x010
	35	#define TRCAUXCTLR 0x018
	36	#define TRCEVENTCTL0R 0x020
	37	#define TRCEVENTCTL1R 0x024
	38	#define TRCSTALLCTLR 0x02C
	39	#define TRCTSCTLR 0x030
	40	#define TRCSYNCPR 0x034
	41	#define TRCCCCTLR 0x038
	42	#define TRCBBCTLR 0x03C
	43	#define TRCTRACEIDR 0x040
	44	#define TRCQCTLR 0x044
	45	/* Filtering control registers */
	46	#define TRCVICTLR 0x080
	47	#define TRCVIIECTLR 0x084
	48	#define TRCVISSCTLR 0x088
	49	#define TRCVIPCSSCTLR 0x08C
	50	#define TRCVDCTLR 0x0A0
	51	#define TRCVDSACCTLR 0x0A4
	52	#define TRCVDARCCTLR 0x0A8
	53	/* Derived resources registers */
	54	#define TRCSEQEVRn(n) (0x100 + (n * 4))
	55	#define TRCSEQRSTEVR 0x118
	56	#define TRCSEQSTR 0x11C
	57	#define TRCEXTINSELR 0x120
	58	#define TRCCNTRLDVRn(n) (0x140 + (n * 4))
	59	#define TRCCNTCTLRn(n) (0x150 + (n * 4))
	60	#define TRCCNTVRn(n) (0x160 + (n * 4))
	61	/* ID registers */
	62	#define TRCIDR8 0x180
	63	#define TRCIDR9 0x184
	64	#define TRCIDR10 0x188
	65	#define TRCIDR11 0x18C
	66	#define TRCIDR12 0x190
	67	#define TRCIDR13 0x194
	68	#define TRCIMSPEC0 0x1C0
	69	#define TRCIMSPECn(n) (0x1C0 + (n * 4))
	70	#define TRCIDR0 0x1E0
	71	#define TRCIDR1 0x1E4
	72	#define TRCIDR2 0x1E8
	73	#define TRCIDR3 0x1EC
	74	#define TRCIDR4 0x1F0
	75	#define TRCIDR5 0x1F4
	76	#define TRCIDR6 0x1F8
	77	#define TRCIDR7 0x1FC
	78	/* Resource selection registers */
	79	#define TRCRSCTLRn(n) (0x200 + (n * 4))
	80	/* Single-shot comparator registers */
81	#define TRCSSCCRn(n) (0x280 + (n * 4))
82	#define TRCSSCSRn(n) (0x2A0 + (n * 4))
83	#define TRCSSPCICRn(n) (0x2C0 + (n * 4))
84	/* Management registers (0x300-0x314) */
85	#define TRCOSLAR 0x300
86	#define TRCOSLSR 0x304
87	#define TRCPDCR 0x310
88	#define TRCPDSR 0x314
89	/* Trace registers (0x318-0xEFC) */
90	/* Comparator registers */
91	#define TRCACVRn(n) (0x400 + (n * 8))
92	#define TRCACATRn(n) (0x480 + (n * 8))
93	#define TRCDVCVRn(n) (0x500 + (n * 16))
94	#define TRCDVCMRn(n) (0x580 + (n * 16))
95	#define TRCCIDCVRn(n) (0x600 + (n * 8))
96	#define TRCVMIDCVRn(n) (0x640 + (n * 8))
97	#define TRCCIDCCTLR0 0x680
98	#define TRCCIDCCTLR1 0x684
99	#define TRCVMIDCCTLR0 0x688
100	#define TRCVMIDCCTLR1 0x68C
101	/* Management register (0xF00) */
102	/* Integration control registers */
103	#define TRCITCTRL 0xF00
104	/* Trace registers (0xFA0-0xFA4) */
105	/* Claim tag registers */
106	#define TRCCLAIMSET 0xFA0
107	#define TRCCLAIMCLR 0xFA4
108	/* Management registers (0xFA8-0xFFC) */
109	#define TRCDEVAFF0 0xFA8
110	#define TRCDEVAFF1 0xFAC
111	#define TRCLAR 0xFB0
112	#define TRCLSR 0xFB4
113	#define TRCAUTHSTATUS 0xFB8
114	#define TRCDEVARCH 0xFBC
115	#define TRCDEVID 0xFC8
116	#define TRCDEVTYPE 0xFCC
117	#define TRCPIDR4 0xFD0
118	#define TRCPIDR5 0xFD4
119	#define TRCPIDR6 0xFD8
120	#define TRCPIDR7 0xFDC
121	#define TRCPIDR0 0xFE0
122	#define TRCPIDR1 0xFE4
123	#define TRCPIDR2 0xFE8
124	#define TRCPIDR3 0xFEC
125	#define TRCCIDR0 0xFF0
126	#define TRCCIDR1 0xFF4
127	#define TRCCIDR2 0xFF8
128	#define TRCCIDR3 0xFFC
129
130	/* ETMv4 resources */
131	#define ETM_MAX_NR_PE 8
132	#define ETMv4_MAX_CNTR 4
133	#define ETM_MAX_SEQ_STATES 4
134	#define ETM_MAX_EXT_INP_SEL 4
135	#define ETM_MAX_EXT_INP 256
136	#define ETM_MAX_EXT_OUT 4
137	#define ETM_MAX_SINGLE_ADDR_CMP 16
138	#define ETM_MAX_ADDR_RANGE_CMP (ETM_MAX_SINGLE_ADDR_CMP / 2)
139	#define ETM_MAX_DATA_VAL_CMP 8
140	#define ETMv4_MAX_CTXID_CMP 8
141	#define ETM_MAX_VMID_CMP 8
142	#define ETM_MAX_PE_CMP 8
143	#define ETM_MAX_RES_SEL 16
144	#define ETM_MAX_SS_CMP 8
145
146	#define ETM_ARCH_V4 0x40
147	#define ETMv4_SYNC_MASK 0x1F
148	#define ETM_CYC_THRESHOLD_MASK 0xFFF
149	#define ETMv4_EVENT_MASK 0xFF
150	#define ETM_CNTR_MAX_VAL 0xFFFF
151	#define ETM_TRACEID_MASK 0x3f
152
153	/* ETMv4 programming modes */
154	#define ETM_MODE_EXCLUDE BIT(0)
155	#define ETM_MODE_LOAD BIT(1)
156	#define ETM_MODE_STORE BIT(2)
157	#define ETM_MODE_LOAD_STORE BIT(3)
158	#define ETM_MODE_BB BIT(4)
159	#define ETMv4_MODE_CYCACC BIT(5)
160	#define ETMv4_MODE_CTXID BIT(6)
161	#define ETM_MODE_VMID BIT(7)
162	#define ETM_MODE_COND(val) BMVAL(val, 8, 10)
163	#define ETMv4_MODE_TIMESTAMP BIT(11)
164	#define ETM_MODE_RETURNSTACK BIT(12)
165	#define ETM_MODE_QELEM(val) BMVAL(val, 13, 14)
166	#define ETM_MODE_DATA_TRACE_ADDR BIT(15)
167	#define ETM_MODE_DATA_TRACE_VAL BIT(16)
168	#define ETM_MODE_ISTALL BIT(17)
169	#define ETM_MODE_DSTALL BIT(18)
170	#define ETM_MODE_ATB_TRIGGER BIT(19)
171	#define ETM_MODE_LPOVERRIDE BIT(20)
172	#define ETM_MODE_ISTALL_EN BIT(21)
173	#define ETM_MODE_DSTALL_EN BIT(22)
174	#define ETM_MODE_INSTPRIO BIT(23)
175	#define ETM_MODE_NOOVERFLOW BIT(24)
176	#define ETM_MODE_TRACE_RESET BIT(25)
177	#define ETM_MODE_TRACE_ERR BIT(26)
178	#define ETM_MODE_VIEWINST_STARTSTOP BIT(27)
4f6fce54 MP	179	#define ETMv4_MODE_ALL (GENMASK(27, 0) \| \
	180	ETM_MODE_EXCL_KERN \| \
	181	ETM_MODE_EXCL_USER)
2e1cdfe1 PP	182
2e1cdfe1 PP	183	#define TRCSTATR_IDLE_BIT 0
fc208abe MP	184	#define ETM_DEFAULT_ADDR_COMP 0
fc208abe MP	185
46a3d5cd SH	186	/* PowerDown Control Register bits */
	187	#define TRCPDCR_PU BIT(3)
	188
fc208abe MP	189	/* secure state access levels */
	190	#define ETM_EXLEVEL_S_APP BIT(8)
	191	#define ETM_EXLEVEL_S_OS BIT(9)
	192	#define ETM_EXLEVEL_S_NA BIT(10)
	193	#define ETM_EXLEVEL_S_HYP BIT(11)
	194	/* non-secure state access levels */
	195	#define ETM_EXLEVEL_NS_APP BIT(12)
	196	#define ETM_EXLEVEL_NS_OS BIT(13)
	197	#define ETM_EXLEVEL_NS_HYP BIT(14)
	198	#define ETM_EXLEVEL_NS_NA BIT(15)
2e1cdfe1 PP	199
2e1cdfe1 PP	200	/**
54ff892b	201	* struct etmv4_config - configuration information related to an ETMv4
2e1cdfe1	202	* @mode: Controls various modes supported by this ETM.
2e1cdfe1 PP	203	* @pe_sel: Controls which PE to trace.
	204	* @cfg: Controls the tracing options.
	205	* @eventctrl0: Controls the tracing of arbitrary events.
	206	* @eventctrl1: Controls the behavior of the events that @event_ctrl0 selects.
	207	* @stallctl: If functionality that prevents trace unit buffer overflows
	208	* is available.
2e1cdfe1 PP	209	* @ts_ctrl: Controls the insertion of global timestamps in the
2e1cdfe1 PP	210	* trace streams.
2e1cdfe1	211	* @syncfreq: Controls how often trace synchronization requests occur.
2e1cdfe1 PP	212	* the TRCCCCTLR register.
2e1cdfe1 PP	213	* @ccctlr: Sets the threshold value for cycle counting.
2e1cdfe1 PP	214	* @vinst_ctrl: Controls instruction trace filtering.
	215	* @viiectlr: Set or read, the address range comparators.
	216	* @vissctlr: Set, or read, the single address comparators that control the
	217	* ViewInst start-stop logic.
	218	* @vipcssctlr: Set, or read, which PE comparator inputs can control the
	219	* ViewInst start-stop logic.
	220	* @seq_idx: Sequencor index selector.
	221	* @seq_ctrl: Control for the sequencer state transition control register.
	222	* @seq_rst: Moves the sequencer to state 0 when a programmed event occurs.
	223	* @seq_state: Set, or read the sequencer state.
	224	* @cntr_idx: Counter index seletor.
	225	* @cntrldvr: Sets or returns the reload count value for a counter.
	226	* @cntr_ctrl: Controls the operation of a counter.
	227	* @cntr_val: Sets or returns the value for a counter.
	228	* @res_idx: Resource index selector.
	229	* @res_ctrl: Controls the selection of the resources in the trace unit.
	230	* @ss_ctrl: Controls the corresponding single-shot comparator resource.
	231	* @ss_status: The status of the corresponding single-shot comparator.
	232	* @ss_pe_cmp: Selects the PE comparator inputs for Single-shot control.
	233	* @addr_idx: Address comparator index selector.
	234	* @addr_val: Value for address comparator.
	235	* @addr_acc: Address comparator access type.
	236	* @addr_type: Current status of the comparator register.
	237	* @ctxid_idx: Context ID index selector.
cd196ac3	238	* @ctxid_pid: Value of the context ID comparator.
f67b467a CZ	239	* @ctxid_vpid: Virtual PID seen by users if PID namespace is enabled, otherwise
f67b467a CZ	240	* the same value of ctxid_pid.
2e1cdfe1 PP	241	* @ctxid_mask0:Context ID comparator mask for comparator 0-3.
	242	* @ctxid_mask1:Context ID comparator mask for comparator 4-7.
	243	* @vmid_idx: VM ID index selector.
2e1cdfe1 PP	244	* @vmid_val: Value of the VM ID comparator.
	245	* @vmid_mask0: VM ID comparator mask for comparator 0-3.
	246	* @vmid_mask1: VM ID comparator mask for comparator 4-7.
2e1cdfe1 PP	247	* @ext_inp: External input selection.
2e1cdfe1 PP	248	*/
54ff892b	249	struct etmv4_config {
2e1cdfe1	250	u32 mode;
2e1cdfe1 PP	251	u32 pe_sel;
	252	u32 cfg;
	253	u32 eventctrl0;
	254	u32 eventctrl1;
2e1cdfe1	255	u32 stall_ctrl;
2e1cdfe1	256	u32 ts_ctrl;
2e1cdfe1	257	u32 syncfreq;
2e1cdfe1	258	u32 ccctlr;
2e1cdfe1	259	u32 bb_ctrl;
2e1cdfe1 PP	260	u32 vinst_ctrl;
	261	u32 viiectlr;
	262	u32 vissctlr;
	263	u32 vipcssctlr;
	264	u8 seq_idx;
	265	u32 seq_ctrl[ETM_MAX_SEQ_STATES];
	266	u32 seq_rst;
	267	u32 seq_state;
	268	u8 cntr_idx;
	269	u32 cntrldvr[ETMv4_MAX_CNTR];
	270	u32 cntr_ctrl[ETMv4_MAX_CNTR];
	271	u32 cntr_val[ETMv4_MAX_CNTR];
	272	u8 res_idx;
	273	u32 res_ctrl[ETM_MAX_RES_SEL];
	274	u32 ss_ctrl[ETM_MAX_SS_CMP];
	275	u32 ss_status[ETM_MAX_SS_CMP];
	276	u32 ss_pe_cmp[ETM_MAX_SS_CMP];
	277	u8 addr_idx;
	278	u64 addr_val[ETM_MAX_SINGLE_ADDR_CMP];
	279	u64 addr_acc[ETM_MAX_SINGLE_ADDR_CMP];
	280	u8 addr_type[ETM_MAX_SINGLE_ADDR_CMP];
	281	u8 ctxid_idx;
cd196ac3	282	u64 ctxid_pid[ETMv4_MAX_CTXID_CMP];
f67b467a	283	u64 ctxid_vpid[ETMv4_MAX_CTXID_CMP];
2e1cdfe1 PP	284	u32 ctxid_mask0;
	285	u32 ctxid_mask1;
	286	u8 vmid_idx;
2e1cdfe1 PP	287	u64 vmid_val[ETM_MAX_VMID_CMP];
	288	u32 vmid_mask0;
	289	u32 vmid_mask1;
54ff892b MP	290	u32 ext_inp;
	291	};
	292
	293	/**
	294	* struct etm4_drvdata - specifics associated to an ETM component
	295	* @base: Memory mapped base address for this component.
	296	* @dev: The device entity associated to this component.
	297	* @csdev: Component vitals needed by the framework.
	298	* @spinlock: Only one at a time pls.
c38a9ec2	299	* @mode: This tracer's mode, i.e sysFS, Perf or disabled.
54ff892b MP	300	* @cpu: The cpu this component is affined to.
	301	* @arch: ETM version number.
	302	* @nr_pe: The number of processing entity available for tracing.
	303	* @nr_pe_cmp: The number of processing entity comparator inputs that are
	304	* available for tracing.
	305	* @nr_addr_cmp:Number of pairs of address comparators available
	306	* as found in ETMIDR4 0-3.
	307	* @nr_cntr: Number of counters as found in ETMIDR5 bit 28-30.
	308	* @nr_ext_inp: Number of external input.
	309	* @numcidc: Number of contextID comparators.
	310	* @numvmidc: Number of VMID comparators.
	311	* @nrseqstate: The number of sequencer states that are implemented.
	312	* @nr_event: Indicates how many events the trace unit support.
	313	* @nr_resource:The number of resource selection pairs available for tracing.
	314	* @nr_ss_cmp: Number of single-shot comparator controls that are available.
	315	* @trcid: value of the current ID for this component.
	316	* @trcid_size: Indicates the trace ID width.
	317	* @ts_size: Global timestamp size field.
	318	* @ctxid_size: Size of the context ID field to consider.
	319	* @vmid_size: Size of the VM ID comparator to consider.
	320	* @ccsize: Indicates the size of the cycle counter in bits.
	321	* @ccitmin: minimum value that can be programmed in
	322	* @s_ex_level: In secure state, indicates whether instruction tracing is
	323	* supported for the corresponding Exception level.
	324	* @ns_ex_level:In non-secure state, indicates whether instruction tracing is
	325	* supported for the corresponding Exception level.
54ff892b MP	326	* @sticky_enable: true if ETM base configuration has been done.
	327	* @boot_enable:True if we should start tracing at boot time.
	328	* @os_unlock: True if access to management registers is allowed.
	329	* @instrp0: Tracing of load and store instructions
	330	* as P0 elements is supported.
	331	* @trcbb: Indicates if the trace unit supports branch broadcast tracing.
	332	* @trccond: If the trace unit supports conditional
	333	* instruction tracing.
	334	* @retstack: Indicates if the implementation supports a return stack.
	335	* @trccci: Indicates if the trace unit supports cycle counting
	336	* for instruction.
	337	* @q_support: Q element support characteristics.
	338	* @trc_error: Whether a trace unit can trace a system
	339	* error exception.
	340	* @syncpr: Indicates if an implementation has a fixed
	341	* synchronization period.
	342	* @stall_ctrl: Enables trace unit functionality that prevents trace
	343	* unit buffer overflows.
	344	* @sysstall: Does the system support stall control of the PE?
	345	* @nooverflow: Indicate if overflow prevention is supported.
	346	* @atbtrig: If the implementation can support ATB triggers
	347	* @lpoverride: If the implementation can support low-power state over.
	348	* @config: structure holding configuration parameters.
	349	*/
	350	struct etmv4_drvdata {
	351	void __iomem *base;
	352	struct device *dev;
	353	struct coresight_device *csdev;
	354	spinlock_t spinlock;
c38a9ec2	355	local_t mode;
54ff892b MP	356	int cpu;
	357	u8 arch;
	358	u8 nr_pe;
	359	u8 nr_pe_cmp;
	360	u8 nr_addr_cmp;
	361	u8 nr_cntr;
	362	u8 nr_ext_inp;
	363	u8 numcidc;
	364	u8 numvmidc;
	365	u8 nrseqstate;
	366	u8 nr_event;
	367	u8 nr_resource;
	368	u8 nr_ss_cmp;
	369	u8 trcid;
	370	u8 trcid_size;
	371	u8 ts_size;
	372	u8 ctxid_size;
	373	u8 vmid_size;
	374	u8 ccsize;
	375	u8 ccitmin;
2e1cdfe1 PP	376	u8 s_ex_level;
2e1cdfe1 PP	377	u8 ns_ex_level;
6327a454	378	u8 q_support;
54ff892b MP	379	bool sticky_enable;
	380	bool boot_enable;
	381	bool os_unlock;
	382	bool instrp0;
	383	bool trcbb;
	384	bool trccond;
	385	bool retstack;
	386	bool trccci;
54ff892b MP	387	bool trc_error;
	388	bool syncpr;
	389	bool stallctl;
	390	bool sysstall;
	391	bool nooverflow;
	392	bool atbtrig;
	393	bool lpoverride;
	394	struct etmv4_config config;
2e1cdfe1 PP	395	};
	396
	397	/* Address comparator access types */
	398	enum etm_addr_acctype {
	399	ETM_INSTR_ADDR,
	400	ETM_DATA_LOAD_ADDR,
	401	ETM_DATA_STORE_ADDR,
	402	ETM_DATA_LOAD_STORE_ADDR,
	403	};
	404
	405	/* Address comparator context types */
	406	enum etm_addr_ctxtype {
	407	ETM_CTX_NONE,
	408	ETM_CTX_CTXID,
	409	ETM_CTX_VMID,
	410	ETM_CTX_CTXID_VMID,
	411	};
	412
	413	enum etm_addr_type {
	414	ETM_ADDR_TYPE_NONE,
	415	ETM_ADDR_TYPE_SINGLE,
	416	ETM_ADDR_TYPE_RANGE,
	417	ETM_ADDR_TYPE_START,
	418	ETM_ADDR_TYPE_STOP,
	419	};
a77de263 MP	420
a77de263 MP	421	extern const struct attribute_group *coresight_etmv4_groups[];
4f6fce54	422	void etm4_config_trace_mode(struct etmv4_config *config);
2e1cdfe1	423	#endif