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a06ae860 PP |
1 | /* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved. |
2 | * | |
3 | * This program is free software; you can redistribute it and/or modify | |
4 | * it under the terms of the GNU General Public License version 2 and | |
5 | * only version 2 as published by the Free Software Foundation. | |
6 | * | |
7 | * This program is distributed in the hope that it will be useful, | |
8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
10 | * GNU General Public License for more details. | |
11 | */ | |
12 | ||
13 | #ifndef _CORESIGHT_PRIV_H | |
14 | #define _CORESIGHT_PRIV_H | |
15 | ||
16 | #include <linux/bitops.h> | |
17 | #include <linux/io.h> | |
18 | #include <linux/coresight.h> | |
cd9e3474 | 19 | #include <linux/pm_runtime.h> |
a06ae860 PP |
20 | |
21 | /* | |
22 | * Coresight management registers (0xf00-0xfcc) | |
23 | * 0xfa0 - 0xfa4: Management registers in PFTv1.0 | |
24 | * Trace registers in PFTv1.1 | |
25 | */ | |
26 | #define CORESIGHT_ITCTRL 0xf00 | |
27 | #define CORESIGHT_CLAIMSET 0xfa0 | |
28 | #define CORESIGHT_CLAIMCLR 0xfa4 | |
29 | #define CORESIGHT_LAR 0xfb0 | |
30 | #define CORESIGHT_LSR 0xfb4 | |
31 | #define CORESIGHT_AUTHSTATUS 0xfb8 | |
32 | #define CORESIGHT_DEVID 0xfc8 | |
33 | #define CORESIGHT_DEVTYPE 0xfcc | |
34 | ||
35 | #define TIMEOUT_US 100 | |
36 | #define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb) | |
37 | ||
2127154d MP |
38 | #define ETM_MODE_EXCL_KERN BIT(30) |
39 | #define ETM_MODE_EXCL_USER BIT(31) | |
40 | ||
3224dcc5 SH |
41 | typedef u32 (*coresight_read_fn)(const struct device *, u32 offset); |
42 | #define coresight_simple_func(type, func, name, offset) \ | |
154f3520 MP |
43 | static ssize_t name##_show(struct device *_dev, \ |
44 | struct device_attribute *attr, char *buf) \ | |
45 | { \ | |
46 | type *drvdata = dev_get_drvdata(_dev->parent); \ | |
3224dcc5 | 47 | coresight_read_fn fn = func; \ |
cd9e3474 MP |
48 | u32 val; \ |
49 | pm_runtime_get_sync(_dev->parent); \ | |
3224dcc5 SH |
50 | if (fn) \ |
51 | val = fn(_dev->parent, offset); \ | |
52 | else \ | |
53 | val = readl_relaxed(drvdata->base + offset); \ | |
cd9e3474 MP |
54 | pm_runtime_put_sync(_dev->parent); \ |
55 | return scnprintf(buf, PAGE_SIZE, "0x%x\n", val); \ | |
154f3520 MP |
56 | } \ |
57 | static DEVICE_ATTR_RO(name) | |
58 | ||
22fd532e MP |
59 | enum cs_mode { |
60 | CS_MODE_DISABLED, | |
61 | CS_MODE_SYSFS, | |
62 | CS_MODE_PERF, | |
63 | }; | |
64 | ||
a02e81f7 MP |
65 | /** |
66 | * struct cs_buffer - keep track of a recording session' specifics | |
67 | * @cur: index of the current buffer | |
68 | * @nr_pages: max number of pages granted to us | |
69 | * @offset: offset within the current buffer | |
70 | * @data_size: how much we collected in this run | |
71 | * @lost: other than zero if we had a HW buffer wrap around | |
72 | * @snapshot: is this run in snapshot mode | |
73 | * @data_pages: a handle the ring buffer | |
74 | */ | |
75 | struct cs_buffers { | |
76 | unsigned int cur; | |
77 | unsigned int nr_pages; | |
78 | unsigned long offset; | |
79 | local_t data_size; | |
80 | local_t lost; | |
81 | bool snapshot; | |
82 | void **data_pages; | |
83 | }; | |
84 | ||
a06ae860 PP |
85 | static inline void CS_LOCK(void __iomem *addr) |
86 | { | |
87 | do { | |
88 | /* Wait for things to settle */ | |
89 | mb(); | |
90 | writel_relaxed(0x0, addr + CORESIGHT_LAR); | |
91 | } while (0); | |
92 | } | |
93 | ||
94 | static inline void CS_UNLOCK(void __iomem *addr) | |
95 | { | |
96 | do { | |
97 | writel_relaxed(CORESIGHT_UNLOCK, addr + CORESIGHT_LAR); | |
84b763d5 | 98 | /* Make sure everyone has seen this */ |
a06ae860 PP |
99 | mb(); |
100 | } while (0); | |
101 | } | |
102 | ||
b3e94405 | 103 | void coresight_disable_path(struct list_head *path); |
e827d455 | 104 | int coresight_enable_path(struct list_head *path, u32 mode); |
b6404e21 | 105 | struct coresight_device *coresight_get_sink(struct list_head *path); |
b3e94405 MP |
106 | struct list_head *coresight_build_path(struct coresight_device *csdev); |
107 | void coresight_release_path(struct list_head *path); | |
108 | ||
a06ae860 PP |
109 | #ifdef CONFIG_CORESIGHT_SOURCE_ETM3X |
110 | extern int etm_readl_cp14(u32 off, unsigned int *val); | |
111 | extern int etm_writel_cp14(u32 off, u32 val); | |
112 | #else | |
113 | static inline int etm_readl_cp14(u32 off, unsigned int *val) { return 0; } | |
5fb31cd8 | 114 | static inline int etm_writel_cp14(u32 off, u32 val) { return 0; } |
a06ae860 PP |
115 | #endif |
116 | ||
117 | #endif |