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1738cd3e NB |
1 | /* |
2 | * Copyright 2015 Amazon.com, Inc. or its affiliates. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef ENA_COM | |
34 | #define ENA_COM | |
35 | ||
e9e1da25 | 36 | #include <linux/compiler.h> |
1738cd3e NB |
37 | #include <linux/delay.h> |
38 | #include <linux/dma-mapping.h> | |
39 | #include <linux/gfp.h> | |
40 | #include <linux/sched.h> | |
41 | #include <linux/sizes.h> | |
42 | #include <linux/spinlock.h> | |
43 | #include <linux/types.h> | |
44 | #include <linux/wait.h> | |
45 | ||
46 | #include "ena_common_defs.h" | |
47 | #include "ena_admin_defs.h" | |
48 | #include "ena_eth_io_defs.h" | |
49 | #include "ena_regs_defs.h" | |
50 | ||
51 | #undef pr_fmt | |
52 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
53 | ||
54 | #define ENA_MAX_NUM_IO_QUEUES 128U | |
55 | /* We need to queues for each IO (on for Tx and one for Rx) */ | |
56 | #define ENA_TOTAL_NUM_QUEUES (2 * (ENA_MAX_NUM_IO_QUEUES)) | |
57 | ||
58 | #define ENA_MAX_HANDLERS 256 | |
59 | ||
60 | #define ENA_MAX_PHYS_ADDR_SIZE_BITS 48 | |
61 | ||
62 | /* Unit in usec */ | |
63 | #define ENA_REG_READ_TIMEOUT 200000 | |
64 | ||
65 | #define ADMIN_SQ_SIZE(depth) ((depth) * sizeof(struct ena_admin_aq_entry)) | |
66 | #define ADMIN_CQ_SIZE(depth) ((depth) * sizeof(struct ena_admin_acq_entry)) | |
67 | #define ADMIN_AENQ_SIZE(depth) ((depth) * sizeof(struct ena_admin_aenq_entry)) | |
68 | ||
69 | /*****************************************************************************/ | |
70 | /*****************************************************************************/ | |
71 | /* ENA adaptive interrupt moderation settings */ | |
72 | ||
73 | #define ENA_INTR_LOWEST_USECS (0) | |
74 | #define ENA_INTR_LOWEST_PKTS (3) | |
75 | #define ENA_INTR_LOWEST_BYTES (2 * 1524) | |
76 | ||
77 | #define ENA_INTR_LOW_USECS (32) | |
78 | #define ENA_INTR_LOW_PKTS (12) | |
79 | #define ENA_INTR_LOW_BYTES (16 * 1024) | |
80 | ||
81 | #define ENA_INTR_MID_USECS (80) | |
82 | #define ENA_INTR_MID_PKTS (48) | |
83 | #define ENA_INTR_MID_BYTES (64 * 1024) | |
84 | ||
85 | #define ENA_INTR_HIGH_USECS (128) | |
86 | #define ENA_INTR_HIGH_PKTS (96) | |
87 | #define ENA_INTR_HIGH_BYTES (128 * 1024) | |
88 | ||
89 | #define ENA_INTR_HIGHEST_USECS (192) | |
90 | #define ENA_INTR_HIGHEST_PKTS (128) | |
91 | #define ENA_INTR_HIGHEST_BYTES (192 * 1024) | |
92 | ||
93 | #define ENA_INTR_INITIAL_TX_INTERVAL_USECS 196 | |
94 | #define ENA_INTR_INITIAL_RX_INTERVAL_USECS 4 | |
95 | #define ENA_INTR_DELAY_OLD_VALUE_WEIGHT 6 | |
96 | #define ENA_INTR_DELAY_NEW_VALUE_WEIGHT 4 | |
97 | #define ENA_INTR_MODER_LEVEL_STRIDE 2 | |
98 | #define ENA_INTR_BYTE_COUNT_NOT_SUPPORTED 0xFFFFFF | |
99 | ||
bca37ffd NB |
100 | #define ENA_HW_HINTS_NO_TIMEOUT 0xFFFF |
101 | ||
1738cd3e NB |
102 | enum ena_intr_moder_level { |
103 | ENA_INTR_MODER_LOWEST = 0, | |
104 | ENA_INTR_MODER_LOW, | |
105 | ENA_INTR_MODER_MID, | |
106 | ENA_INTR_MODER_HIGH, | |
107 | ENA_INTR_MODER_HIGHEST, | |
108 | ENA_INTR_MAX_NUM_OF_LEVELS, | |
109 | }; | |
110 | ||
111 | struct ena_intr_moder_entry { | |
112 | unsigned int intr_moder_interval; | |
113 | unsigned int pkts_per_interval; | |
114 | unsigned int bytes_per_interval; | |
115 | }; | |
116 | ||
117 | enum queue_direction { | |
118 | ENA_COM_IO_QUEUE_DIRECTION_TX, | |
119 | ENA_COM_IO_QUEUE_DIRECTION_RX | |
120 | }; | |
121 | ||
122 | struct ena_com_buf { | |
123 | dma_addr_t paddr; /**< Buffer physical address */ | |
124 | u16 len; /**< Buffer length in bytes */ | |
125 | }; | |
126 | ||
127 | struct ena_com_rx_buf_info { | |
128 | u16 len; | |
129 | u16 req_id; | |
130 | }; | |
131 | ||
132 | struct ena_com_io_desc_addr { | |
133 | u8 __iomem *pbuf_dev_addr; /* LLQ address */ | |
134 | u8 *virt_addr; | |
135 | dma_addr_t phys_addr; | |
136 | }; | |
137 | ||
138 | struct ena_com_tx_meta { | |
139 | u16 mss; | |
140 | u16 l3_hdr_len; | |
141 | u16 l3_hdr_offset; | |
142 | u16 l4_hdr_len; /* In words */ | |
143 | }; | |
144 | ||
145 | struct ena_com_io_cq { | |
146 | struct ena_com_io_desc_addr cdesc_addr; | |
147 | ||
148 | /* Interrupt unmask register */ | |
149 | u32 __iomem *unmask_reg; | |
150 | ||
151 | /* The completion queue head doorbell register */ | |
152 | u32 __iomem *cq_head_db_reg; | |
153 | ||
154 | /* numa configuration register (for TPH) */ | |
155 | u32 __iomem *numa_node_cfg_reg; | |
156 | ||
157 | /* The value to write to the above register to unmask | |
158 | * the interrupt of this queue | |
159 | */ | |
160 | u32 msix_vector; | |
161 | ||
162 | enum queue_direction direction; | |
163 | ||
164 | /* holds the number of cdesc of the current packet */ | |
165 | u16 cur_rx_pkt_cdesc_count; | |
166 | /* save the firt cdesc idx of the current packet */ | |
167 | u16 cur_rx_pkt_cdesc_start_idx; | |
168 | ||
169 | u16 q_depth; | |
170 | /* Caller qid */ | |
171 | u16 qid; | |
172 | ||
173 | /* Device queue index */ | |
174 | u16 idx; | |
175 | u16 head; | |
176 | u16 last_head_update; | |
177 | u8 phase; | |
178 | u8 cdesc_entry_size_in_bytes; | |
179 | ||
180 | } ____cacheline_aligned; | |
181 | ||
182 | struct ena_com_io_sq { | |
183 | struct ena_com_io_desc_addr desc_addr; | |
184 | ||
185 | u32 __iomem *db_addr; | |
186 | u8 __iomem *header_addr; | |
187 | ||
188 | enum queue_direction direction; | |
189 | enum ena_admin_placement_policy_type mem_queue_type; | |
190 | ||
191 | u32 msix_vector; | |
192 | struct ena_com_tx_meta cached_tx_meta; | |
193 | ||
194 | u16 q_depth; | |
195 | u16 qid; | |
196 | ||
197 | u16 idx; | |
198 | u16 tail; | |
199 | u16 next_to_comp; | |
200 | u32 tx_max_header_size; | |
201 | u8 phase; | |
202 | u8 desc_entry_size; | |
203 | u8 dma_addr_bits; | |
204 | } ____cacheline_aligned; | |
205 | ||
206 | struct ena_com_admin_cq { | |
207 | struct ena_admin_acq_entry *entries; | |
208 | dma_addr_t dma_addr; | |
209 | ||
210 | u16 head; | |
211 | u8 phase; | |
212 | }; | |
213 | ||
214 | struct ena_com_admin_sq { | |
215 | struct ena_admin_aq_entry *entries; | |
216 | dma_addr_t dma_addr; | |
217 | ||
218 | u32 __iomem *db_addr; | |
219 | ||
220 | u16 head; | |
221 | u16 tail; | |
222 | u8 phase; | |
223 | ||
224 | }; | |
225 | ||
226 | struct ena_com_stats_admin { | |
227 | u32 aborted_cmd; | |
228 | u32 submitted_cmd; | |
229 | u32 completed_cmd; | |
230 | u32 out_of_space; | |
231 | u32 no_completion; | |
232 | }; | |
233 | ||
234 | struct ena_com_admin_queue { | |
235 | void *q_dmadev; | |
236 | spinlock_t q_lock; /* spinlock for the admin queue */ | |
bca37ffd | 237 | |
1738cd3e | 238 | struct ena_comp_ctx *comp_ctx; |
bca37ffd | 239 | u32 completion_timeout; |
1738cd3e NB |
240 | u16 q_depth; |
241 | struct ena_com_admin_cq cq; | |
242 | struct ena_com_admin_sq sq; | |
243 | ||
244 | /* Indicate if the admin queue should poll for completion */ | |
245 | bool polling; | |
246 | ||
247 | u16 curr_cmd_id; | |
248 | ||
249 | /* Indicate that the ena was initialized and can | |
250 | * process new admin commands | |
251 | */ | |
252 | bool running_state; | |
253 | ||
254 | /* Count the number of outstanding admin commands */ | |
255 | atomic_t outstanding_cmds; | |
256 | ||
257 | struct ena_com_stats_admin stats; | |
258 | }; | |
259 | ||
260 | struct ena_aenq_handlers; | |
261 | ||
262 | struct ena_com_aenq { | |
263 | u16 head; | |
264 | u8 phase; | |
265 | struct ena_admin_aenq_entry *entries; | |
266 | dma_addr_t dma_addr; | |
267 | u16 q_depth; | |
268 | struct ena_aenq_handlers *aenq_handlers; | |
269 | }; | |
270 | ||
271 | struct ena_com_mmio_read { | |
272 | struct ena_admin_ena_mmio_req_read_less_resp *read_resp; | |
273 | dma_addr_t read_resp_dma_addr; | |
bca37ffd | 274 | u32 reg_read_to; /* in us */ |
1738cd3e NB |
275 | u16 seq_num; |
276 | bool readless_supported; | |
277 | /* spin lock to ensure a single outstanding read */ | |
278 | spinlock_t lock; | |
279 | }; | |
280 | ||
281 | struct ena_rss { | |
282 | /* Indirect table */ | |
283 | u16 *host_rss_ind_tbl; | |
284 | struct ena_admin_rss_ind_table_entry *rss_ind_tbl; | |
285 | dma_addr_t rss_ind_tbl_dma_addr; | |
286 | u16 tbl_log_size; | |
287 | ||
288 | /* Hash key */ | |
289 | enum ena_admin_hash_functions hash_func; | |
290 | struct ena_admin_feature_rss_flow_hash_control *hash_key; | |
291 | dma_addr_t hash_key_dma_addr; | |
292 | u32 hash_init_val; | |
293 | ||
294 | /* Flow Control */ | |
295 | struct ena_admin_feature_rss_hash_control *hash_ctrl; | |
296 | dma_addr_t hash_ctrl_dma_addr; | |
297 | ||
298 | }; | |
299 | ||
300 | struct ena_host_attribute { | |
301 | /* Debug area */ | |
302 | u8 *debug_area_virt_addr; | |
303 | dma_addr_t debug_area_dma_addr; | |
304 | u32 debug_area_size; | |
305 | ||
306 | /* Host information */ | |
307 | struct ena_admin_host_info *host_info; | |
308 | dma_addr_t host_info_dma_addr; | |
309 | }; | |
310 | ||
311 | /* Each ena_dev is a PCI function. */ | |
312 | struct ena_com_dev { | |
313 | struct ena_com_admin_queue admin_queue; | |
314 | struct ena_com_aenq aenq; | |
315 | struct ena_com_io_cq io_cq_queues[ENA_TOTAL_NUM_QUEUES]; | |
316 | struct ena_com_io_sq io_sq_queues[ENA_TOTAL_NUM_QUEUES]; | |
317 | u8 __iomem *reg_bar; | |
318 | void __iomem *mem_bar; | |
319 | void *dmadev; | |
320 | ||
321 | enum ena_admin_placement_policy_type tx_mem_queue_type; | |
322 | u32 tx_max_header_size; | |
323 | u16 stats_func; /* Selected function for extended statistic dump */ | |
324 | u16 stats_queue; /* Selected queue for extended statistic dump */ | |
325 | ||
326 | struct ena_com_mmio_read mmio_read; | |
327 | ||
328 | struct ena_rss rss; | |
329 | u32 supported_features; | |
330 | u32 dma_addr_bits; | |
331 | ||
332 | struct ena_host_attribute host_attr; | |
333 | bool adaptive_coalescing; | |
334 | u16 intr_delay_resolution; | |
335 | u32 intr_moder_tx_interval; | |
336 | struct ena_intr_moder_entry *intr_moder_tbl; | |
337 | }; | |
338 | ||
339 | struct ena_com_dev_get_features_ctx { | |
340 | struct ena_admin_queue_feature_desc max_queues; | |
341 | struct ena_admin_device_attr_feature_desc dev_attr; | |
342 | struct ena_admin_feature_aenq_desc aenq; | |
343 | struct ena_admin_feature_offload_desc offload; | |
bca37ffd | 344 | struct ena_admin_ena_hw_hints hw_hints; |
1738cd3e NB |
345 | }; |
346 | ||
347 | struct ena_com_create_io_ctx { | |
348 | enum ena_admin_placement_policy_type mem_queue_type; | |
349 | enum queue_direction direction; | |
350 | int numa_node; | |
351 | u32 msix_vector; | |
352 | u16 queue_size; | |
353 | u16 qid; | |
354 | }; | |
355 | ||
356 | typedef void (*ena_aenq_handler)(void *data, | |
357 | struct ena_admin_aenq_entry *aenq_e); | |
358 | ||
359 | /* Holds aenq handlers. Indexed by AENQ event group */ | |
360 | struct ena_aenq_handlers { | |
361 | ena_aenq_handler handlers[ENA_MAX_HANDLERS]; | |
362 | ena_aenq_handler unimplemented_handler; | |
363 | }; | |
364 | ||
365 | /*****************************************************************************/ | |
366 | /*****************************************************************************/ | |
367 | ||
368 | /* ena_com_mmio_reg_read_request_init - Init the mmio reg read mechanism | |
369 | * @ena_dev: ENA communication layer struct | |
370 | * | |
371 | * Initialize the register read mechanism. | |
372 | * | |
373 | * @note: This method must be the first stage in the initialization sequence. | |
374 | * | |
375 | * @return - 0 on success, negative value on failure. | |
376 | */ | |
377 | int ena_com_mmio_reg_read_request_init(struct ena_com_dev *ena_dev); | |
378 | ||
379 | /* ena_com_set_mmio_read_mode - Enable/disable the mmio reg read mechanism | |
380 | * @ena_dev: ENA communication layer struct | |
381 | * @readless_supported: readless mode (enable/disable) | |
382 | */ | |
383 | void ena_com_set_mmio_read_mode(struct ena_com_dev *ena_dev, | |
384 | bool readless_supported); | |
385 | ||
386 | /* ena_com_mmio_reg_read_request_write_dev_addr - Write the mmio reg read return | |
387 | * value physical address. | |
388 | * @ena_dev: ENA communication layer struct | |
389 | */ | |
390 | void ena_com_mmio_reg_read_request_write_dev_addr(struct ena_com_dev *ena_dev); | |
391 | ||
392 | /* ena_com_mmio_reg_read_request_destroy - Destroy the mmio reg read mechanism | |
393 | * @ena_dev: ENA communication layer struct | |
394 | */ | |
395 | void ena_com_mmio_reg_read_request_destroy(struct ena_com_dev *ena_dev); | |
396 | ||
397 | /* ena_com_admin_init - Init the admin and the async queues | |
398 | * @ena_dev: ENA communication layer struct | |
399 | * @aenq_handlers: Those handlers to be called upon event. | |
400 | * @init_spinlock: Indicate if this method should init the admin spinlock or | |
401 | * the spinlock was init before (for example, in a case of FLR). | |
402 | * | |
403 | * Initialize the admin submission and completion queues. | |
404 | * Initialize the asynchronous events notification queues. | |
405 | * | |
406 | * @return - 0 on success, negative value on failure. | |
407 | */ | |
408 | int ena_com_admin_init(struct ena_com_dev *ena_dev, | |
409 | struct ena_aenq_handlers *aenq_handlers, | |
410 | bool init_spinlock); | |
411 | ||
412 | /* ena_com_admin_destroy - Destroy the admin and the async events queues. | |
413 | * @ena_dev: ENA communication layer struct | |
414 | * | |
415 | * @note: Before calling this method, the caller must validate that the device | |
416 | * won't send any additional admin completions/aenq. | |
417 | * To achieve that, a FLR is recommended. | |
418 | */ | |
419 | void ena_com_admin_destroy(struct ena_com_dev *ena_dev); | |
420 | ||
421 | /* ena_com_dev_reset - Perform device FLR to the device. | |
422 | * @ena_dev: ENA communication layer struct | |
423 | * | |
424 | * @return - 0 on success, negative value on failure. | |
425 | */ | |
426 | int ena_com_dev_reset(struct ena_com_dev *ena_dev); | |
427 | ||
428 | /* ena_com_create_io_queue - Create io queue. | |
429 | * @ena_dev: ENA communication layer struct | |
430 | * @ctx - create context structure | |
431 | * | |
432 | * Create the submission and the completion queues. | |
433 | * | |
434 | * @return - 0 on success, negative value on failure. | |
435 | */ | |
436 | int ena_com_create_io_queue(struct ena_com_dev *ena_dev, | |
437 | struct ena_com_create_io_ctx *ctx); | |
438 | ||
439 | /* ena_com_destroy_io_queue - Destroy IO queue with the queue id - qid. | |
440 | * @ena_dev: ENA communication layer struct | |
441 | * @qid - the caller virtual queue id. | |
442 | */ | |
443 | void ena_com_destroy_io_queue(struct ena_com_dev *ena_dev, u16 qid); | |
444 | ||
445 | /* ena_com_get_io_handlers - Return the io queue handlers | |
446 | * @ena_dev: ENA communication layer struct | |
447 | * @qid - the caller virtual queue id. | |
448 | * @io_sq - IO submission queue handler | |
449 | * @io_cq - IO completion queue handler. | |
450 | * | |
451 | * @return - 0 on success, negative value on failure. | |
452 | */ | |
453 | int ena_com_get_io_handlers(struct ena_com_dev *ena_dev, u16 qid, | |
454 | struct ena_com_io_sq **io_sq, | |
455 | struct ena_com_io_cq **io_cq); | |
456 | ||
457 | /* ena_com_admin_aenq_enable - ENAble asynchronous event notifications | |
458 | * @ena_dev: ENA communication layer struct | |
459 | * | |
460 | * After this method, aenq event can be received via AENQ. | |
461 | */ | |
462 | void ena_com_admin_aenq_enable(struct ena_com_dev *ena_dev); | |
463 | ||
464 | /* ena_com_set_admin_running_state - Set the state of the admin queue | |
465 | * @ena_dev: ENA communication layer struct | |
466 | * | |
467 | * Change the state of the admin queue (enable/disable) | |
468 | */ | |
469 | void ena_com_set_admin_running_state(struct ena_com_dev *ena_dev, bool state); | |
470 | ||
471 | /* ena_com_get_admin_running_state - Get the admin queue state | |
472 | * @ena_dev: ENA communication layer struct | |
473 | * | |
474 | * Retrieve the state of the admin queue (enable/disable) | |
475 | * | |
476 | * @return - current polling mode (enable/disable) | |
477 | */ | |
478 | bool ena_com_get_admin_running_state(struct ena_com_dev *ena_dev); | |
479 | ||
480 | /* ena_com_set_admin_polling_mode - Set the admin completion queue polling mode | |
481 | * @ena_dev: ENA communication layer struct | |
482 | * @polling: ENAble/Disable polling mode | |
483 | * | |
484 | * Set the admin completion mode. | |
485 | */ | |
486 | void ena_com_set_admin_polling_mode(struct ena_com_dev *ena_dev, bool polling); | |
487 | ||
488 | /* ena_com_set_admin_polling_mode - Get the admin completion queue polling mode | |
489 | * @ena_dev: ENA communication layer struct | |
490 | * | |
491 | * Get the admin completion mode. | |
492 | * If polling mode is on, ena_com_execute_admin_command will perform a | |
493 | * polling on the admin completion queue for the commands completion, | |
494 | * otherwise it will wait on wait event. | |
495 | * | |
496 | * @return state | |
497 | */ | |
498 | bool ena_com_get_ena_admin_polling_mode(struct ena_com_dev *ena_dev); | |
499 | ||
500 | /* ena_com_admin_q_comp_intr_handler - admin queue interrupt handler | |
501 | * @ena_dev: ENA communication layer struct | |
502 | * | |
503 | * This method go over the admin completion queue and wake up all the pending | |
504 | * threads that wait on the commands wait event. | |
505 | * | |
506 | * @note: Should be called after MSI-X interrupt. | |
507 | */ | |
508 | void ena_com_admin_q_comp_intr_handler(struct ena_com_dev *ena_dev); | |
509 | ||
510 | /* ena_com_aenq_intr_handler - AENQ interrupt handler | |
511 | * @ena_dev: ENA communication layer struct | |
512 | * | |
513 | * This method go over the async event notification queue and call the proper | |
514 | * aenq handler. | |
515 | */ | |
516 | void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data); | |
517 | ||
518 | /* ena_com_abort_admin_commands - Abort all the outstanding admin commands. | |
519 | * @ena_dev: ENA communication layer struct | |
520 | * | |
521 | * This method aborts all the outstanding admin commands. | |
522 | * The caller should then call ena_com_wait_for_abort_completion to make sure | |
523 | * all the commands were completed. | |
524 | */ | |
525 | void ena_com_abort_admin_commands(struct ena_com_dev *ena_dev); | |
526 | ||
527 | /* ena_com_wait_for_abort_completion - Wait for admin commands abort. | |
528 | * @ena_dev: ENA communication layer struct | |
529 | * | |
530 | * This method wait until all the outstanding admin commands will be completed. | |
531 | */ | |
532 | void ena_com_wait_for_abort_completion(struct ena_com_dev *ena_dev); | |
533 | ||
534 | /* ena_com_validate_version - Validate the device parameters | |
535 | * @ena_dev: ENA communication layer struct | |
536 | * | |
537 | * This method validate the device parameters are the same as the saved | |
538 | * parameters in ena_dev. | |
539 | * This method is useful after device reset, to validate the device mac address | |
540 | * and the device offloads are the same as before the reset. | |
541 | * | |
542 | * @return - 0 on success negative value otherwise. | |
543 | */ | |
544 | int ena_com_validate_version(struct ena_com_dev *ena_dev); | |
545 | ||
546 | /* ena_com_get_link_params - Retrieve physical link parameters. | |
547 | * @ena_dev: ENA communication layer struct | |
548 | * @resp: Link parameters | |
549 | * | |
550 | * Retrieve the physical link parameters, | |
551 | * like speed, auto-negotiation and full duplex support. | |
552 | * | |
553 | * @return - 0 on Success negative value otherwise. | |
554 | */ | |
555 | int ena_com_get_link_params(struct ena_com_dev *ena_dev, | |
556 | struct ena_admin_get_feat_resp *resp); | |
557 | ||
558 | /* ena_com_get_dma_width - Retrieve physical dma address width the device | |
559 | * supports. | |
560 | * @ena_dev: ENA communication layer struct | |
561 | * | |
562 | * Retrieve the maximum physical address bits the device can handle. | |
563 | * | |
564 | * @return: > 0 on Success and negative value otherwise. | |
565 | */ | |
566 | int ena_com_get_dma_width(struct ena_com_dev *ena_dev); | |
567 | ||
568 | /* ena_com_set_aenq_config - Set aenq groups configurations | |
569 | * @ena_dev: ENA communication layer struct | |
570 | * @groups flag: bit fields flags of enum ena_admin_aenq_group. | |
571 | * | |
572 | * Configure which aenq event group the driver would like to receive. | |
573 | * | |
574 | * @return: 0 on Success and negative value otherwise. | |
575 | */ | |
576 | int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag); | |
577 | ||
578 | /* ena_com_get_dev_attr_feat - Get device features | |
579 | * @ena_dev: ENA communication layer struct | |
580 | * @get_feat_ctx: returned context that contain the get features. | |
581 | * | |
582 | * @return: 0 on Success and negative value otherwise. | |
583 | */ | |
584 | int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev, | |
585 | struct ena_com_dev_get_features_ctx *get_feat_ctx); | |
586 | ||
587 | /* ena_com_get_dev_basic_stats - Get device basic statistics | |
588 | * @ena_dev: ENA communication layer struct | |
589 | * @stats: stats return value | |
590 | * | |
591 | * @return: 0 on Success and negative value otherwise. | |
592 | */ | |
593 | int ena_com_get_dev_basic_stats(struct ena_com_dev *ena_dev, | |
594 | struct ena_admin_basic_stats *stats); | |
595 | ||
596 | /* ena_com_set_dev_mtu - Configure the device mtu. | |
597 | * @ena_dev: ENA communication layer struct | |
598 | * @mtu: mtu value | |
599 | * | |
600 | * @return: 0 on Success and negative value otherwise. | |
601 | */ | |
602 | int ena_com_set_dev_mtu(struct ena_com_dev *ena_dev, int mtu); | |
603 | ||
604 | /* ena_com_get_offload_settings - Retrieve the device offloads capabilities | |
605 | * @ena_dev: ENA communication layer struct | |
606 | * @offlad: offload return value | |
607 | * | |
608 | * @return: 0 on Success and negative value otherwise. | |
609 | */ | |
610 | int ena_com_get_offload_settings(struct ena_com_dev *ena_dev, | |
611 | struct ena_admin_feature_offload_desc *offload); | |
612 | ||
613 | /* ena_com_rss_init - Init RSS | |
614 | * @ena_dev: ENA communication layer struct | |
615 | * @log_size: indirection log size | |
616 | * | |
617 | * Allocate RSS/RFS resources. | |
618 | * The caller then can configure rss using ena_com_set_hash_function, | |
619 | * ena_com_set_hash_ctrl and ena_com_indirect_table_set. | |
620 | * | |
621 | * @return: 0 on Success and negative value otherwise. | |
622 | */ | |
623 | int ena_com_rss_init(struct ena_com_dev *ena_dev, u16 log_size); | |
624 | ||
625 | /* ena_com_rss_destroy - Destroy rss | |
626 | * @ena_dev: ENA communication layer struct | |
627 | * | |
628 | * Free all the RSS/RFS resources. | |
629 | */ | |
630 | void ena_com_rss_destroy(struct ena_com_dev *ena_dev); | |
631 | ||
632 | /* ena_com_fill_hash_function - Fill RSS hash function | |
633 | * @ena_dev: ENA communication layer struct | |
634 | * @func: The hash function (Toeplitz or crc) | |
635 | * @key: Hash key (for toeplitz hash) | |
636 | * @key_len: key length (max length 10 DW) | |
637 | * @init_val: initial value for the hash function | |
638 | * | |
639 | * Fill the ena_dev resources with the desire hash function, hash key, key_len | |
640 | * and key initial value (if needed by the hash function). | |
641 | * To flush the key into the device the caller should call | |
642 | * ena_com_set_hash_function. | |
643 | * | |
644 | * @return: 0 on Success and negative value otherwise. | |
645 | */ | |
646 | int ena_com_fill_hash_function(struct ena_com_dev *ena_dev, | |
647 | enum ena_admin_hash_functions func, | |
648 | const u8 *key, u16 key_len, u32 init_val); | |
649 | ||
650 | /* ena_com_set_hash_function - Flush the hash function and it dependencies to | |
651 | * the device. | |
652 | * @ena_dev: ENA communication layer struct | |
653 | * | |
654 | * Flush the hash function and it dependencies (key, key length and | |
655 | * initial value) if needed. | |
656 | * | |
657 | * @note: Prior to this method the caller should call ena_com_fill_hash_function | |
658 | * | |
659 | * @return: 0 on Success and negative value otherwise. | |
660 | */ | |
661 | int ena_com_set_hash_function(struct ena_com_dev *ena_dev); | |
662 | ||
663 | /* ena_com_get_hash_function - Retrieve the hash function and the hash key | |
664 | * from the device. | |
665 | * @ena_dev: ENA communication layer struct | |
666 | * @func: hash function | |
667 | * @key: hash key | |
668 | * | |
669 | * Retrieve the hash function and the hash key from the device. | |
670 | * | |
671 | * @note: If the caller called ena_com_fill_hash_function but didn't flash | |
672 | * it to the device, the new configuration will be lost. | |
673 | * | |
674 | * @return: 0 on Success and negative value otherwise. | |
675 | */ | |
676 | int ena_com_get_hash_function(struct ena_com_dev *ena_dev, | |
677 | enum ena_admin_hash_functions *func, | |
678 | u8 *key); | |
679 | ||
680 | /* ena_com_fill_hash_ctrl - Fill RSS hash control | |
681 | * @ena_dev: ENA communication layer struct. | |
682 | * @proto: The protocol to configure. | |
683 | * @hash_fields: bit mask of ena_admin_flow_hash_fields | |
684 | * | |
685 | * Fill the ena_dev resources with the desire hash control (the ethernet | |
686 | * fields that take part of the hash) for a specific protocol. | |
687 | * To flush the hash control to the device, the caller should call | |
688 | * ena_com_set_hash_ctrl. | |
689 | * | |
690 | * @return: 0 on Success and negative value otherwise. | |
691 | */ | |
692 | int ena_com_fill_hash_ctrl(struct ena_com_dev *ena_dev, | |
693 | enum ena_admin_flow_hash_proto proto, | |
694 | u16 hash_fields); | |
695 | ||
696 | /* ena_com_set_hash_ctrl - Flush the hash control resources to the device. | |
697 | * @ena_dev: ENA communication layer struct | |
698 | * | |
699 | * Flush the hash control (the ethernet fields that take part of the hash) | |
700 | * | |
701 | * @note: Prior to this method the caller should call ena_com_fill_hash_ctrl. | |
702 | * | |
703 | * @return: 0 on Success and negative value otherwise. | |
704 | */ | |
705 | int ena_com_set_hash_ctrl(struct ena_com_dev *ena_dev); | |
706 | ||
707 | /* ena_com_get_hash_ctrl - Retrieve the hash control from the device. | |
708 | * @ena_dev: ENA communication layer struct | |
709 | * @proto: The protocol to retrieve. | |
710 | * @fields: bit mask of ena_admin_flow_hash_fields. | |
711 | * | |
712 | * Retrieve the hash control from the device. | |
713 | * | |
714 | * @note, If the caller called ena_com_fill_hash_ctrl but didn't flash | |
715 | * it to the device, the new configuration will be lost. | |
716 | * | |
717 | * @return: 0 on Success and negative value otherwise. | |
718 | */ | |
719 | int ena_com_get_hash_ctrl(struct ena_com_dev *ena_dev, | |
720 | enum ena_admin_flow_hash_proto proto, | |
721 | u16 *fields); | |
722 | ||
723 | /* ena_com_set_default_hash_ctrl - Set the hash control to a default | |
724 | * configuration. | |
725 | * @ena_dev: ENA communication layer struct | |
726 | * | |
727 | * Fill the ena_dev resources with the default hash control configuration. | |
728 | * To flush the hash control to the device, the caller should call | |
729 | * ena_com_set_hash_ctrl. | |
730 | * | |
731 | * @return: 0 on Success and negative value otherwise. | |
732 | */ | |
733 | int ena_com_set_default_hash_ctrl(struct ena_com_dev *ena_dev); | |
734 | ||
735 | /* ena_com_indirect_table_fill_entry - Fill a single entry in the RSS | |
736 | * indirection table | |
737 | * @ena_dev: ENA communication layer struct. | |
738 | * @entry_idx - indirection table entry. | |
739 | * @entry_value - redirection value | |
740 | * | |
741 | * Fill a single entry of the RSS indirection table in the ena_dev resources. | |
742 | * To flush the indirection table to the device, the called should call | |
743 | * ena_com_indirect_table_set. | |
744 | * | |
745 | * @return: 0 on Success and negative value otherwise. | |
746 | */ | |
747 | int ena_com_indirect_table_fill_entry(struct ena_com_dev *ena_dev, | |
748 | u16 entry_idx, u16 entry_value); | |
749 | ||
750 | /* ena_com_indirect_table_set - Flush the indirection table to the device. | |
751 | * @ena_dev: ENA communication layer struct | |
752 | * | |
753 | * Flush the indirection hash control to the device. | |
754 | * Prior to this method the caller should call ena_com_indirect_table_fill_entry | |
755 | * | |
756 | * @return: 0 on Success and negative value otherwise. | |
757 | */ | |
758 | int ena_com_indirect_table_set(struct ena_com_dev *ena_dev); | |
759 | ||
760 | /* ena_com_indirect_table_get - Retrieve the indirection table from the device. | |
761 | * @ena_dev: ENA communication layer struct | |
762 | * @ind_tbl: indirection table | |
763 | * | |
764 | * Retrieve the RSS indirection table from the device. | |
765 | * | |
766 | * @note: If the caller called ena_com_indirect_table_fill_entry but didn't flash | |
767 | * it to the device, the new configuration will be lost. | |
768 | * | |
769 | * @return: 0 on Success and negative value otherwise. | |
770 | */ | |
771 | int ena_com_indirect_table_get(struct ena_com_dev *ena_dev, u32 *ind_tbl); | |
772 | ||
773 | /* ena_com_allocate_host_info - Allocate host info resources. | |
774 | * @ena_dev: ENA communication layer struct | |
775 | * | |
776 | * @return: 0 on Success and negative value otherwise. | |
777 | */ | |
778 | int ena_com_allocate_host_info(struct ena_com_dev *ena_dev); | |
779 | ||
780 | /* ena_com_allocate_debug_area - Allocate debug area. | |
781 | * @ena_dev: ENA communication layer struct | |
782 | * @debug_area_size - debug area size. | |
783 | * | |
784 | * @return: 0 on Success and negative value otherwise. | |
785 | */ | |
786 | int ena_com_allocate_debug_area(struct ena_com_dev *ena_dev, | |
787 | u32 debug_area_size); | |
788 | ||
789 | /* ena_com_delete_debug_area - Free the debug area resources. | |
790 | * @ena_dev: ENA communication layer struct | |
791 | * | |
792 | * Free the allocate debug area. | |
793 | */ | |
794 | void ena_com_delete_debug_area(struct ena_com_dev *ena_dev); | |
795 | ||
796 | /* ena_com_delete_host_info - Free the host info resources. | |
797 | * @ena_dev: ENA communication layer struct | |
798 | * | |
799 | * Free the allocate host info. | |
800 | */ | |
801 | void ena_com_delete_host_info(struct ena_com_dev *ena_dev); | |
802 | ||
803 | /* ena_com_set_host_attributes - Update the device with the host | |
804 | * attributes (debug area and host info) base address. | |
805 | * @ena_dev: ENA communication layer struct | |
806 | * | |
807 | * @return: 0 on Success and negative value otherwise. | |
808 | */ | |
809 | int ena_com_set_host_attributes(struct ena_com_dev *ena_dev); | |
810 | ||
811 | /* ena_com_create_io_cq - Create io completion queue. | |
812 | * @ena_dev: ENA communication layer struct | |
813 | * @io_cq - io completion queue handler | |
814 | ||
815 | * Create IO completion queue. | |
816 | * | |
817 | * @return - 0 on success, negative value on failure. | |
818 | */ | |
819 | int ena_com_create_io_cq(struct ena_com_dev *ena_dev, | |
820 | struct ena_com_io_cq *io_cq); | |
821 | ||
822 | /* ena_com_destroy_io_cq - Destroy io completion queue. | |
823 | * @ena_dev: ENA communication layer struct | |
824 | * @io_cq - io completion queue handler | |
825 | ||
826 | * Destroy IO completion queue. | |
827 | * | |
828 | * @return - 0 on success, negative value on failure. | |
829 | */ | |
830 | int ena_com_destroy_io_cq(struct ena_com_dev *ena_dev, | |
831 | struct ena_com_io_cq *io_cq); | |
832 | ||
833 | /* ena_com_execute_admin_command - Execute admin command | |
834 | * @admin_queue: admin queue. | |
835 | * @cmd: the admin command to execute. | |
836 | * @cmd_size: the command size. | |
837 | * @cmd_completion: command completion return value. | |
838 | * @cmd_comp_size: command completion size. | |
839 | ||
840 | * Submit an admin command and then wait until the device will return a | |
841 | * completion. | |
842 | * The completion will be copyed into cmd_comp. | |
843 | * | |
844 | * @return - 0 on success, negative value on failure. | |
845 | */ | |
846 | int ena_com_execute_admin_command(struct ena_com_admin_queue *admin_queue, | |
847 | struct ena_admin_aq_entry *cmd, | |
848 | size_t cmd_size, | |
849 | struct ena_admin_acq_entry *cmd_comp, | |
850 | size_t cmd_comp_size); | |
851 | ||
852 | /* ena_com_init_interrupt_moderation - Init interrupt moderation | |
853 | * @ena_dev: ENA communication layer struct | |
854 | * | |
855 | * @return - 0 on success, negative value on failure. | |
856 | */ | |
857 | int ena_com_init_interrupt_moderation(struct ena_com_dev *ena_dev); | |
858 | ||
859 | /* ena_com_destroy_interrupt_moderation - Destroy interrupt moderation resources | |
860 | * @ena_dev: ENA communication layer struct | |
861 | */ | |
862 | void ena_com_destroy_interrupt_moderation(struct ena_com_dev *ena_dev); | |
863 | ||
864 | /* ena_com_interrupt_moderation_supported - Return if interrupt moderation | |
865 | * capability is supported by the device. | |
866 | * | |
867 | * @return - supported or not. | |
868 | */ | |
869 | bool ena_com_interrupt_moderation_supported(struct ena_com_dev *ena_dev); | |
870 | ||
871 | /* ena_com_config_default_interrupt_moderation_table - Restore the interrupt | |
872 | * moderation table back to the default parameters. | |
873 | * @ena_dev: ENA communication layer struct | |
874 | */ | |
875 | void ena_com_config_default_interrupt_moderation_table(struct ena_com_dev *ena_dev); | |
876 | ||
877 | /* ena_com_update_nonadaptive_moderation_interval_tx - Update the | |
878 | * non-adaptive interval in Tx direction. | |
879 | * @ena_dev: ENA communication layer struct | |
880 | * @tx_coalesce_usecs: Interval in usec. | |
881 | * | |
882 | * @return - 0 on success, negative value on failure. | |
883 | */ | |
884 | int ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev, | |
885 | u32 tx_coalesce_usecs); | |
886 | ||
887 | /* ena_com_update_nonadaptive_moderation_interval_rx - Update the | |
888 | * non-adaptive interval in Rx direction. | |
889 | * @ena_dev: ENA communication layer struct | |
890 | * @rx_coalesce_usecs: Interval in usec. | |
891 | * | |
892 | * @return - 0 on success, negative value on failure. | |
893 | */ | |
894 | int ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev, | |
895 | u32 rx_coalesce_usecs); | |
896 | ||
897 | /* ena_com_get_nonadaptive_moderation_interval_tx - Retrieve the | |
898 | * non-adaptive interval in Tx direction. | |
899 | * @ena_dev: ENA communication layer struct | |
900 | * | |
901 | * @return - interval in usec | |
902 | */ | |
903 | unsigned int ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev); | |
904 | ||
905 | /* ena_com_get_nonadaptive_moderation_interval_rx - Retrieve the | |
906 | * non-adaptive interval in Rx direction. | |
907 | * @ena_dev: ENA communication layer struct | |
908 | * | |
909 | * @return - interval in usec | |
910 | */ | |
911 | unsigned int ena_com_get_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev); | |
912 | ||
913 | /* ena_com_init_intr_moderation_entry - Update a single entry in the interrupt | |
914 | * moderation table. | |
915 | * @ena_dev: ENA communication layer struct | |
916 | * @level: Interrupt moderation table level | |
917 | * @entry: Entry value | |
918 | * | |
919 | * Update a single entry in the interrupt moderation table. | |
920 | */ | |
921 | void ena_com_init_intr_moderation_entry(struct ena_com_dev *ena_dev, | |
922 | enum ena_intr_moder_level level, | |
923 | struct ena_intr_moder_entry *entry); | |
924 | ||
925 | /* ena_com_get_intr_moderation_entry - Init ena_intr_moder_entry. | |
926 | * @ena_dev: ENA communication layer struct | |
927 | * @level: Interrupt moderation table level | |
928 | * @entry: Entry to fill. | |
929 | * | |
930 | * Initialize the entry according to the adaptive interrupt moderation table. | |
931 | */ | |
932 | void ena_com_get_intr_moderation_entry(struct ena_com_dev *ena_dev, | |
933 | enum ena_intr_moder_level level, | |
934 | struct ena_intr_moder_entry *entry); | |
935 | ||
936 | static inline bool ena_com_get_adaptive_moderation_enabled(struct ena_com_dev *ena_dev) | |
937 | { | |
938 | return ena_dev->adaptive_coalescing; | |
939 | } | |
940 | ||
941 | static inline void ena_com_enable_adaptive_moderation(struct ena_com_dev *ena_dev) | |
942 | { | |
943 | ena_dev->adaptive_coalescing = true; | |
944 | } | |
945 | ||
946 | static inline void ena_com_disable_adaptive_moderation(struct ena_com_dev *ena_dev) | |
947 | { | |
948 | ena_dev->adaptive_coalescing = false; | |
949 | } | |
950 | ||
951 | /* ena_com_calculate_interrupt_delay - Calculate new interrupt delay | |
952 | * @ena_dev: ENA communication layer struct | |
953 | * @pkts: Number of packets since the last update | |
954 | * @bytes: Number of bytes received since the last update. | |
955 | * @smoothed_interval: Returned interval | |
956 | * @moder_tbl_idx: Current table level as input update new level as return | |
957 | * value. | |
958 | */ | |
959 | static inline void ena_com_calculate_interrupt_delay(struct ena_com_dev *ena_dev, | |
960 | unsigned int pkts, | |
961 | unsigned int bytes, | |
962 | unsigned int *smoothed_interval, | |
963 | unsigned int *moder_tbl_idx) | |
964 | { | |
965 | enum ena_intr_moder_level curr_moder_idx, new_moder_idx; | |
966 | struct ena_intr_moder_entry *curr_moder_entry; | |
967 | struct ena_intr_moder_entry *pred_moder_entry; | |
968 | struct ena_intr_moder_entry *new_moder_entry; | |
969 | struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl; | |
970 | unsigned int interval; | |
971 | ||
972 | /* We apply adaptive moderation on Rx path only. | |
973 | * Tx uses static interrupt moderation. | |
974 | */ | |
975 | if (!pkts || !bytes) | |
976 | /* Tx interrupt, or spurious interrupt, | |
977 | * in both cases we just use same delay values | |
978 | */ | |
979 | return; | |
980 | ||
981 | curr_moder_idx = (enum ena_intr_moder_level)(*moder_tbl_idx); | |
982 | if (unlikely(curr_moder_idx >= ENA_INTR_MAX_NUM_OF_LEVELS)) { | |
983 | pr_err("Wrong moderation index %u\n", curr_moder_idx); | |
984 | return; | |
985 | } | |
986 | ||
987 | curr_moder_entry = &intr_moder_tbl[curr_moder_idx]; | |
988 | new_moder_idx = curr_moder_idx; | |
989 | ||
990 | if (curr_moder_idx == ENA_INTR_MODER_LOWEST) { | |
991 | if ((pkts > curr_moder_entry->pkts_per_interval) || | |
992 | (bytes > curr_moder_entry->bytes_per_interval)) | |
993 | new_moder_idx = | |
994 | (enum ena_intr_moder_level)(curr_moder_idx + ENA_INTR_MODER_LEVEL_STRIDE); | |
995 | } else { | |
996 | pred_moder_entry = &intr_moder_tbl[curr_moder_idx - ENA_INTR_MODER_LEVEL_STRIDE]; | |
997 | ||
998 | if ((pkts <= pred_moder_entry->pkts_per_interval) || | |
999 | (bytes <= pred_moder_entry->bytes_per_interval)) | |
1000 | new_moder_idx = | |
1001 | (enum ena_intr_moder_level)(curr_moder_idx - ENA_INTR_MODER_LEVEL_STRIDE); | |
1002 | else if ((pkts > curr_moder_entry->pkts_per_interval) || | |
1003 | (bytes > curr_moder_entry->bytes_per_interval)) { | |
1004 | if (curr_moder_idx != ENA_INTR_MODER_HIGHEST) | |
1005 | new_moder_idx = | |
1006 | (enum ena_intr_moder_level)(curr_moder_idx + ENA_INTR_MODER_LEVEL_STRIDE); | |
1007 | } | |
1008 | } | |
1009 | new_moder_entry = &intr_moder_tbl[new_moder_idx]; | |
1010 | ||
1011 | interval = new_moder_entry->intr_moder_interval; | |
1012 | *smoothed_interval = ( | |
1013 | (interval * ENA_INTR_DELAY_NEW_VALUE_WEIGHT + | |
1014 | ENA_INTR_DELAY_OLD_VALUE_WEIGHT * (*smoothed_interval)) + 5) / | |
1015 | 10; | |
1016 | ||
1017 | *moder_tbl_idx = new_moder_idx; | |
1018 | } | |
1019 | ||
1020 | /* ena_com_update_intr_reg - Prepare interrupt register | |
1021 | * @intr_reg: interrupt register to update. | |
1022 | * @rx_delay_interval: Rx interval in usecs | |
1023 | * @tx_delay_interval: Tx interval in usecs | |
1024 | * @unmask: unask enable/disable | |
1025 | * | |
1026 | * Prepare interrupt update register with the supplied parameters. | |
1027 | */ | |
1028 | static inline void ena_com_update_intr_reg(struct ena_eth_io_intr_reg *intr_reg, | |
1029 | u32 rx_delay_interval, | |
1030 | u32 tx_delay_interval, | |
1031 | bool unmask) | |
1032 | { | |
1033 | intr_reg->intr_control = 0; | |
1034 | intr_reg->intr_control |= rx_delay_interval & | |
1035 | ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK; | |
1036 | ||
1037 | intr_reg->intr_control |= | |
1038 | (tx_delay_interval << ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT) | |
1039 | & ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK; | |
1040 | ||
1041 | if (unmask) | |
1042 | intr_reg->intr_control |= ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK; | |
1043 | } | |
1044 | ||
1045 | #endif /* !(ENA_COM) */ |