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net/ena: use napi_complete_done() return value
[mirror_ubuntu-zesty-kernel.git] / drivers / net / ethernet / amazon / ena / ena_netdev.c
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1738cd3e
NB		 1/*
2 * Copyright 2015 Amazon.com, Inc. or its affiliates.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
34
35#ifdef CONFIG_RFS_ACCEL
36#include <linux/cpu_rmap.h>
37#endif /* CONFIG_RFS_ACCEL */
38#include <linux/ethtool.h>
39#include <linux/if_vlan.h>
40#include <linux/kernel.h>
41#include <linux/module.h>
42#include <linux/moduleparam.h>
43#include <linux/numa.h>
44#include <linux/pci.h>
45#include <linux/utsname.h>
46#include <linux/version.h>
47#include <linux/vmalloc.h>
48#include <net/ip.h>
49
50#include "ena_netdev.h"
51#include "ena_pci_id_tbl.h"
52
53static char version[] = DEVICE_NAME " v" DRV_MODULE_VERSION "\n";
54
55MODULE_AUTHOR("Amazon.com, Inc. or its affiliates");
56MODULE_DESCRIPTION(DEVICE_NAME);
57MODULE_LICENSE("GPL");
58MODULE_VERSION(DRV_MODULE_VERSION);
59
60/* Time in jiffies before concluding the transmitter is hung. */
61#define TX_TIMEOUT (5 * HZ)
62
63#define ENA_NAPI_BUDGET 64
64
65#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | \
66 NETIF_MSG_TX_DONE | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR)
67static int debug = -1;
68module_param(debug, int, 0);
69MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
70
71static struct ena_aenq_handlers aenq_handlers;
72
73static struct workqueue_struct *ena_wq;
74
75MODULE_DEVICE_TABLE(pci, ena_pci_tbl);
76
77static int ena_rss_init_default(struct ena_adapter *adapter);
78
79static void ena_tx_timeout(struct net_device *dev)
80{
81 struct ena_adapter *adapter = netdev_priv(dev);
82
d5796182
NB		 83 /* Change the state of the device to trigger reset
84 * Check that we are not in the middle or a trigger already
85 */
86
87 if (test_and_set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags))
88 return;
89
1738cd3e
NB		 90 u64_stats_update_begin(&adapter->syncp);
91 adapter->dev_stats.tx_timeout++;
92 u64_stats_update_end(&adapter->syncp);
93
94 netif_err(adapter, tx_err, dev, "Transmit time out\n");
1738cd3e
NB		 95}
96
97static void update_rx_ring_mtu(struct ena_adapter *adapter, int mtu)
98{
99 int i;
100
101 for (i = 0; i < adapter->num_queues; i++)
102 adapter->rx_ring[i].mtu = mtu;
103}
104
105static int ena_change_mtu(struct net_device *dev, int new_mtu)
106{
107 struct ena_adapter *adapter = netdev_priv(dev);
108 int ret;
109
1738cd3e
NB		 110 ret = ena_com_set_dev_mtu(adapter->ena_dev, new_mtu);
111 if (!ret) {
112 netif_dbg(adapter, drv, dev, "set MTU to %d\n", new_mtu);
113 update_rx_ring_mtu(adapter, new_mtu);
114 dev->mtu = new_mtu;
115 } else {
116 netif_err(adapter, drv, dev, "Failed to set MTU to %d\n",
117 new_mtu);
118 }
119
120 return ret;
121}
122
123static int ena_init_rx_cpu_rmap(struct ena_adapter *adapter)
124{
125#ifdef CONFIG_RFS_ACCEL
126 u32 i;
127 int rc;
128
129 adapter->netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(adapter->num_queues);
130 if (!adapter->netdev->rx_cpu_rmap)
131 return -ENOMEM;
132 for (i = 0; i < adapter->num_queues; i++) {
133 int irq_idx = ENA_IO_IRQ_IDX(i);
134
135 rc = irq_cpu_rmap_add(adapter->netdev->rx_cpu_rmap,
136 adapter->msix_entries[irq_idx].vector);
137 if (rc) {
138 free_irq_cpu_rmap(adapter->netdev->rx_cpu_rmap);
139 adapter->netdev->rx_cpu_rmap = NULL;
140 return rc;
141 }
142 }
143#endif /* CONFIG_RFS_ACCEL */
144 return 0;
145}
146
147static void ena_init_io_rings_common(struct ena_adapter *adapter,
148 struct ena_ring *ring, u16 qid)
149{
150 ring->qid = qid;
151 ring->pdev = adapter->pdev;
152 ring->dev = &adapter->pdev->dev;
153 ring->netdev = adapter->netdev;
154 ring->napi = &adapter->ena_napi[qid].napi;
155 ring->adapter = adapter;
156 ring->ena_dev = adapter->ena_dev;
157 ring->per_napi_packets = 0;
158 ring->per_napi_bytes = 0;
159 ring->cpu = 0;
160 u64_stats_init(&ring->syncp);
161}
162
163static void ena_init_io_rings(struct ena_adapter *adapter)
164{
165 struct ena_com_dev *ena_dev;
166 struct ena_ring *txr, *rxr;
167 int i;
168
169 ena_dev = adapter->ena_dev;
170
171 for (i = 0; i < adapter->num_queues; i++) {
172 txr = &adapter->tx_ring[i];
173 rxr = &adapter->rx_ring[i];
174
175 /* TX/RX common ring state */
176 ena_init_io_rings_common(adapter, txr, i);
177 ena_init_io_rings_common(adapter, rxr, i);
178
179 /* TX specific ring state */
180 txr->ring_size = adapter->tx_ring_size;
181 txr->tx_max_header_size = ena_dev->tx_max_header_size;
182 txr->tx_mem_queue_type = ena_dev->tx_mem_queue_type;
183 txr->sgl_size = adapter->max_tx_sgl_size;
184 txr->smoothed_interval =
185 ena_com_get_nonadaptive_moderation_interval_tx(ena_dev);
186
187 /* RX specific ring state */
188 rxr->ring_size = adapter->rx_ring_size;
189 rxr->rx_copybreak = adapter->rx_copybreak;
190 rxr->sgl_size = adapter->max_rx_sgl_size;
191 rxr->smoothed_interval =
192 ena_com_get_nonadaptive_moderation_interval_rx(ena_dev);
193 }
194}
195
196/* ena_setup_tx_resources - allocate I/O Tx resources (Descriptors)
197 * @adapter: network interface device structure
198 * @qid: queue index
199 *
200 * Return 0 on success, negative on failure
201 */
202static int ena_setup_tx_resources(struct ena_adapter *adapter, int qid)
203{
204 struct ena_ring *tx_ring = &adapter->tx_ring[qid];
205 struct ena_irq *ena_irq = &adapter->irq_tbl[ENA_IO_IRQ_IDX(qid)];
206 int size, i, node;
207
208 if (tx_ring->tx_buffer_info) {
209 netif_err(adapter, ifup,
210 adapter->netdev, "tx_buffer_info info is not NULL");
211 return -EEXIST;
212 }
213
214 size = sizeof(struct ena_tx_buffer) * tx_ring->ring_size;
215 node = cpu_to_node(ena_irq->cpu);
216
217 tx_ring->tx_buffer_info = vzalloc_node(size, node);
218 if (!tx_ring->tx_buffer_info) {
219 tx_ring->tx_buffer_info = vzalloc(size);
220 if (!tx_ring->tx_buffer_info)
221 return -ENOMEM;
222 }
223
224 size = sizeof(u16) * tx_ring->ring_size;
225 tx_ring->free_tx_ids = vzalloc_node(size, node);
226 if (!tx_ring->free_tx_ids) {
227 tx_ring->free_tx_ids = vzalloc(size);
228 if (!tx_ring->free_tx_ids) {
229 vfree(tx_ring->tx_buffer_info);
230 return -ENOMEM;
231 }
232 }
233
234 /* Req id ring for TX out of order completions */
235 for (i = 0; i < tx_ring->ring_size; i++)
236 tx_ring->free_tx_ids[i] = i;
237
238 /* Reset tx statistics */
239 memset(&tx_ring->tx_stats, 0x0, sizeof(tx_ring->tx_stats));
240
241 tx_ring->next_to_use = 0;
242 tx_ring->next_to_clean = 0;
243 tx_ring->cpu = ena_irq->cpu;
244 return 0;
245}
246
247/* ena_free_tx_resources - Free I/O Tx Resources per Queue
248 * @adapter: network interface device structure
249 * @qid: queue index
250 *
251 * Free all transmit software resources
252 */
253static void ena_free_tx_resources(struct ena_adapter *adapter, int qid)
254{
255 struct ena_ring *tx_ring = &adapter->tx_ring[qid];
256
257 vfree(tx_ring->tx_buffer_info);
258 tx_ring->tx_buffer_info = NULL;
259
260 vfree(tx_ring->free_tx_ids);
261 tx_ring->free_tx_ids = NULL;
262}
263
264/* ena_setup_all_tx_resources - allocate I/O Tx queues resources for All queues
265 * @adapter: private structure
266 *
267 * Return 0 on success, negative on failure
268 */
269static int ena_setup_all_tx_resources(struct ena_adapter *adapter)
270{
271 int i, rc = 0;
272
273 for (i = 0; i < adapter->num_queues; i++) {
274 rc = ena_setup_tx_resources(adapter, i);
275 if (rc)
276 goto err_setup_tx;
277 }
278
279 return 0;
280
281err_setup_tx:
282
283 netif_err(adapter, ifup, adapter->netdev,
284 "Tx queue %d: allocation failed\n", i);
285
286 /* rewind the index freeing the rings as we go */
287 while (i--)
288 ena_free_tx_resources(adapter, i);
289 return rc;
290}
291
292/* ena_free_all_io_tx_resources - Free I/O Tx Resources for All Queues
293 * @adapter: board private structure
294 *
295 * Free all transmit software resources
296 */
297static void ena_free_all_io_tx_resources(struct ena_adapter *adapter)
298{
299 int i;
300
301 for (i = 0; i < adapter->num_queues; i++)
302 ena_free_tx_resources(adapter, i);
303}
304
305/* ena_setup_rx_resources - allocate I/O Rx resources (Descriptors)
306 * @adapter: network interface device structure
307 * @qid: queue index
308 *
309 * Returns 0 on success, negative on failure
310 */
311static int ena_setup_rx_resources(struct ena_adapter *adapter,
312 u32 qid)
313{
314 struct ena_ring *rx_ring = &adapter->rx_ring[qid];
315 struct ena_irq *ena_irq = &adapter->irq_tbl[ENA_IO_IRQ_IDX(qid)];
316 int size, node;
317
318 if (rx_ring->rx_buffer_info) {
319 netif_err(adapter, ifup, adapter->netdev,
320 "rx_buffer_info is not NULL");
321 return -EEXIST;
322 }
323
324 /* alloc extra element so in rx path
325 * we can always prefetch rx_info + 1
326 */
327 size = sizeof(struct ena_rx_buffer) * (rx_ring->ring_size + 1);
328 node = cpu_to_node(ena_irq->cpu);
329
330 rx_ring->rx_buffer_info = vzalloc_node(size, node);
331 if (!rx_ring->rx_buffer_info) {
332 rx_ring->rx_buffer_info = vzalloc(size);
333 if (!rx_ring->rx_buffer_info)
334 return -ENOMEM;
335 }
336
337 /* Reset rx statistics */
338 memset(&rx_ring->rx_stats, 0x0, sizeof(rx_ring->rx_stats));
339
340 rx_ring->next_to_clean = 0;
341 rx_ring->next_to_use = 0;
342 rx_ring->cpu = ena_irq->cpu;
343
344 return 0;
345}
346
347/* ena_free_rx_resources - Free I/O Rx Resources
348 * @adapter: network interface device structure
349 * @qid: queue index
350 *
351 * Free all receive software resources
352 */
353static void ena_free_rx_resources(struct ena_adapter *adapter,
354 u32 qid)
355{
356 struct ena_ring *rx_ring = &adapter->rx_ring[qid];
357
358 vfree(rx_ring->rx_buffer_info);
359 rx_ring->rx_buffer_info = NULL;
360}
361
362/* ena_setup_all_rx_resources - allocate I/O Rx queues resources for all queues
363 * @adapter: board private structure
364 *
365 * Return 0 on success, negative on failure
366 */
367static int ena_setup_all_rx_resources(struct ena_adapter *adapter)
368{
369 int i, rc = 0;
370
371 for (i = 0; i < adapter->num_queues; i++) {
372 rc = ena_setup_rx_resources(adapter, i);
373 if (rc)
374 goto err_setup_rx;
375 }
376
377 return 0;
378
379err_setup_rx:
380
381 netif_err(adapter, ifup, adapter->netdev,
382 "Rx queue %d: allocation failed\n", i);
383
384 /* rewind the index freeing the rings as we go */
385 while (i--)
386 ena_free_rx_resources(adapter, i);
387 return rc;
388}
389
390/* ena_free_all_io_rx_resources - Free I/O Rx Resources for All Queues
391 * @adapter: board private structure
392 *
393 * Free all receive software resources
394 */
395static void ena_free_all_io_rx_resources(struct ena_adapter *adapter)
396{
397 int i;
398
399 for (i = 0; i < adapter->num_queues; i++)
400 ena_free_rx_resources(adapter, i);
401}
402
403static inline int ena_alloc_rx_page(struct ena_ring *rx_ring,
404 struct ena_rx_buffer *rx_info, gfp_t gfp)
405{
406 struct ena_com_buf *ena_buf;
407 struct page *page;
408 dma_addr_t dma;
409
410 /* if previous allocated page is not used */
411 if (unlikely(rx_info->page))
412 return 0;
413
414 page = alloc_page(gfp);
415 if (unlikely(!page)) {
416 u64_stats_update_begin(&rx_ring->syncp);
417 rx_ring->rx_stats.page_alloc_fail++;
418 u64_stats_update_end(&rx_ring->syncp);
419 return -ENOMEM;
420 }
421
422 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE,
423 DMA_FROM_DEVICE);
424 if (unlikely(dma_mapping_error(rx_ring->dev, dma))) {
425 u64_stats_update_begin(&rx_ring->syncp);
426 rx_ring->rx_stats.dma_mapping_err++;
427 u64_stats_update_end(&rx_ring->syncp);
428
429 __free_page(page);
430 return -EIO;
431 }
432 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev,
433 "alloc page %p, rx_info %p\n", page, rx_info);
434
435 rx_info->page = page;
436 rx_info->page_offset = 0;
437 ena_buf = &rx_info->ena_buf;
438 ena_buf->paddr = dma;
439 ena_buf->len = PAGE_SIZE;
440
441 return 0;
442}
443
444static void ena_free_rx_page(struct ena_ring *rx_ring,
445 struct ena_rx_buffer *rx_info)
446{
447 struct page *page = rx_info->page;
448 struct ena_com_buf *ena_buf = &rx_info->ena_buf;
449
450 if (unlikely(!page)) {
451 netif_warn(rx_ring->adapter, rx_err, rx_ring->netdev,
452 "Trying to free unallocated buffer\n");
453 return;
454 }
455
456 dma_unmap_page(rx_ring->dev, ena_buf->paddr, PAGE_SIZE,
457 DMA_FROM_DEVICE);
458
459 __free_page(page);
460 rx_info->page = NULL;
461}
462
463static int ena_refill_rx_bufs(struct ena_ring *rx_ring, u32 num)
464{
465 u16 next_to_use;
466 u32 i;
467 int rc;
468
469 next_to_use = rx_ring->next_to_use;
470
471 for (i = 0; i < num; i++) {
472 struct ena_rx_buffer *rx_info =
473 &rx_ring->rx_buffer_info[next_to_use];
474
475 rc = ena_alloc_rx_page(rx_ring, rx_info,
476 __GFP_COLD | GFP_ATOMIC | __GFP_COMP);
477 if (unlikely(rc < 0)) {
478 netif_warn(rx_ring->adapter, rx_err, rx_ring->netdev,
479 "failed to alloc buffer for rx queue %d\n",
480 rx_ring->qid);
481 break;
482 }
483 rc = ena_com_add_single_rx_desc(rx_ring->ena_com_io_sq,
484 &rx_info->ena_buf,
485 next_to_use);
486 if (unlikely(rc)) {
487 netif_warn(rx_ring->adapter, rx_status, rx_ring->netdev,
488 "failed to add buffer for rx queue %d\n",
489 rx_ring->qid);
490 break;
491 }
492 next_to_use = ENA_RX_RING_IDX_NEXT(next_to_use,
493 rx_ring->ring_size);
494 }
495
496 if (unlikely(i < num)) {
497 u64_stats_update_begin(&rx_ring->syncp);
498 rx_ring->rx_stats.refil_partial++;
499 u64_stats_update_end(&rx_ring->syncp);
500 netdev_warn(rx_ring->netdev,
501 "refilled rx qid %d with only %d buffers (from %d)\n",
502 rx_ring->qid, i, num);
503 }
504
505 if (likely(i)) {
506 /* Add memory barrier to make sure the desc were written before
507 * issue a doorbell
508 */
509 wmb();
510 ena_com_write_sq_doorbell(rx_ring->ena_com_io_sq);
511 }
512
513 rx_ring->next_to_use = next_to_use;
514
515 return i;
516}
517
518static void ena_free_rx_bufs(struct ena_adapter *adapter,
519 u32 qid)
520{
521 struct ena_ring *rx_ring = &adapter->rx_ring[qid];
522 u32 i;
523
524 for (i = 0; i < rx_ring->ring_size; i++) {
525 struct ena_rx_buffer *rx_info = &rx_ring->rx_buffer_info[i];
526
527 if (rx_info->page)
528 ena_free_rx_page(rx_ring, rx_info);
529 }
530}
531
532/* ena_refill_all_rx_bufs - allocate all queues Rx buffers
533 * @adapter: board private structure
534 *
535 */
536static void ena_refill_all_rx_bufs(struct ena_adapter *adapter)
537{
538 struct ena_ring *rx_ring;
539 int i, rc, bufs_num;
540
541 for (i = 0; i < adapter->num_queues; i++) {
542 rx_ring = &adapter->rx_ring[i];
543 bufs_num = rx_ring->ring_size - 1;
544 rc = ena_refill_rx_bufs(rx_ring, bufs_num);
545
546 if (unlikely(rc != bufs_num))
547 netif_warn(rx_ring->adapter, rx_status, rx_ring->netdev,
548 "refilling Queue %d failed. allocated %d buffers from: %d\n",
549 i, rc, bufs_num);
550 }
551}
552
553static void ena_free_all_rx_bufs(struct ena_adapter *adapter)
554{
555 int i;
556
557 for (i = 0; i < adapter->num_queues; i++)
558 ena_free_rx_bufs(adapter, i);
559}
560
561/* ena_free_tx_bufs - Free Tx Buffers per Queue
562 * @tx_ring: TX ring for which buffers be freed
563 */
564static void ena_free_tx_bufs(struct ena_ring *tx_ring)
565{
11a2f0ed 566 bool print_once = true;
1738cd3e
NB		 567 u32 i;
568
569 for (i = 0; i < tx_ring->ring_size; i++) {
570 struct ena_tx_buffer *tx_info = &tx_ring->tx_buffer_info[i];
571 struct ena_com_buf *ena_buf;
572 int nr_frags;
573 int j;
574
575 if (!tx_info->skb)
576 continue;
577
11a2f0ed
NB		 578 if (print_once) {
579 netdev_notice(tx_ring->netdev,
580 "free uncompleted tx skb qid %d idx 0x%x\n",
581 tx_ring->qid, i);
582 print_once = false;
583 } else {
584 netdev_dbg(tx_ring->netdev,
585 "free uncompleted tx skb qid %d idx 0x%x\n",
586 tx_ring->qid, i);
587 }
1738cd3e
NB		 588
589 ena_buf = tx_info->bufs;
590 dma_unmap_single(tx_ring->dev,
591 ena_buf->paddr,
592 ena_buf->len,
593 DMA_TO_DEVICE);
594
595 /* unmap remaining mapped pages */
596 nr_frags = tx_info->num_of_bufs - 1;
597 for (j = 0; j < nr_frags; j++) {
598 ena_buf++;
599 dma_unmap_page(tx_ring->dev,
600 ena_buf->paddr,
601 ena_buf->len,
602 DMA_TO_DEVICE);
603 }
604
605 dev_kfree_skb_any(tx_info->skb);
606 }
607 netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring->netdev,
608 tx_ring->qid));
609}
610
611static void ena_free_all_tx_bufs(struct ena_adapter *adapter)
612{
613 struct ena_ring *tx_ring;
614 int i;
615
616 for (i = 0; i < adapter->num_queues; i++) {
617 tx_ring = &adapter->tx_ring[i];
618 ena_free_tx_bufs(tx_ring);
619 }
620}
621
622static void ena_destroy_all_tx_queues(struct ena_adapter *adapter)
623{
624 u16 ena_qid;
625 int i;
626
627 for (i = 0; i < adapter->num_queues; i++) {
628 ena_qid = ENA_IO_TXQ_IDX(i);
629 ena_com_destroy_io_queue(adapter->ena_dev, ena_qid);
630 }
631}
632
633static void ena_destroy_all_rx_queues(struct ena_adapter *adapter)
634{
635 u16 ena_qid;
636 int i;
637
638 for (i = 0; i < adapter->num_queues; i++) {
639 ena_qid = ENA_IO_RXQ_IDX(i);
640 ena_com_destroy_io_queue(adapter->ena_dev, ena_qid);
641 }
642}
643
644static void ena_destroy_all_io_queues(struct ena_adapter *adapter)
645{
646 ena_destroy_all_tx_queues(adapter);
647 ena_destroy_all_rx_queues(adapter);
648}
649
650static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id)
651{
652 struct ena_tx_buffer *tx_info = NULL;
653
654 if (likely(req_id < tx_ring->ring_size)) {
655 tx_info = &tx_ring->tx_buffer_info[req_id];
656 if (likely(tx_info->skb))
657 return 0;
658 }
659
660 if (tx_info)
661 netif_err(tx_ring->adapter, tx_done, tx_ring->netdev,
662 "tx_info doesn't have valid skb\n");
663 else
664 netif_err(tx_ring->adapter, tx_done, tx_ring->netdev,
665 "Invalid req_id: %hu\n", req_id);
666
667 u64_stats_update_begin(&tx_ring->syncp);
668 tx_ring->tx_stats.bad_req_id++;
669 u64_stats_update_end(&tx_ring->syncp);
670
671 /* Trigger device reset */
672 set_bit(ENA_FLAG_TRIGGER_RESET, &tx_ring->adapter->flags);
673 return -EFAULT;
674}
675
676static int ena_clean_tx_irq(struct ena_ring *tx_ring, u32 budget)
677{
678 struct netdev_queue *txq;
679 bool above_thresh;
680 u32 tx_bytes = 0;
681 u32 total_done = 0;
682 u16 next_to_clean;
683 u16 req_id;
684 int tx_pkts = 0;
685 int rc;
686
687 next_to_clean = tx_ring->next_to_clean;
688 txq = netdev_get_tx_queue(tx_ring->netdev, tx_ring->qid);
689
690 while (tx_pkts < budget) {
691 struct ena_tx_buffer *tx_info;
692 struct sk_buff *skb;
693 struct ena_com_buf *ena_buf;
694 int i, nr_frags;
695
696 rc = ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq,
697 &req_id);
698 if (rc)
699 break;
700
701 rc = validate_tx_req_id(tx_ring, req_id);
702 if (rc)
703 break;
704
705 tx_info = &tx_ring->tx_buffer_info[req_id];
706 skb = tx_info->skb;
707
708 /* prefetch skb_end_pointer() to speedup skb_shinfo(skb) */
709 prefetch(&skb->end);
710
711 tx_info->skb = NULL;
712 tx_info->last_jiffies = 0;
713
714 if (likely(tx_info->num_of_bufs != 0)) {
715 ena_buf = tx_info->bufs;
716
717 dma_unmap_single(tx_ring->dev,
718 dma_unmap_addr(ena_buf, paddr),
719 dma_unmap_len(ena_buf, len),
720 DMA_TO_DEVICE);
721
722 /* unmap remaining mapped pages */
723 nr_frags = tx_info->num_of_bufs - 1;
724 for (i = 0; i < nr_frags; i++) {
725 ena_buf++;
726 dma_unmap_page(tx_ring->dev,
727 dma_unmap_addr(ena_buf, paddr),
728 dma_unmap_len(ena_buf, len),
729 DMA_TO_DEVICE);
730 }
731 }
732
733 netif_dbg(tx_ring->adapter, tx_done, tx_ring->netdev,
734 "tx_poll: q %d skb %p completed\n", tx_ring->qid,
735 skb);
736
737 tx_bytes += skb->len;
738 dev_kfree_skb(skb);
739 tx_pkts++;
740 total_done += tx_info->tx_descs;
741
742 tx_ring->free_tx_ids[next_to_clean] = req_id;
743 next_to_clean = ENA_TX_RING_IDX_NEXT(next_to_clean,
744 tx_ring->ring_size);
745 }
746
747 tx_ring->next_to_clean = next_to_clean;
748 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_done);
749 ena_com_update_dev_comp_head(tx_ring->ena_com_io_cq);
750
751 netdev_tx_completed_queue(txq, tx_pkts, tx_bytes);
752
753 netif_dbg(tx_ring->adapter, tx_done, tx_ring->netdev,
754 "tx_poll: q %d done. total pkts: %d\n",
755 tx_ring->qid, tx_pkts);
756
757 /* need to make the rings circular update visible to
758 * ena_start_xmit() before checking for netif_queue_stopped().
759 */
760 smp_mb();
761
762 above_thresh = ena_com_sq_empty_space(tx_ring->ena_com_io_sq) >
763 ENA_TX_WAKEUP_THRESH;
764 if (unlikely(netif_tx_queue_stopped(txq) && above_thresh)) {
765 __netif_tx_lock(txq, smp_processor_id());
766 above_thresh = ena_com_sq_empty_space(tx_ring->ena_com_io_sq) >
767 ENA_TX_WAKEUP_THRESH;
768 if (netif_tx_queue_stopped(txq) && above_thresh) {
769 netif_tx_wake_queue(txq);
770 u64_stats_update_begin(&tx_ring->syncp);
771 tx_ring->tx_stats.queue_wakeup++;
772 u64_stats_update_end(&tx_ring->syncp);
773 }
774 __netif_tx_unlock(txq);
775 }
776
777 tx_ring->per_napi_bytes += tx_bytes;
778 tx_ring->per_napi_packets += tx_pkts;
779
780 return tx_pkts;
781}
782
783static struct sk_buff *ena_rx_skb(struct ena_ring *rx_ring,
784 struct ena_com_rx_buf_info *ena_bufs,
785 u32 descs,
786 u16 *next_to_clean)
787{
788 struct sk_buff *skb;
789 struct ena_rx_buffer *rx_info =
790 &rx_ring->rx_buffer_info[*next_to_clean];
791 u32 len;
792 u32 buf = 0;
793 void *va;
794
795 len = ena_bufs[0].len;
796 if (unlikely(!rx_info->page)) {
797 netif_err(rx_ring->adapter, rx_err, rx_ring->netdev,
798 "Page is NULL\n");
799 return NULL;
800 }
801
802 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev,
803 "rx_info %p page %p\n",
804 rx_info, rx_info->page);
805
806 /* save virt address of first buffer */
807 va = page_address(rx_info->page) + rx_info->page_offset;
808 prefetch(va + NET_IP_ALIGN);
809
810 if (len <= rx_ring->rx_copybreak) {
811 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
812 rx_ring->rx_copybreak);
813 if (unlikely(!skb)) {
814 u64_stats_update_begin(&rx_ring->syncp);
815 rx_ring->rx_stats.skb_alloc_fail++;
816 u64_stats_update_end(&rx_ring->syncp);
817 netif_err(rx_ring->adapter, rx_err, rx_ring->netdev,
818 "Failed to allocate skb\n");
819 return NULL;
820 }
821
822 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev,
823 "rx allocated small packet. len %d. data_len %d\n",
824 skb->len, skb->data_len);
825
826 /* sync this buffer for CPU use */
827 dma_sync_single_for_cpu(rx_ring->dev,
828 dma_unmap_addr(&rx_info->ena_buf, paddr),
829 len,
830 DMA_FROM_DEVICE);
831 skb_copy_to_linear_data(skb, va, len);
832 dma_sync_single_for_device(rx_ring->dev,
833 dma_unmap_addr(&rx_info->ena_buf, paddr),
834 len,
835 DMA_FROM_DEVICE);
836
837 skb_put(skb, len);
838 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
839 *next_to_clean = ENA_RX_RING_IDX_ADD(*next_to_clean, descs,
840 rx_ring->ring_size);
841 return skb;
842 }
843
844 skb = napi_get_frags(rx_ring->napi);
845 if (unlikely(!skb)) {
846 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev,
847 "Failed allocating skb\n");
848 u64_stats_update_begin(&rx_ring->syncp);
849 rx_ring->rx_stats.skb_alloc_fail++;
850 u64_stats_update_end(&rx_ring->syncp);
851 return NULL;
852 }
853
854 do {
855 dma_unmap_page(rx_ring->dev,
856 dma_unmap_addr(&rx_info->ena_buf, paddr),
857 PAGE_SIZE, DMA_FROM_DEVICE);
858
859 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_info->page,
860 rx_info->page_offset, len, PAGE_SIZE);
861
862 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev,
863 "rx skb updated. len %d. data_len %d\n",
864 skb->len, skb->data_len);
865
866 rx_info->page = NULL;
867 *next_to_clean =
868 ENA_RX_RING_IDX_NEXT(*next_to_clean,
869 rx_ring->ring_size);
870 if (likely(--descs == 0))
871 break;
872 rx_info = &rx_ring->rx_buffer_info[*next_to_clean];
873 len = ena_bufs[++buf].len;
874 } while (1);
875
876 return skb;
877}
878
879/* ena_rx_checksum - indicate in skb if hw indicated a good cksum
880 * @adapter: structure containing adapter specific data
881 * @ena_rx_ctx: received packet context/metadata
882 * @skb: skb currently being received and modified
883 */
884static inline void ena_rx_checksum(struct ena_ring *rx_ring,
885 struct ena_com_rx_ctx *ena_rx_ctx,
886 struct sk_buff *skb)
887{
888 /* Rx csum disabled */
889 if (unlikely(!(rx_ring->netdev->features & NETIF_F_RXCSUM))) {
890 skb->ip_summed = CHECKSUM_NONE;
891 return;
892 }
893
894 /* For fragmented packets the checksum isn't valid */
895 if (ena_rx_ctx->frag) {
896 skb->ip_summed = CHECKSUM_NONE;
897 return;
898 }
899
900 /* if IP and error */
901 if (unlikely((ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4) &&
902 (ena_rx_ctx->l3_csum_err))) {
903 /* ipv4 checksum error */
904 skb->ip_summed = CHECKSUM_NONE;
905 u64_stats_update_begin(&rx_ring->syncp);
906 rx_ring->rx_stats.bad_csum++;
907 u64_stats_update_end(&rx_ring->syncp);
908 netif_err(rx_ring->adapter, rx_err, rx_ring->netdev,
909 "RX IPv4 header checksum error\n");
910 return;
911 }
912
913 /* if TCP/UDP */
914 if (likely((ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP) ||
915 (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP))) {
916 if (unlikely(ena_rx_ctx->l4_csum_err)) {
917 /* TCP/UDP checksum error */
918 u64_stats_update_begin(&rx_ring->syncp);
919 rx_ring->rx_stats.bad_csum++;
920 u64_stats_update_end(&rx_ring->syncp);
921 netif_err(rx_ring->adapter, rx_err, rx_ring->netdev,
922 "RX L4 checksum error\n");
923 skb->ip_summed = CHECKSUM_NONE;
924 return;
925 }
926
927 skb->ip_summed = CHECKSUM_UNNECESSARY;
928 }
929}
930
931static void ena_set_rx_hash(struct ena_ring *rx_ring,
932 struct ena_com_rx_ctx *ena_rx_ctx,
933 struct sk_buff *skb)
934{
935 enum pkt_hash_types hash_type;
936
937 if (likely(rx_ring->netdev->features & NETIF_F_RXHASH)) {
938 if (likely((ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP) ||
939 (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)))
940
941 hash_type = PKT_HASH_TYPE_L4;
942 else
943 hash_type = PKT_HASH_TYPE_NONE;
944
945 /* Override hash type if the packet is fragmented */
946 if (ena_rx_ctx->frag)
947 hash_type = PKT_HASH_TYPE_NONE;
948
949 skb_set_hash(skb, ena_rx_ctx->hash, hash_type);
950 }
951}
952
953/* ena_clean_rx_irq - Cleanup RX irq
954 * @rx_ring: RX ring to clean
955 * @napi: napi handler
956 * @budget: how many packets driver is allowed to clean
957 *
958 * Returns the number of cleaned buffers.
959 */
960static int ena_clean_rx_irq(struct ena_ring *rx_ring, struct napi_struct *napi,
961 u32 budget)
962{
963 u16 next_to_clean = rx_ring->next_to_clean;
964 u32 res_budget, work_done;
965
966 struct ena_com_rx_ctx ena_rx_ctx;
967 struct ena_adapter *adapter;
968 struct sk_buff *skb;
969 int refill_required;
970 int refill_threshold;
971 int rc = 0;
972 int total_len = 0;
973 int rx_copybreak_pkt = 0;
974
975 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev,
976 "%s qid %d\n", __func__, rx_ring->qid);
977 res_budget = budget;
978
979 do {
980 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
981 ena_rx_ctx.max_bufs = rx_ring->sgl_size;
982 ena_rx_ctx.descs = 0;
983 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
984 rx_ring->ena_com_io_sq,
985 &ena_rx_ctx);
986 if (unlikely(rc))
987 goto error;
988
989 if (unlikely(ena_rx_ctx.descs == 0))
990 break;
991
992 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev,
993 "rx_poll: q %d got packet from ena. descs #: %d l3 proto %d l4 proto %d hash: %x\n",
994 rx_ring->qid, ena_rx_ctx.descs, ena_rx_ctx.l3_proto,
995 ena_rx_ctx.l4_proto, ena_rx_ctx.hash);
996
997 /* allocate skb and fill it */
998 skb = ena_rx_skb(rx_ring, rx_ring->ena_bufs, ena_rx_ctx.descs,
999 &next_to_clean);
1000
1001 /* exit if we failed to retrieve a buffer */
1002 if (unlikely(!skb)) {
1003 next_to_clean = ENA_RX_RING_IDX_ADD(next_to_clean,
1004 ena_rx_ctx.descs,
1005 rx_ring->ring_size);
1006 break;
1007 }
1008
1009 ena_rx_checksum(rx_ring, &ena_rx_ctx, skb);
1010
1011 ena_set_rx_hash(rx_ring, &ena_rx_ctx, skb);
1012
1013 skb_record_rx_queue(skb, rx_ring->qid);
1014
1015 if (rx_ring->ena_bufs[0].len <= rx_ring->rx_copybreak) {
1016 total_len += rx_ring->ena_bufs[0].len;
1017 rx_copybreak_pkt++;
1018 napi_gro_receive(napi, skb);
1019 } else {
1020 total_len += skb->len;
1021 napi_gro_frags(napi);
1022 }
1023
1024 res_budget--;
1025 } while (likely(res_budget));
1026
1027 work_done = budget - res_budget;
1028 rx_ring->per_napi_bytes += total_len;
1029 rx_ring->per_napi_packets += work_done;
1030 u64_stats_update_begin(&rx_ring->syncp);
1031 rx_ring->rx_stats.bytes += total_len;
1032 rx_ring->rx_stats.cnt += work_done;
1033 rx_ring->rx_stats.rx_copybreak_pkt += rx_copybreak_pkt;
1034 u64_stats_update_end(&rx_ring->syncp);
1035
1036 rx_ring->next_to_clean = next_to_clean;
1037
1038 refill_required = ena_com_sq_empty_space(rx_ring->ena_com_io_sq);
1039 refill_threshold = rx_ring->ring_size / ENA_RX_REFILL_THRESH_DIVIDER;
1040
1041 /* Optimization, try to batch new rx buffers */
1042 if (refill_required > refill_threshold) {
1043 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq);
1044 ena_refill_rx_bufs(rx_ring, refill_required);
1045 }
1046
1047 return work_done;
1048
1049error:
1050 adapter = netdev_priv(rx_ring->netdev);
1051
1052 u64_stats_update_begin(&rx_ring->syncp);
1053 rx_ring->rx_stats.bad_desc_num++;
1054 u64_stats_update_end(&rx_ring->syncp);
1055
1056 /* Too many desc from the device. Trigger reset */
1057 set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags);
1058
1059 return 0;
1060}
1061
1062inline void ena_adjust_intr_moderation(struct ena_ring *rx_ring,
1063 struct ena_ring *tx_ring)
1064{
1065 /* We apply adaptive moderation on Rx path only.
1066 * Tx uses static interrupt moderation.
1067 */
1068 ena_com_calculate_interrupt_delay(rx_ring->ena_dev,
1069 rx_ring->per_napi_packets,
1070 rx_ring->per_napi_bytes,
1071 &rx_ring->smoothed_interval,
1072 &rx_ring->moder_tbl_idx);
1073
1074 /* Reset per napi packets/bytes */
1075 tx_ring->per_napi_packets = 0;
1076 tx_ring->per_napi_bytes = 0;
1077 rx_ring->per_napi_packets = 0;
1078 rx_ring->per_napi_bytes = 0;
1079}
1080
1081static inline void ena_update_ring_numa_node(struct ena_ring *tx_ring,
1082 struct ena_ring *rx_ring)
1083{
1084 int cpu = get_cpu();
1085 int numa_node;
1086
1087 /* Check only one ring since the 2 rings are running on the same cpu */
1088 if (likely(tx_ring->cpu == cpu))
1089 goto out;
1090
1091 numa_node = cpu_to_node(cpu);
1092 put_cpu();
1093
1094 if (numa_node != NUMA_NO_NODE) {
1095 ena_com_update_numa_node(tx_ring->ena_com_io_cq, numa_node);
1096 ena_com_update_numa_node(rx_ring->ena_com_io_cq, numa_node);
1097 }
1098
1099 tx_ring->cpu = cpu;
1100 rx_ring->cpu = cpu;
1101
1102 return;
1103out:
1104 put_cpu();
1105}
1106
1107static int ena_io_poll(struct napi_struct *napi, int budget)
1108{
1109 struct ena_napi *ena_napi = container_of(napi, struct ena_napi, napi);
1110 struct ena_ring *tx_ring, *rx_ring;
1111 struct ena_eth_io_intr_reg intr_reg;
1112
1113 u32 tx_work_done;
1114 u32 rx_work_done;
1115 int tx_budget;
1116 int napi_comp_call = 0;
1117 int ret;
1118
1119 tx_ring = ena_napi->tx_ring;
1120 rx_ring = ena_napi->rx_ring;
1121
1122 tx_budget = tx_ring->ring_size / ENA_TX_POLL_BUDGET_DIVIDER;
1123
d5796182
NB		 1124 if (!test_bit(ENA_FLAG_DEV_UP, &tx_ring->adapter->flags) ||
1125 test_bit(ENA_FLAG_TRIGGER_RESET, &tx_ring->adapter->flags)) {
1738cd3e
NB		 1126 napi_complete_done(napi, 0);
1127 return 0;
1128 }
1129
1130 tx_work_done = ena_clean_tx_irq(tx_ring, tx_budget);
1131 rx_work_done = ena_clean_rx_irq(rx_ring, napi, budget);
1132
e9b1d2a8
NB		 1133 /* If the device is about to reset or down, avoid unmask
1134 * the interrupt and return 0 so NAPI won't reschedule
1135 */
1136 if (unlikely(!test_bit(ENA_FLAG_DEV_UP, &tx_ring->adapter->flags) ||
1137 test_bit(ENA_FLAG_TRIGGER_RESET, &tx_ring->adapter->flags))) {
1138 napi_complete_done(napi, 0);
1139 ret = 0;
1738cd3e 1140
e9b1d2a8 1141 } else if ((budget > rx_work_done) && (tx_budget > tx_work_done)) {
1738cd3e 1142 napi_comp_call = 1;
1738cd3e 1143
e9b1d2a8
NB		 1144 /* Update numa and unmask the interrupt only when schedule
1145 * from the interrupt context (vs from sk_busy_loop)
1738cd3e 1146 */
e9b1d2a8
NB		 1147 if (napi_complete_done(napi, rx_work_done)) {
1148 /* Tx and Rx share the same interrupt vector */
1149 if (ena_com_get_adaptive_moderation_enabled(rx_ring->ena_dev))
1150 ena_adjust_intr_moderation(rx_ring, tx_ring);
1151
1152 /* Update intr register: rx intr delay,
1153 * tx intr delay and interrupt unmask
1154 */
1155 ena_com_update_intr_reg(&intr_reg,
1156 rx_ring->smoothed_interval,
1157 tx_ring->smoothed_interval,
1158 true);
1159
1160 /* It is a shared MSI-X.
1161 * Tx and Rx CQ have pointer to it.
1162 * So we use one of them to reach the intr reg
1163 */
1164 ena_com_unmask_intr(rx_ring->ena_com_io_cq, &intr_reg);
1165 }
1738cd3e 1166
1738cd3e
NB		 1167
1168 ena_update_ring_numa_node(tx_ring, rx_ring);
1169
1170 ret = rx_work_done;
1171 } else {
1172 ret = budget;
1173 }
1174
1175 u64_stats_update_begin(&tx_ring->syncp);
1176 tx_ring->tx_stats.napi_comp += napi_comp_call;
1177 tx_ring->tx_stats.tx_poll++;
1178 u64_stats_update_end(&tx_ring->syncp);
1179
1180 return ret;
1181}
1182
1183static irqreturn_t ena_intr_msix_mgmnt(int irq, void *data)
1184{
1185 struct ena_adapter *adapter = (struct ena_adapter *)data;
1186
1187 ena_com_admin_q_comp_intr_handler(adapter->ena_dev);
1188
1189 /* Don't call the aenq handler before probe is done */
1190 if (likely(test_bit(ENA_FLAG_DEVICE_RUNNING, &adapter->flags)))
1191 ena_com_aenq_intr_handler(adapter->ena_dev, data);
1192
1193 return IRQ_HANDLED;
1194}
1195
1196/* ena_intr_msix_io - MSI-X Interrupt Handler for Tx/Rx
1197 * @irq: interrupt number
1198 * @data: pointer to a network interface private napi device structure
1199 */
1200static irqreturn_t ena_intr_msix_io(int irq, void *data)
1201{
1202 struct ena_napi *ena_napi = data;
1203
1204 napi_schedule(&ena_napi->napi);
1205
1206 return IRQ_HANDLED;
1207}
1208
1209static int ena_enable_msix(struct ena_adapter *adapter, int num_queues)
1210{
1211 int i, msix_vecs, rc;
1212
1213 if (test_bit(ENA_FLAG_MSIX_ENABLED, &adapter->flags)) {
1214 netif_err(adapter, probe, adapter->netdev,
1215 "Error, MSI-X is already enabled\n");
1216 return -EPERM;
1217 }
1218
1219 /* Reserved the max msix vectors we might need */
1220 msix_vecs = ENA_MAX_MSIX_VEC(num_queues);
1221
1222 netif_dbg(adapter, probe, adapter->netdev,
1223 "trying to enable MSI-X, vectors %d\n", msix_vecs);
1224
1225 adapter->msix_entries = vzalloc(msix_vecs * sizeof(struct msix_entry));
1226
1227 if (!adapter->msix_entries)
1228 return -ENOMEM;
1229
1230 for (i = 0; i < msix_vecs; i++)
1231 adapter->msix_entries[i].entry = i;
1232
1233 rc = pci_enable_msix(adapter->pdev, adapter->msix_entries, msix_vecs);
1234 if (rc != 0) {
1235 netif_err(adapter, probe, adapter->netdev,
1236 "Failed to enable MSI-X, vectors %d rc %d\n",
1237 msix_vecs, rc);
1238 return -ENOSPC;
1239 }
1240
1241 netif_dbg(adapter, probe, adapter->netdev, "enable MSI-X, vectors %d\n",
1242 msix_vecs);
1243
1244 if (msix_vecs >= 1) {
1245 if (ena_init_rx_cpu_rmap(adapter))
1246 netif_warn(adapter, probe, adapter->netdev,
1247 "Failed to map IRQs to CPUs\n");
1248 }
1249
1250 adapter->msix_vecs = msix_vecs;
1251 set_bit(ENA_FLAG_MSIX_ENABLED, &adapter->flags);
1252
1253 return 0;
1254}
1255
1256static void ena_setup_mgmnt_intr(struct ena_adapter *adapter)
1257{
1258 u32 cpu;
1259
1260 snprintf(adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].name,
1261 ENA_IRQNAME_SIZE, "ena-mgmnt@pci:%s",
1262 pci_name(adapter->pdev));
1263 adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].handler =
1264 ena_intr_msix_mgmnt;
1265 adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].data = adapter;
1266 adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].vector =
1267 adapter->msix_entries[ENA_MGMNT_IRQ_IDX].vector;
1268 cpu = cpumask_first(cpu_online_mask);
1269 adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].cpu = cpu;
1270 cpumask_set_cpu(cpu,
1271 &adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].affinity_hint_mask);
1272}
1273
1274static void ena_setup_io_intr(struct ena_adapter *adapter)
1275{
1276 struct net_device *netdev;
1277 int irq_idx, i, cpu;
1278
1279 netdev = adapter->netdev;
1280
1281 for (i = 0; i < adapter->num_queues; i++) {
1282 irq_idx = ENA_IO_IRQ_IDX(i);
1283 cpu = i % num_online_cpus();
1284
1285 snprintf(adapter->irq_tbl[irq_idx].name, ENA_IRQNAME_SIZE,
1286 "%s-Tx-Rx-%d", netdev->name, i);
1287 adapter->irq_tbl[irq_idx].handler = ena_intr_msix_io;
1288 adapter->irq_tbl[irq_idx].data = &adapter->ena_napi[i];
1289 adapter->irq_tbl[irq_idx].vector =
1290 adapter->msix_entries[irq_idx].vector;
1291 adapter->irq_tbl[irq_idx].cpu = cpu;
1292
1293 cpumask_set_cpu(cpu,
1294 &adapter->irq_tbl[irq_idx].affinity_hint_mask);
1295 }
1296}
1297
1298static int ena_request_mgmnt_irq(struct ena_adapter *adapter)
1299{
1300 unsigned long flags = 0;
1301 struct ena_irq *irq;
1302 int rc;
1303
1304 irq = &adapter->irq_tbl[ENA_MGMNT_IRQ_IDX];
1305 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
1306 irq->data);
1307 if (rc) {
1308 netif_err(adapter, probe, adapter->netdev,
1309 "failed to request admin irq\n");
1310 return rc;
1311 }
1312
1313 netif_dbg(adapter, probe, adapter->netdev,
1314 "set affinity hint of mgmnt irq.to 0x%lx (irq vector: %d)\n",
1315 irq->affinity_hint_mask.bits[0], irq->vector);
1316
1317 irq_set_affinity_hint(irq->vector, &irq->affinity_hint_mask);
1318
1319 return rc;
1320}
1321
1322static int ena_request_io_irq(struct ena_adapter *adapter)
1323{
1324 unsigned long flags = 0;
1325 struct ena_irq *irq;
1326 int rc = 0, i, k;
1327
1328 if (!test_bit(ENA_FLAG_MSIX_ENABLED, &adapter->flags)) {
1329 netif_err(adapter, ifup, adapter->netdev,
1330 "Failed to request I/O IRQ: MSI-X is not enabled\n");
1331 return -EINVAL;
1332 }
1333
1334 for (i = ENA_IO_IRQ_FIRST_IDX; i < adapter->msix_vecs; i++) {
1335 irq = &adapter->irq_tbl[i];
1336 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
1337 irq->data);
1338 if (rc) {
1339 netif_err(adapter, ifup, adapter->netdev,
1340 "Failed to request I/O IRQ. index %d rc %d\n",
1341 i, rc);
1342 goto err;
1343 }
1344
1345 netif_dbg(adapter, ifup, adapter->netdev,
1346 "set affinity hint of irq. index %d to 0x%lx (irq vector: %d)\n",
1347 i, irq->affinity_hint_mask.bits[0], irq->vector);
1348
1349 irq_set_affinity_hint(irq->vector, &irq->affinity_hint_mask);
1350 }
1351
1352 return rc;
1353
1354err:
1355 for (k = ENA_IO_IRQ_FIRST_IDX; k < i; k++) {
1356 irq = &adapter->irq_tbl[k];
1357 free_irq(irq->vector, irq->data);
1358 }
1359
1360 return rc;
1361}
1362
1363static void ena_free_mgmnt_irq(struct ena_adapter *adapter)
1364{
1365 struct ena_irq *irq;
1366
1367 irq = &adapter->irq_tbl[ENA_MGMNT_IRQ_IDX];
1368 synchronize_irq(irq->vector);
1369 irq_set_affinity_hint(irq->vector, NULL);
1370 free_irq(irq->vector, irq->data);
1371}
1372
1373static void ena_free_io_irq(struct ena_adapter *adapter)
1374{
1375 struct ena_irq *irq;
1376 int i;
1377
1378#ifdef CONFIG_RFS_ACCEL
1379 if (adapter->msix_vecs >= 1) {
1380 free_irq_cpu_rmap(adapter->netdev->rx_cpu_rmap);
1381 adapter->netdev->rx_cpu_rmap = NULL;
1382 }
1383#endif /* CONFIG_RFS_ACCEL */
1384
1385 for (i = ENA_IO_IRQ_FIRST_IDX; i < adapter->msix_vecs; i++) {
1386 irq = &adapter->irq_tbl[i];
1387 irq_set_affinity_hint(irq->vector, NULL);
1388 free_irq(irq->vector, irq->data);
1389 }
1390}
1391
1392static void ena_disable_msix(struct ena_adapter *adapter)
1393{
1394 if (test_and_clear_bit(ENA_FLAG_MSIX_ENABLED, &adapter->flags))
1395 pci_disable_msix(adapter->pdev);
1396
1397 if (adapter->msix_entries)
1398 vfree(adapter->msix_entries);
1399 adapter->msix_entries = NULL;
1400}
1401
1402static void ena_disable_io_intr_sync(struct ena_adapter *adapter)
1403{
1404 int i;
1405
1406 if (!netif_running(adapter->netdev))
1407 return;
1408
1409 for (i = ENA_IO_IRQ_FIRST_IDX; i < adapter->msix_vecs; i++)
1410 synchronize_irq(adapter->irq_tbl[i].vector);
1411}
1412
1413static void ena_del_napi(struct ena_adapter *adapter)
1414{
1415 int i;
1416
1417 for (i = 0; i < adapter->num_queues; i++)
1418 netif_napi_del(&adapter->ena_napi[i].napi);
1419}
1420
1421static void ena_init_napi(struct ena_adapter *adapter)
1422{
1423 struct ena_napi *napi;
1424 int i;
1425
1426 for (i = 0; i < adapter->num_queues; i++) {
1427 napi = &adapter->ena_napi[i];
1428
1429 netif_napi_add(adapter->netdev,
1430 &adapter->ena_napi[i].napi,
1431 ena_io_poll,
1432 ENA_NAPI_BUDGET);
1433 napi->rx_ring = &adapter->rx_ring[i];
1434 napi->tx_ring = &adapter->tx_ring[i];
1435 napi->qid = i;
1436 }
1437}
1438
1439static void ena_napi_disable_all(struct ena_adapter *adapter)
1440{
1441 int i;
1442
1443 for (i = 0; i < adapter->num_queues; i++)
1444 napi_disable(&adapter->ena_napi[i].napi);
1445}
1446
1447static void ena_napi_enable_all(struct ena_adapter *adapter)
1448{
1449 int i;
1450
1451 for (i = 0; i < adapter->num_queues; i++)
1452 napi_enable(&adapter->ena_napi[i].napi);
1453}
1454
1455static void ena_restore_ethtool_params(struct ena_adapter *adapter)
1456{
1457 adapter->tx_usecs = 0;
1458 adapter->rx_usecs = 0;
1459 adapter->tx_frames = 1;
1460 adapter->rx_frames = 1;
1461}
1462
1463/* Configure the Rx forwarding */
1464static int ena_rss_configure(struct ena_adapter *adapter)
1465{
1466 struct ena_com_dev *ena_dev = adapter->ena_dev;
1467 int rc;
1468
1469 /* In case the RSS table wasn't initialized by probe */
1470 if (!ena_dev->rss.tbl_log_size) {
1471 rc = ena_rss_init_default(adapter);
1472 if (rc && (rc != -EPERM)) {
1473 netif_err(adapter, ifup, adapter->netdev,
1474 "Failed to init RSS rc: %d\n", rc);
1475 return rc;
1476 }
1477 }
1478
1479 /* Set indirect table */
1480 rc = ena_com_indirect_table_set(ena_dev);
1481 if (unlikely(rc && rc != -EPERM))
1482 return rc;
1483
1484 /* Configure hash function (if supported) */
1485 rc = ena_com_set_hash_function(ena_dev);
1486 if (unlikely(rc && (rc != -EPERM)))
1487 return rc;
1488
1489 /* Configure hash inputs (if supported) */
1490 rc = ena_com_set_hash_ctrl(ena_dev);
1491 if (unlikely(rc && (rc != -EPERM)))
1492 return rc;
1493
1494 return 0;
1495}
1496
1497static int ena_up_complete(struct ena_adapter *adapter)
1498{
1499 int rc, i;
1500
1501 rc = ena_rss_configure(adapter);
1502 if (rc)
1503 return rc;
1504
1505 ena_init_napi(adapter);
1506
1507 ena_change_mtu(adapter->netdev, adapter->netdev->mtu);
1508
1509 ena_refill_all_rx_bufs(adapter);
1510
1511 /* enable transmits */
1512 netif_tx_start_all_queues(adapter->netdev);
1513
1514 ena_restore_ethtool_params(adapter);
1515
1516 ena_napi_enable_all(adapter);
1517
1518 /* schedule napi in case we had pending packets
1519 * from the last time we disable napi
1520 */
1521 for (i = 0; i < adapter->num_queues; i++)
1522 napi_schedule(&adapter->ena_napi[i].napi);
1523
1524 return 0;
1525}
1526
1527static int ena_create_io_tx_queue(struct ena_adapter *adapter, int qid)
1528{
1529 struct ena_com_create_io_ctx ctx = { 0 };
1530 struct ena_com_dev *ena_dev;
1531 struct ena_ring *tx_ring;
1532 u32 msix_vector;
1533 u16 ena_qid;
1534 int rc;
1535
1536 ena_dev = adapter->ena_dev;
1537
1538 tx_ring = &adapter->tx_ring[qid];
1539 msix_vector = ENA_IO_IRQ_IDX(qid);
1540 ena_qid = ENA_IO_TXQ_IDX(qid);
1541
1542 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1543 ctx.qid = ena_qid;
1544 ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1545 ctx.msix_vector = msix_vector;
1546 ctx.queue_size = adapter->tx_ring_size;
1547 ctx.numa_node = cpu_to_node(tx_ring->cpu);
1548
1549 rc = ena_com_create_io_queue(ena_dev, &ctx);
1550 if (rc) {
1551 netif_err(adapter, ifup, adapter->netdev,
1552 "Failed to create I/O TX queue num %d rc: %d\n",
1553 qid, rc);
1554 return rc;
1555 }
1556
1557 rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1558 &tx_ring->ena_com_io_sq,
1559 &tx_ring->ena_com_io_cq);
1560 if (rc) {
1561 netif_err(adapter, ifup, adapter->netdev,
1562 "Failed to get TX queue handlers. TX queue num %d rc: %d\n",
1563 qid, rc);
1564 ena_com_destroy_io_queue(ena_dev, ena_qid);
1565 }
1566
1567 ena_com_update_numa_node(tx_ring->ena_com_io_cq, ctx.numa_node);
1568 return rc;
1569}
1570
1571static int ena_create_all_io_tx_queues(struct ena_adapter *adapter)
1572{
1573 struct ena_com_dev *ena_dev = adapter->ena_dev;
1574 int rc, i;
1575
1576 for (i = 0; i < adapter->num_queues; i++) {
1577 rc = ena_create_io_tx_queue(adapter, i);
1578 if (rc)
1579 goto create_err;
1580 }
1581
1582 return 0;
1583
1584create_err:
1585 while (i--)
1586 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(i));
1587
1588 return rc;
1589}
1590
1591static int ena_create_io_rx_queue(struct ena_adapter *adapter, int qid)
1592{
1593 struct ena_com_dev *ena_dev;
1594 struct ena_com_create_io_ctx ctx = { 0 };
1595 struct ena_ring *rx_ring;
1596 u32 msix_vector;
1597 u16 ena_qid;
1598 int rc;
1599
1600 ena_dev = adapter->ena_dev;
1601
1602 rx_ring = &adapter->rx_ring[qid];
1603 msix_vector = ENA_IO_IRQ_IDX(qid);
1604 ena_qid = ENA_IO_RXQ_IDX(qid);
1605
1606 ctx.qid = ena_qid;
1607 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1608 ctx.mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1609 ctx.msix_vector = msix_vector;
1610 ctx.queue_size = adapter->rx_ring_size;
1611 ctx.numa_node = cpu_to_node(rx_ring->cpu);
1612
1613 rc = ena_com_create_io_queue(ena_dev, &ctx);
1614 if (rc) {
1615 netif_err(adapter, ifup, adapter->netdev,
1616 "Failed to create I/O RX queue num %d rc: %d\n",
1617 qid, rc);
1618 return rc;
1619 }
1620
1621 rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1622 &rx_ring->ena_com_io_sq,
1623 &rx_ring->ena_com_io_cq);
1624 if (rc) {
1625 netif_err(adapter, ifup, adapter->netdev,
1626 "Failed to get RX queue handlers. RX queue num %d rc: %d\n",
1627 qid, rc);
1628 ena_com_destroy_io_queue(ena_dev, ena_qid);
1629 }
1630
1631 ena_com_update_numa_node(rx_ring->ena_com_io_cq, ctx.numa_node);
1632
1633 return rc;
1634}
1635
1636static int ena_create_all_io_rx_queues(struct ena_adapter *adapter)
1637{
1638 struct ena_com_dev *ena_dev = adapter->ena_dev;
1639 int rc, i;
1640
1641 for (i = 0; i < adapter->num_queues; i++) {
1642 rc = ena_create_io_rx_queue(adapter, i);
1643 if (rc)
1644 goto create_err;
1645 }
1646
1647 return 0;
1648
1649create_err:
1650 while (i--)
1651 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(i));
1652
1653 return rc;
1654}
1655
1656static int ena_up(struct ena_adapter *adapter)
1657{
1658 int rc;
1659
1660 netdev_dbg(adapter->netdev, "%s\n", __func__);
1661
1662 ena_setup_io_intr(adapter);
1663
1664 rc = ena_request_io_irq(adapter);
1665 if (rc)
1666 goto err_req_irq;
1667
1668 /* allocate transmit descriptors */
1669 rc = ena_setup_all_tx_resources(adapter);
1670 if (rc)
1671 goto err_setup_tx;
1672
1673 /* allocate receive descriptors */
1674 rc = ena_setup_all_rx_resources(adapter);
1675 if (rc)
1676 goto err_setup_rx;
1677
1678 /* Create TX queues */
1679 rc = ena_create_all_io_tx_queues(adapter);
1680 if (rc)
1681 goto err_create_tx_queues;
1682
1683 /* Create RX queues */
1684 rc = ena_create_all_io_rx_queues(adapter);
1685 if (rc)
1686 goto err_create_rx_queues;
1687
1688 rc = ena_up_complete(adapter);
1689 if (rc)
1690 goto err_up;
1691
1692 if (test_bit(ENA_FLAG_LINK_UP, &adapter->flags))
1693 netif_carrier_on(adapter->netdev);
1694
1695 u64_stats_update_begin(&adapter->syncp);
1696 adapter->dev_stats.interface_up++;
1697 u64_stats_update_end(&adapter->syncp);
1698
1699 set_bit(ENA_FLAG_DEV_UP, &adapter->flags);
1700
1701 return rc;
1702
1703err_up:
1704 ena_destroy_all_rx_queues(adapter);
1705err_create_rx_queues:
1706 ena_destroy_all_tx_queues(adapter);
1707err_create_tx_queues:
1708 ena_free_all_io_rx_resources(adapter);
1709err_setup_rx:
1710 ena_free_all_io_tx_resources(adapter);
1711err_setup_tx:
1712 ena_free_io_irq(adapter);
1713err_req_irq:
1714
1715 return rc;
1716}
1717
1718static void ena_down(struct ena_adapter *adapter)
1719{
1720 netif_info(adapter, ifdown, adapter->netdev, "%s\n", __func__);
1721
1722 clear_bit(ENA_FLAG_DEV_UP, &adapter->flags);
1723
1724 u64_stats_update_begin(&adapter->syncp);
1725 adapter->dev_stats.interface_down++;
1726 u64_stats_update_end(&adapter->syncp);
1727
1738cd3e
NB		 1728 netif_carrier_off(adapter->netdev);
1729 netif_tx_disable(adapter->netdev);
1730
d5796182
NB		 1731 /* After this point the napi handler won't enable the tx queue */
1732 ena_napi_disable_all(adapter);
1733
1738cd3e 1734 /* After destroy the queue there won't be any new interrupts */
d5796182
NB		 1735
1736 if (test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags)) {
1737 int rc;
1738
1739 rc = ena_com_dev_reset(adapter->ena_dev);
1740 if (rc)
1741 dev_err(&adapter->pdev->dev, "Device reset failed\n");
1742 }
1743
1738cd3e
NB		 1744 ena_destroy_all_io_queues(adapter);
1745
1746 ena_disable_io_intr_sync(adapter);
1747 ena_free_io_irq(adapter);
1748 ena_del_napi(adapter);
1749
1750 ena_free_all_tx_bufs(adapter);
1751 ena_free_all_rx_bufs(adapter);
1752 ena_free_all_io_tx_resources(adapter);
1753 ena_free_all_io_rx_resources(adapter);
1754}
1755
1756/* ena_open - Called when a network interface is made active
1757 * @netdev: network interface device structure
1758 *
1759 * Returns 0 on success, negative value on failure
1760 *
1761 * The open entry point is called when a network interface is made
1762 * active by the system (IFF_UP). At this point all resources needed
1763 * for transmit and receive operations are allocated, the interrupt
1764 * handler is registered with the OS, the watchdog timer is started,
1765 * and the stack is notified that the interface is ready.
1766 */
1767static int ena_open(struct net_device *netdev)
1768{
1769 struct ena_adapter *adapter = netdev_priv(netdev);
1770 int rc;
1771
1772 /* Notify the stack of the actual queue counts. */
1773 rc = netif_set_real_num_tx_queues(netdev, adapter->num_queues);
1774 if (rc) {
1775 netif_err(adapter, ifup, netdev, "Can't set num tx queues\n");
1776 return rc;
1777 }
1778
1779 rc = netif_set_real_num_rx_queues(netdev, adapter->num_queues);
1780 if (rc) {
1781 netif_err(adapter, ifup, netdev, "Can't set num rx queues\n");
1782 return rc;
1783 }
1784
1785 rc = ena_up(adapter);
1786 if (rc)
1787 return rc;
1788
1789 return rc;
1790}
1791
1792/* ena_close - Disables a network interface
1793 * @netdev: network interface device structure
1794 *
1795 * Returns 0, this is not allowed to fail
1796 *
1797 * The close entry point is called when an interface is de-activated
1798 * by the OS. The hardware is still under the drivers control, but
1799 * needs to be disabled. A global MAC reset is issued to stop the
1800 * hardware, and all transmit and receive resources are freed.
1801 */
1802static int ena_close(struct net_device *netdev)
1803{
1804 struct ena_adapter *adapter = netdev_priv(netdev);
1805
1806 netif_dbg(adapter, ifdown, netdev, "%s\n", __func__);
1807
1808 if (test_bit(ENA_FLAG_DEV_UP, &adapter->flags))
1809 ena_down(adapter);
1810
1811 return 0;
1812}
1813
1814static void ena_tx_csum(struct ena_com_tx_ctx *ena_tx_ctx, struct sk_buff *skb)
1815{
1816 u32 mss = skb_shinfo(skb)->gso_size;
1817 struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
1818 u8 l4_protocol = 0;
1819
1820 if ((skb->ip_summed == CHECKSUM_PARTIAL) || mss) {
1821 ena_tx_ctx->l4_csum_enable = 1;
1822 if (mss) {
1823 ena_tx_ctx->tso_enable = 1;
1824 ena_meta->l4_hdr_len = tcp_hdr(skb)->doff;
1825 ena_tx_ctx->l4_csum_partial = 0;
1826 } else {
1827 ena_tx_ctx->tso_enable = 0;
1828 ena_meta->l4_hdr_len = 0;
1829 ena_tx_ctx->l4_csum_partial = 1;
1830 }
1831
1832 switch (ip_hdr(skb)->version) {
1833 case IPVERSION:
1834 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
1835 if (ip_hdr(skb)->frag_off & htons(IP_DF))
1836 ena_tx_ctx->df = 1;
1837 if (mss)
1838 ena_tx_ctx->l3_csum_enable = 1;
1839 l4_protocol = ip_hdr(skb)->protocol;
1840 break;
1841 case 6:
1842 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
1843 l4_protocol = ipv6_hdr(skb)->nexthdr;
1844 break;
1845 default:
1846 break;
1847 }
1848
1849 if (l4_protocol == IPPROTO_TCP)
1850 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
1851 else
1852 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
1853
1854 ena_meta->mss = mss;
1855 ena_meta->l3_hdr_len = skb_network_header_len(skb);
1856 ena_meta->l3_hdr_offset = skb_network_offset(skb);
1857 ena_tx_ctx->meta_valid = 1;
1858
1859 } else {
1860 ena_tx_ctx->meta_valid = 0;
1861 }
1862}
1863
1864static int ena_check_and_linearize_skb(struct ena_ring *tx_ring,
1865 struct sk_buff *skb)
1866{
1867 int num_frags, header_len, rc;
1868
1869 num_frags = skb_shinfo(skb)->nr_frags;
1870 header_len = skb_headlen(skb);
1871
1872 if (num_frags < tx_ring->sgl_size)
1873 return 0;
1874
1875 if ((num_frags == tx_ring->sgl_size) &&
1876 (header_len < tx_ring->tx_max_header_size))
1877 return 0;
1878
1879 u64_stats_update_begin(&tx_ring->syncp);
1880 tx_ring->tx_stats.linearize++;
1881 u64_stats_update_end(&tx_ring->syncp);
1882
1883 rc = skb_linearize(skb);
1884 if (unlikely(rc)) {
1885 u64_stats_update_begin(&tx_ring->syncp);
1886 tx_ring->tx_stats.linearize_failed++;
1887 u64_stats_update_end(&tx_ring->syncp);
1888 }
1889
1890 return rc;
1891}
1892
1893/* Called with netif_tx_lock. */
1894static netdev_tx_t ena_start_xmit(struct sk_buff *skb, struct net_device *dev)
1895{
1896 struct ena_adapter *adapter = netdev_priv(dev);
1897 struct ena_tx_buffer *tx_info;
1898 struct ena_com_tx_ctx ena_tx_ctx;
1899 struct ena_ring *tx_ring;
1900 struct netdev_queue *txq;
1901 struct ena_com_buf *ena_buf;
1902 void *push_hdr;
1903 u32 len, last_frag;
1904 u16 next_to_use;
1905 u16 req_id;
1906 u16 push_len;
1907 u16 header_len;
1908 dma_addr_t dma;
1909 int qid, rc, nb_hw_desc;
1910 int i = -1;
1911
1912 netif_dbg(adapter, tx_queued, dev, "%s skb %p\n", __func__, skb);
1913 /* Determine which tx ring we will be placed on */
1914 qid = skb_get_queue_mapping(skb);
1915 tx_ring = &adapter->tx_ring[qid];
1916 txq = netdev_get_tx_queue(dev, qid);
1917
1918 rc = ena_check_and_linearize_skb(tx_ring, skb);
1919 if (unlikely(rc))
1920 goto error_drop_packet;
1921
1922 skb_tx_timestamp(skb);
1923 len = skb_headlen(skb);
1924
1925 next_to_use = tx_ring->next_to_use;
1926 req_id = tx_ring->free_tx_ids[next_to_use];
1927 tx_info = &tx_ring->tx_buffer_info[req_id];
1928 tx_info->num_of_bufs = 0;
1929
1930 WARN(tx_info->skb, "SKB isn't NULL req_id %d\n", req_id);
1931 ena_buf = tx_info->bufs;
1932 tx_info->skb = skb;
1933
1934 if (tx_ring->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1935 /* prepared the push buffer */
1936 push_len = min_t(u32, len, tx_ring->tx_max_header_size);
1937 header_len = push_len;
1938 push_hdr = skb->data;
1939 } else {
1940 push_len = 0;
1941 header_len = min_t(u32, len, tx_ring->tx_max_header_size);
1942 push_hdr = NULL;
1943 }
1944
1945 netif_dbg(adapter, tx_queued, dev,
1946 "skb: %p header_buf->vaddr: %p push_len: %d\n", skb,
1947 push_hdr, push_len);
1948
1949 if (len > push_len) {
1950 dma = dma_map_single(tx_ring->dev, skb->data + push_len,
1951 len - push_len, DMA_TO_DEVICE);
1952 if (dma_mapping_error(tx_ring->dev, dma))
1953 goto error_report_dma_error;
1954
1955 ena_buf->paddr = dma;
1956 ena_buf->len = len - push_len;
1957
1958 ena_buf++;
1959 tx_info->num_of_bufs++;
1960 }
1961
1962 last_frag = skb_shinfo(skb)->nr_frags;
1963
1964 for (i = 0; i < last_frag; i++) {
1965 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1966
1967 len = skb_frag_size(frag);
1968 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, len,
1969 DMA_TO_DEVICE);
1970 if (dma_mapping_error(tx_ring->dev, dma))
1971 goto error_report_dma_error;
1972
1973 ena_buf->paddr = dma;
1974 ena_buf->len = len;
1975 ena_buf++;
1976 }
1977
1978 tx_info->num_of_bufs += last_frag;
1979
1980 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx));
1981 ena_tx_ctx.ena_bufs = tx_info->bufs;
1982 ena_tx_ctx.push_header = push_hdr;
1983 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
1984 ena_tx_ctx.req_id = req_id;
1985 ena_tx_ctx.header_len = header_len;
1986
1987 /* set flags and meta data */
1988 ena_tx_csum(&ena_tx_ctx, skb);
1989
1990 /* prepare the packet's descriptors to dma engine */
1991 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq, &ena_tx_ctx,
1992 &nb_hw_desc);
1993
1994 if (unlikely(rc)) {
1995 netif_err(adapter, tx_queued, dev,
1996 "failed to prepare tx bufs\n");
1997 u64_stats_update_begin(&tx_ring->syncp);
1998 tx_ring->tx_stats.queue_stop++;
1999 tx_ring->tx_stats.prepare_ctx_err++;
2000 u64_stats_update_end(&tx_ring->syncp);
2001 netif_tx_stop_queue(txq);
2002 goto error_unmap_dma;
2003 }
2004
2005 netdev_tx_sent_queue(txq, skb->len);
2006
2007 u64_stats_update_begin(&tx_ring->syncp);
2008 tx_ring->tx_stats.cnt++;
2009 tx_ring->tx_stats.bytes += skb->len;
2010 u64_stats_update_end(&tx_ring->syncp);
2011
2012 tx_info->tx_descs = nb_hw_desc;
2013 tx_info->last_jiffies = jiffies;
2014
2015 tx_ring->next_to_use = ENA_TX_RING_IDX_NEXT(next_to_use,
2016 tx_ring->ring_size);
2017
2018 /* This WMB is aimed to:
2019 * 1 - perform smp barrier before reading next_to_completion
2020 * 2 - make sure the desc were written before trigger DB
2021 */
2022 wmb();
2023
2024 /* stop the queue when no more space available, the packet can have up
2025 * to sgl_size + 2. one for the meta descriptor and one for header
2026 * (if the header is larger than tx_max_header_size).
2027 */
2028 if (unlikely(ena_com_sq_empty_space(tx_ring->ena_com_io_sq) <
2029 (tx_ring->sgl_size + 2))) {
2030 netif_dbg(adapter, tx_queued, dev, "%s stop queue %d\n",
2031 __func__, qid);
2032
2033 netif_tx_stop_queue(txq);
2034 u64_stats_update_begin(&tx_ring->syncp);
2035 tx_ring->tx_stats.queue_stop++;
2036 u64_stats_update_end(&tx_ring->syncp);
2037
2038 /* There is a rare condition where this function decide to
2039 * stop the queue but meanwhile clean_tx_irq updates
2040 * next_to_completion and terminates.
2041 * The queue will remain stopped forever.
2042 * To solve this issue this function perform rmb, check
2043 * the wakeup condition and wake up the queue if needed.
2044 */
2045 smp_rmb();
2046
2047 if (ena_com_sq_empty_space(tx_ring->ena_com_io_sq)
2048 > ENA_TX_WAKEUP_THRESH) {
2049 netif_tx_wake_queue(txq);
2050 u64_stats_update_begin(&tx_ring->syncp);
2051 tx_ring->tx_stats.queue_wakeup++;
2052 u64_stats_update_end(&tx_ring->syncp);
2053 }
2054 }
2055
2056 if (netif_xmit_stopped(txq) || !skb->xmit_more) {
2057 /* trigger the dma engine */
2058 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2059 u64_stats_update_begin(&tx_ring->syncp);
2060 tx_ring->tx_stats.doorbells++;
2061 u64_stats_update_end(&tx_ring->syncp);
2062 }
2063
2064 return NETDEV_TX_OK;
2065
2066error_report_dma_error:
2067 u64_stats_update_begin(&tx_ring->syncp);
2068 tx_ring->tx_stats.dma_mapping_err++;
2069 u64_stats_update_end(&tx_ring->syncp);
2070 netdev_warn(adapter->netdev, "failed to map skb\n");
2071
2072 tx_info->skb = NULL;
2073
2074error_unmap_dma:
2075 if (i >= 0) {
2076 /* save value of frag that failed */
2077 last_frag = i;
2078
2079 /* start back at beginning and unmap skb */
2080 tx_info->skb = NULL;
2081 ena_buf = tx_info->bufs;
2082 dma_unmap_single(tx_ring->dev, dma_unmap_addr(ena_buf, paddr),
2083 dma_unmap_len(ena_buf, len), DMA_TO_DEVICE);
2084
2085 /* unmap remaining mapped pages */
2086 for (i = 0; i < last_frag; i++) {
2087 ena_buf++;
2088 dma_unmap_page(tx_ring->dev, dma_unmap_addr(ena_buf, paddr),
2089 dma_unmap_len(ena_buf, len), DMA_TO_DEVICE);
2090 }
2091 }
2092
2093error_drop_packet:
2094
2095 dev_kfree_skb(skb);
2096 return NETDEV_TX_OK;
2097}
2098
2099#ifdef CONFIG_NET_POLL_CONTROLLER
2100static void ena_netpoll(struct net_device *netdev)
2101{
2102 struct ena_adapter *adapter = netdev_priv(netdev);
2103 int i;
2104
d5796182
NB		 2105 /* Dont schedule NAPI if the driver is in the middle of reset
2106 * or netdev is down.
2107 */
2108
2109 if (!test_bit(ENA_FLAG_DEV_UP, &adapter->flags) ||
2110 test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags))
2111 return;
2112
1738cd3e
NB		 2113 for (i = 0; i < adapter->num_queues; i++)
2114 napi_schedule(&adapter->ena_napi[i].napi);
2115}
2116#endif /* CONFIG_NET_POLL_CONTROLLER */
2117
2118static u16 ena_select_queue(struct net_device *dev, struct sk_buff *skb,
2119 void *accel_priv, select_queue_fallback_t fallback)
2120{
2121 u16 qid;
2122 /* we suspect that this is good for in--kernel network services that
2123 * want to loop incoming skb rx to tx in normal user generated traffic,
2124 * most probably we will not get to this
2125 */
2126 if (skb_rx_queue_recorded(skb))
2127 qid = skb_get_rx_queue(skb);
2128 else
2129 qid = fallback(dev, skb);
2130
2131 return qid;
2132}
2133
2134static void ena_config_host_info(struct ena_com_dev *ena_dev)
2135{
2136 struct ena_admin_host_info *host_info;
2137 int rc;
2138
2139 /* Allocate only the host info */
2140 rc = ena_com_allocate_host_info(ena_dev);
2141 if (rc) {
2142 pr_err("Cannot allocate host info\n");
2143 return;
2144 }
2145
2146 host_info = ena_dev->host_attr.host_info;
2147
2148 host_info->os_type = ENA_ADMIN_OS_LINUX;
2149 host_info->kernel_ver = LINUX_VERSION_CODE;
2150 strncpy(host_info->kernel_ver_str, utsname()->version,
2151 sizeof(host_info->kernel_ver_str) - 1);
2152 host_info->os_dist = 0;
2153 strncpy(host_info->os_dist_str, utsname()->release,
2154 sizeof(host_info->os_dist_str) - 1);
2155 host_info->driver_version =
2156 (DRV_MODULE_VER_MAJOR) |
2157 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
2158 (DRV_MODULE_VER_SUBMINOR << ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
2159
2160 rc = ena_com_set_host_attributes(ena_dev);
2161 if (rc) {
2162 if (rc == -EPERM)
2163 pr_warn("Cannot set host attributes\n");
2164 else
2165 pr_err("Cannot set host attributes\n");
2166
2167 goto err;
2168 }
2169
2170 return;
2171
2172err:
2173 ena_com_delete_host_info(ena_dev);
2174}
2175
2176static void ena_config_debug_area(struct ena_adapter *adapter)
2177{
2178 u32 debug_area_size;
2179 int rc, ss_count;
2180
2181 ss_count = ena_get_sset_count(adapter->netdev, ETH_SS_STATS);
2182 if (ss_count <= 0) {
2183 netif_err(adapter, drv, adapter->netdev,
2184 "SS count is negative\n");
2185 return;
2186 }
2187
2188 /* allocate 32 bytes for each string and 64bit for the value */
2189 debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
2190
2191 rc = ena_com_allocate_debug_area(adapter->ena_dev, debug_area_size);
2192 if (rc) {
2193 pr_err("Cannot allocate debug area\n");
2194 return;
2195 }
2196
2197 rc = ena_com_set_host_attributes(adapter->ena_dev);
2198 if (rc) {
2199 if (rc == -EPERM)
2200 netif_warn(adapter, drv, adapter->netdev,
2201 "Cannot set host attributes\n");
2202 else
2203 netif_err(adapter, drv, adapter->netdev,
2204 "Cannot set host attributes\n");
2205 goto err;
2206 }
2207
2208 return;
2209err:
2210 ena_com_delete_debug_area(adapter->ena_dev);
2211}
2212
2213static struct rtnl_link_stats64 *ena_get_stats64(struct net_device *netdev,
2214 struct rtnl_link_stats64 *stats)
2215{
2216 struct ena_adapter *adapter = netdev_priv(netdev);
e487b3b0
NB		 2217 struct ena_ring *rx_ring, *tx_ring;
2218 unsigned int start;
2219 u64 rx_drops;
2220 int i;
1738cd3e
NB		 2221
2222 if (!test_bit(ENA_FLAG_DEV_UP, &adapter->flags))
2223 return NULL;
2224
e487b3b0
NB		 2225 for (i = 0; i < adapter->num_queues; i++) {
2226 u64 bytes, packets;
2227
2228 tx_ring = &adapter->tx_ring[i];
1738cd3e 2229
e487b3b0
NB		 2230 do {
2231 start = u64_stats_fetch_begin_irq(&tx_ring->syncp);
2232 packets = tx_ring->tx_stats.cnt;
2233 bytes = tx_ring->tx_stats.bytes;
2234 } while (u64_stats_fetch_retry_irq(&tx_ring->syncp, start));
1738cd3e 2235
e487b3b0
NB		 2236 stats->tx_packets += packets;
2237 stats->tx_bytes += bytes;
2238
2239 rx_ring = &adapter->rx_ring[i];
2240
2241 do {
2242 start = u64_stats_fetch_begin_irq(&rx_ring->syncp);
2243 packets = rx_ring->rx_stats.cnt;
2244 bytes = rx_ring->rx_stats.bytes;
2245 } while (u64_stats_fetch_retry_irq(&rx_ring->syncp, start));
2246
2247 stats->rx_packets += packets;
2248 stats->rx_bytes += bytes;
2249 }
2250
2251 do {
2252 start = u64_stats_fetch_begin_irq(&adapter->syncp);
2253 rx_drops = adapter->dev_stats.rx_drops;
2254 } while (u64_stats_fetch_retry_irq(&adapter->syncp, start));
1738cd3e 2255
e487b3b0 2256 stats->rx_dropped = rx_drops;
1738cd3e
NB		 2257
2258 stats->multicast = 0;
2259 stats->collisions = 0;
2260
2261 stats->rx_length_errors = 0;
2262 stats->rx_crc_errors = 0;
2263 stats->rx_frame_errors = 0;
2264 stats->rx_fifo_errors = 0;
2265 stats->rx_missed_errors = 0;
2266 stats->tx_window_errors = 0;
2267
2268 stats->rx_errors = 0;
2269 stats->tx_errors = 0;
2270
2271 return stats;
2272}
2273
2274static const struct net_device_ops ena_netdev_ops = {
2275 .ndo_open = ena_open,
2276 .ndo_stop = ena_close,
2277 .ndo_start_xmit = ena_start_xmit,
2278 .ndo_select_queue = ena_select_queue,
2279 .ndo_get_stats64 = ena_get_stats64,
2280 .ndo_tx_timeout = ena_tx_timeout,
2281 .ndo_change_mtu = ena_change_mtu,
2282 .ndo_set_mac_address = NULL,
2283 .ndo_validate_addr = eth_validate_addr,
2284#ifdef CONFIG_NET_POLL_CONTROLLER
2285 .ndo_poll_controller = ena_netpoll,
2286#endif /* CONFIG_NET_POLL_CONTROLLER */
2287};
2288
2289static void ena_device_io_suspend(struct work_struct *work)
2290{
2291 struct ena_adapter *adapter =
2292 container_of(work, struct ena_adapter, suspend_io_task);
2293 struct net_device *netdev = adapter->netdev;
2294
2295 /* ena_napi_disable_all disables only the IO handling.
2296 * We are still subject to AENQ keep alive watchdog.
2297 */
2298 u64_stats_update_begin(&adapter->syncp);
2299 adapter->dev_stats.io_suspend++;
2300 u64_stats_update_begin(&adapter->syncp);
2301 ena_napi_disable_all(adapter);
2302 netif_tx_lock(netdev);
2303 netif_device_detach(netdev);
2304 netif_tx_unlock(netdev);
2305}
2306
2307static void ena_device_io_resume(struct work_struct *work)
2308{
2309 struct ena_adapter *adapter =
2310 container_of(work, struct ena_adapter, resume_io_task);
2311 struct net_device *netdev = adapter->netdev;
2312
2313 u64_stats_update_begin(&adapter->syncp);
2314 adapter->dev_stats.io_resume++;
2315 u64_stats_update_end(&adapter->syncp);
2316
2317 netif_device_attach(netdev);
2318 ena_napi_enable_all(adapter);
2319}
2320
2321static int ena_device_validate_params(struct ena_adapter *adapter,
2322 struct ena_com_dev_get_features_ctx *get_feat_ctx)
2323{
2324 struct net_device *netdev = adapter->netdev;
2325 int rc;
2326
2327 rc = ether_addr_equal(get_feat_ctx->dev_attr.mac_addr,
2328 adapter->mac_addr);
2329 if (!rc) {
2330 netif_err(adapter, drv, netdev,
2331 "Error, mac address are different\n");
2332 return -EINVAL;
2333 }
2334
2335 if ((get_feat_ctx->max_queues.max_cq_num < adapter->num_queues) ||
2336 (get_feat_ctx->max_queues.max_sq_num < adapter->num_queues)) {
2337 netif_err(adapter, drv, netdev,
2338 "Error, device doesn't support enough queues\n");
2339 return -EINVAL;
2340 }
2341
2342 if (get_feat_ctx->dev_attr.max_mtu < netdev->mtu) {
2343 netif_err(adapter, drv, netdev,
2344 "Error, device max mtu is smaller than netdev MTU\n");
2345 return -EINVAL;
2346 }
2347
2348 return 0;
2349}
2350
2351static int ena_device_init(struct ena_com_dev *ena_dev, struct pci_dev *pdev,
2352 struct ena_com_dev_get_features_ctx *get_feat_ctx,
2353 bool *wd_state)
2354{
2355 struct device *dev = &pdev->dev;
2356 bool readless_supported;
2357 u32 aenq_groups;
2358 int dma_width;
2359 int rc;
2360
2361 rc = ena_com_mmio_reg_read_request_init(ena_dev);
2362 if (rc) {
2363 dev_err(dev, "failed to init mmio read less\n");
2364 return rc;
2365 }
2366
2367 /* The PCIe configuration space revision id indicate if mmio reg
2368 * read is disabled
2369 */
2370 readless_supported = !(pdev->revision & ENA_MMIO_DISABLE_REG_READ);
2371 ena_com_set_mmio_read_mode(ena_dev, readless_supported);
2372
2373 rc = ena_com_dev_reset(ena_dev);
2374 if (rc) {
2375 dev_err(dev, "Can not reset device\n");
2376 goto err_mmio_read_less;
2377 }
2378
2379 rc = ena_com_validate_version(ena_dev);
2380 if (rc) {
2381 dev_err(dev, "device version is too low\n");
2382 goto err_mmio_read_less;
2383 }
2384
2385 dma_width = ena_com_get_dma_width(ena_dev);
2386 if (dma_width < 0) {
2387 dev_err(dev, "Invalid dma width value %d", dma_width);
6e22066f 2388 rc = dma_width;
1738cd3e
NB		 2389 goto err_mmio_read_less;
2390 }
2391
2392 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(dma_width));
2393 if (rc) {
2394 dev_err(dev, "pci_set_dma_mask failed 0x%x\n", rc);
2395 goto err_mmio_read_less;
2396 }
2397
2398 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(dma_width));
2399 if (rc) {
2400 dev_err(dev, "err_pci_set_consistent_dma_mask failed 0x%x\n",
2401 rc);
2402 goto err_mmio_read_less;
2403 }
2404
2405 /* ENA admin level init */
2406 rc = ena_com_admin_init(ena_dev, &aenq_handlers, true);
2407 if (rc) {
2408 dev_err(dev,
2409 "Can not initialize ena admin queue with device\n");
2410 goto err_mmio_read_less;
2411 }
2412
2413 /* To enable the msix interrupts the driver needs to know the number
2414 * of queues. So the driver uses polling mode to retrieve this
2415 * information
2416 */
2417 ena_com_set_admin_polling_mode(ena_dev, true);
2418
bb2eb26a
NB		 2419 ena_config_host_info(ena_dev);
2420
1738cd3e
NB		 2421 /* Get Device Attributes*/
2422 rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
2423 if (rc) {
2424 dev_err(dev, "Cannot get attribute for ena device rc=%d\n", rc);
2425 goto err_admin_init;
2426 }
2427
2428 /* Try to turn all the available aenq groups */
2429 aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) |
2430 BIT(ENA_ADMIN_FATAL_ERROR) |
2431 BIT(ENA_ADMIN_WARNING) |
2432 BIT(ENA_ADMIN_NOTIFICATION) |
2433 BIT(ENA_ADMIN_KEEP_ALIVE);
2434
2435 aenq_groups &= get_feat_ctx->aenq.supported_groups;
2436
2437 rc = ena_com_set_aenq_config(ena_dev, aenq_groups);
2438 if (rc) {
2439 dev_err(dev, "Cannot configure aenq groups rc= %d\n", rc);
2440 goto err_admin_init;
2441 }
2442
2443 *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE));
2444
1738cd3e
NB		 2445 return 0;
2446
2447err_admin_init:
bb2eb26a 2448 ena_com_delete_host_info(ena_dev);
1738cd3e
NB		 2449 ena_com_admin_destroy(ena_dev);
2450err_mmio_read_less:
2451 ena_com_mmio_reg_read_request_destroy(ena_dev);
2452
2453 return rc;
2454}
2455
2456static int ena_enable_msix_and_set_admin_interrupts(struct ena_adapter *adapter,
2457 int io_vectors)
2458{
2459 struct ena_com_dev *ena_dev = adapter->ena_dev;
2460 struct device *dev = &adapter->pdev->dev;
2461 int rc;
2462
2463 rc = ena_enable_msix(adapter, io_vectors);
2464 if (rc) {
2465 dev_err(dev, "Can not reserve msix vectors\n");
2466 return rc;
2467 }
2468
2469 ena_setup_mgmnt_intr(adapter);
2470
2471 rc = ena_request_mgmnt_irq(adapter);
2472 if (rc) {
2473 dev_err(dev, "Can not setup management interrupts\n");
2474 goto err_disable_msix;
2475 }
2476
2477 ena_com_set_admin_polling_mode(ena_dev, false);
2478
2479 ena_com_admin_aenq_enable(ena_dev);
2480
2481 return 0;
2482
2483err_disable_msix:
2484 ena_disable_msix(adapter);
2485
2486 return rc;
2487}
2488
2489static void ena_fw_reset_device(struct work_struct *work)
2490{
2491 struct ena_com_dev_get_features_ctx get_feat_ctx;
2492 struct ena_adapter *adapter =
2493 container_of(work, struct ena_adapter, reset_task);
2494 struct net_device *netdev = adapter->netdev;
2495 struct ena_com_dev *ena_dev = adapter->ena_dev;
2496 struct pci_dev *pdev = adapter->pdev;
2497 bool dev_up, wd_state;
2498 int rc;
2499
d5796182
NB		 2500 if (unlikely(!test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags))) {
2501 dev_err(&pdev->dev,
2502 "device reset schedule while reset bit is off\n");
2503 return;
2504 }
2505
2506 netif_carrier_off(netdev);
2507
1738cd3e
NB		 2508 del_timer_sync(&adapter->timer_service);
2509
2510 rtnl_lock();
2511
2512 dev_up = test_bit(ENA_FLAG_DEV_UP, &adapter->flags);
2513 ena_com_set_admin_running_state(ena_dev, false);
2514
2515 /* After calling ena_close the tx queues and the napi
2516 * are disabled so no one can interfere or touch the
2517 * data structures
2518 */
2519 ena_close(netdev);
2520
1738cd3e
NB		 2521 ena_free_mgmnt_irq(adapter);
2522
2523 ena_disable_msix(adapter);
2524
2525 ena_com_abort_admin_commands(ena_dev);
2526
2527 ena_com_wait_for_abort_completion(ena_dev);
2528
2529 ena_com_admin_destroy(ena_dev);
2530
2531 ena_com_mmio_reg_read_request_destroy(ena_dev);
2532
d5796182
NB		 2533 clear_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags);
2534
1738cd3e
NB		 2535 /* Finish with the destroy part. Start the init part */
2536
2537 rc = ena_device_init(ena_dev, adapter->pdev, &get_feat_ctx, &wd_state);
2538 if (rc) {
2539 dev_err(&pdev->dev, "Can not initialize device\n");
2540 goto err;
2541 }
2542 adapter->wd_state = wd_state;
2543
2544 rc = ena_device_validate_params(adapter, &get_feat_ctx);
2545 if (rc) {
2546 dev_err(&pdev->dev, "Validation of device parameters failed\n");
2547 goto err_device_destroy;
2548 }
2549
2550 rc = ena_enable_msix_and_set_admin_interrupts(adapter,
2551 adapter->num_queues);
2552 if (rc) {
2553 dev_err(&pdev->dev, "Enable MSI-X failed\n");
2554 goto err_device_destroy;
2555 }
2556 /* If the interface was up before the reset bring it up */
2557 if (dev_up) {
2558 rc = ena_up(adapter);
2559 if (rc) {
2560 dev_err(&pdev->dev, "Failed to create I/O queues\n");
2561 goto err_disable_msix;
2562 }
2563 }
2564
2565 mod_timer(&adapter->timer_service, round_jiffies(jiffies + HZ));
2566
2567 rtnl_unlock();
2568
2569 dev_err(&pdev->dev, "Device reset completed successfully\n");
2570
2571 return;
2572err_disable_msix:
2573 ena_free_mgmnt_irq(adapter);
2574 ena_disable_msix(adapter);
2575err_device_destroy:
2576 ena_com_admin_destroy(ena_dev);
2577err:
2578 rtnl_unlock();
2579
dee93ee4
NB		 2580 clear_bit(ENA_FLAG_DEVICE_RUNNING, &adapter->flags);
2581
1738cd3e
NB		 2582 dev_err(&pdev->dev,
2583 "Reset attempt failed. Can not reset the device\n");
2584}
2585
2586static void check_for_missing_tx_completions(struct ena_adapter *adapter)
2587{
2588 struct ena_tx_buffer *tx_buf;
2589 unsigned long last_jiffies;
2590 struct ena_ring *tx_ring;
2591 int i, j, budget;
2592 u32 missed_tx;
2593
2594 /* Make sure the driver doesn't turn the device in other process */
2595 smp_rmb();
2596
2597 if (!test_bit(ENA_FLAG_DEV_UP, &adapter->flags))
2598 return;
2599
d5796182
NB		 2600 if (test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags))
2601 return;
2602
1738cd3e
NB		 2603 budget = ENA_MONITORED_TX_QUEUES;
2604
2605 for (i = adapter->last_monitored_tx_qid; i < adapter->num_queues; i++) {
2606 tx_ring = &adapter->tx_ring[i];
2607
2608 for (j = 0; j < tx_ring->ring_size; j++) {
2609 tx_buf = &tx_ring->tx_buffer_info[j];
2610 last_jiffies = tx_buf->last_jiffies;
2611 if (unlikely(last_jiffies && time_is_before_jiffies(last_jiffies + TX_TIMEOUT))) {
2612 netif_notice(adapter, tx_err, adapter->netdev,
2613 "Found a Tx that wasn't completed on time, qid %d, index %d.\n",
2614 tx_ring->qid, j);
2615
2616 u64_stats_update_begin(&tx_ring->syncp);
2617 missed_tx = tx_ring->tx_stats.missing_tx_comp++;
2618 u64_stats_update_end(&tx_ring->syncp);
2619
2620 /* Clear last jiffies so the lost buffer won't
2621 * be counted twice.
2622 */
2623 tx_buf->last_jiffies = 0;
2624
2625 if (unlikely(missed_tx > MAX_NUM_OF_TIMEOUTED_PACKETS)) {
2626 netif_err(adapter, tx_err, adapter->netdev,
2627 "The number of lost tx completion is above the threshold (%d > %d). Reset the device\n",
2628 missed_tx, MAX_NUM_OF_TIMEOUTED_PACKETS);
2629 set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags);
2630 }
2631 }
2632 }
2633
2634 budget--;
2635 if (!budget)
2636 break;
2637 }
2638
2639 adapter->last_monitored_tx_qid = i % adapter->num_queues;
2640}
2641
2642/* Check for keep alive expiration */
2643static void check_for_missing_keep_alive(struct ena_adapter *adapter)
2644{
2645 unsigned long keep_alive_expired;
2646
2647 if (!adapter->wd_state)
2648 return;
2649
2650 keep_alive_expired = round_jiffies(adapter->last_keep_alive_jiffies
2651 + ENA_DEVICE_KALIVE_TIMEOUT);
2652 if (unlikely(time_is_before_jiffies(keep_alive_expired))) {
2653 netif_err(adapter, drv, adapter->netdev,
2654 "Keep alive watchdog timeout.\n");
2655 u64_stats_update_begin(&adapter->syncp);
2656 adapter->dev_stats.wd_expired++;
2657 u64_stats_update_end(&adapter->syncp);
2658 set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags);
2659 }
2660}
2661
2662static void check_for_admin_com_state(struct ena_adapter *adapter)
2663{
2664 if (unlikely(!ena_com_get_admin_running_state(adapter->ena_dev))) {
2665 netif_err(adapter, drv, adapter->netdev,
2666 "ENA admin queue is not in running state!\n");
2667 u64_stats_update_begin(&adapter->syncp);
2668 adapter->dev_stats.admin_q_pause++;
2669 u64_stats_update_end(&adapter->syncp);
2670 set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags);
2671 }
2672}
2673
2674static void ena_update_host_info(struct ena_admin_host_info *host_info,
2675 struct net_device *netdev)
2676{
2677 host_info->supported_network_features[0] =
2678 netdev->features & GENMASK_ULL(31, 0);
2679 host_info->supported_network_features[1] =
2680 (netdev->features & GENMASK_ULL(63, 32)) >> 32;
2681}
2682
2683static void ena_timer_service(unsigned long data)
2684{
2685 struct ena_adapter *adapter = (struct ena_adapter *)data;
2686 u8 *debug_area = adapter->ena_dev->host_attr.debug_area_virt_addr;
2687 struct ena_admin_host_info *host_info =
2688 adapter->ena_dev->host_attr.host_info;
2689
2690 check_for_missing_keep_alive(adapter);
2691
2692 check_for_admin_com_state(adapter);
2693
2694 check_for_missing_tx_completions(adapter);
2695
2696 if (debug_area)
2697 ena_dump_stats_to_buf(adapter, debug_area);
2698
2699 if (host_info)
2700 ena_update_host_info(host_info, adapter->netdev);
2701
d5796182 2702 if (unlikely(test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags))) {
1738cd3e
NB		 2703 netif_err(adapter, drv, adapter->netdev,
2704 "Trigger reset is on\n");
2705 ena_dump_stats_to_dmesg(adapter);
2706 queue_work(ena_wq, &adapter->reset_task);
2707 return;
2708 }
2709
2710 /* Reset the timer */
2711 mod_timer(&adapter->timer_service, jiffies + HZ);
2712}
2713
2714static int ena_calc_io_queue_num(struct pci_dev *pdev,
2715 struct ena_com_dev *ena_dev,
2716 struct ena_com_dev_get_features_ctx *get_feat_ctx)
2717{
2718 int io_sq_num, io_queue_num;
2719
2720 /* In case of LLQ use the llq number in the get feature cmd */
2721 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2722 io_sq_num = get_feat_ctx->max_queues.max_llq_num;
2723
2724 if (io_sq_num == 0) {
2725 dev_err(&pdev->dev,
2726 "Trying to use LLQ but llq_num is 0. Fall back into regular queues\n");
2727
2728 ena_dev->tx_mem_queue_type =
2729 ENA_ADMIN_PLACEMENT_POLICY_HOST;
2730 io_sq_num = get_feat_ctx->max_queues.max_sq_num;
2731 }
2732 } else {
2733 io_sq_num = get_feat_ctx->max_queues.max_sq_num;
2734 }
2735
c9b0b2cf 2736 io_queue_num = min_t(int, num_online_cpus(), ENA_MAX_NUM_IO_QUEUES);
1738cd3e
NB		 2737 io_queue_num = min_t(int, io_queue_num, io_sq_num);
2738 io_queue_num = min_t(int, io_queue_num,
2739 get_feat_ctx->max_queues.max_cq_num);
2740 /* 1 IRQ for for mgmnt and 1 IRQs for each IO direction */
2741 io_queue_num = min_t(int, io_queue_num, pci_msix_vec_count(pdev) - 1);
2742 if (unlikely(!io_queue_num)) {
2743 dev_err(&pdev->dev, "The device doesn't have io queues\n");
2744 return -EFAULT;
2745 }
2746
2747 return io_queue_num;
2748}
2749
184b49c8
RR		 2750static void ena_set_push_mode(struct pci_dev *pdev, struct ena_com_dev *ena_dev,
2751 struct ena_com_dev_get_features_ctx *get_feat_ctx)
1738cd3e
NB		 2752{
2753 bool has_mem_bar;
2754
2755 has_mem_bar = pci_select_bars(pdev, IORESOURCE_MEM) & BIT(ENA_MEM_BAR);
2756
2757 /* Enable push mode if device supports LLQ */
2758 if (has_mem_bar && (get_feat_ctx->max_queues.max_llq_num > 0))
2759 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_DEV;
2760 else
2761 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1738cd3e
NB		 2762}
2763
2764static void ena_set_dev_offloads(struct ena_com_dev_get_features_ctx *feat,
2765 struct net_device *netdev)
2766{
2767 netdev_features_t dev_features = 0;
2768
2769 /* Set offload features */
2770 if (feat->offload.tx &
2771 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)
2772 dev_features |= NETIF_F_IP_CSUM;
2773
2774 if (feat->offload.tx &
2775 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK)
2776 dev_features |= NETIF_F_IPV6_CSUM;
2777
2778 if (feat->offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK)
2779 dev_features |= NETIF_F_TSO;
2780
2781 if (feat->offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK)
2782 dev_features |= NETIF_F_TSO6;
2783
2784 if (feat->offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK)
2785 dev_features |= NETIF_F_TSO_ECN;
2786
2787 if (feat->offload.rx_supported &
2788 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK)
2789 dev_features |= NETIF_F_RXCSUM;
2790
2791 if (feat->offload.rx_supported &
2792 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK)
2793 dev_features |= NETIF_F_RXCSUM;
2794
2795 netdev->features =
2796 dev_features |
2797 NETIF_F_SG |
1738cd3e
NB		 2798 NETIF_F_RXHASH |
2799 NETIF_F_HIGHDMA;
2800
2801 netdev->hw_features |= netdev->features;
2802 netdev->vlan_features |= netdev->features;
2803}
2804
2805static void ena_set_conf_feat_params(struct ena_adapter *adapter,
2806 struct ena_com_dev_get_features_ctx *feat)
2807{
2808 struct net_device *netdev = adapter->netdev;
2809
2810 /* Copy mac address */
2811 if (!is_valid_ether_addr(feat->dev_attr.mac_addr)) {
2812 eth_hw_addr_random(netdev);
2813 ether_addr_copy(adapter->mac_addr, netdev->dev_addr);
2814 } else {
2815 ether_addr_copy(adapter->mac_addr, feat->dev_attr.mac_addr);
2816 ether_addr_copy(netdev->dev_addr, adapter->mac_addr);
2817 }
2818
2819 /* Set offload features */
2820 ena_set_dev_offloads(feat, netdev);
2821
2822 adapter->max_mtu = feat->dev_attr.max_mtu;
d894be57
JW		 2823 netdev->max_mtu = adapter->max_mtu;
2824 netdev->min_mtu = ENA_MIN_MTU;
1738cd3e
NB		 2825}
2826
2827static int ena_rss_init_default(struct ena_adapter *adapter)
2828{
2829 struct ena_com_dev *ena_dev = adapter->ena_dev;
2830 struct device *dev = &adapter->pdev->dev;
2831 int rc, i;
2832 u32 val;
2833
2834 rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
2835 if (unlikely(rc)) {
2836 dev_err(dev, "Cannot init indirect table\n");
2837 goto err_rss_init;
2838 }
2839
2840 for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
2841 val = ethtool_rxfh_indir_default(i, adapter->num_queues);
2842 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
2843 ENA_IO_RXQ_IDX(val));
2844 if (unlikely(rc && (rc != -EPERM))) {
2845 dev_err(dev, "Cannot fill indirect table\n");
2846 goto err_fill_indir;
2847 }
2848 }
2849
2850 rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
2851 ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
2852 if (unlikely(rc && (rc != -EPERM))) {
2853 dev_err(dev, "Cannot fill hash function\n");
2854 goto err_fill_indir;
2855 }
2856
2857 rc = ena_com_set_default_hash_ctrl(ena_dev);
2858 if (unlikely(rc && (rc != -EPERM))) {
2859 dev_err(dev, "Cannot fill hash control\n");
2860 goto err_fill_indir;
2861 }
2862
2863 return 0;
2864
2865err_fill_indir:
2866 ena_com_rss_destroy(ena_dev);
2867err_rss_init:
2868
2869 return rc;
2870}
2871
2872static void ena_release_bars(struct ena_com_dev *ena_dev, struct pci_dev *pdev)
2873{
2874 int release_bars;
2875
2876 release_bars = pci_select_bars(pdev, IORESOURCE_MEM) & ENA_BAR_MASK;
2877 pci_release_selected_regions(pdev, release_bars);
2878}
2879
2880static int ena_calc_queue_size(struct pci_dev *pdev,
2881 struct ena_com_dev *ena_dev,
2882 u16 *max_tx_sgl_size,
2883 u16 *max_rx_sgl_size,
2884 struct ena_com_dev_get_features_ctx *get_feat_ctx)
2885{
2886 u32 queue_size = ENA_DEFAULT_RING_SIZE;
2887
2888 queue_size = min_t(u32, queue_size,
2889 get_feat_ctx->max_queues.max_cq_depth);
2890 queue_size = min_t(u32, queue_size,
2891 get_feat_ctx->max_queues.max_sq_depth);
2892
2893 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
2894 queue_size = min_t(u32, queue_size,
2895 get_feat_ctx->max_queues.max_llq_depth);
2896
2897 queue_size = rounddown_pow_of_two(queue_size);
2898
2899 if (unlikely(!queue_size)) {
2900 dev_err(&pdev->dev, "Invalid queue size\n");
2901 return -EFAULT;
2902 }
2903
2904 *max_tx_sgl_size = min_t(u16, ENA_PKT_MAX_BUFS,
2905 get_feat_ctx->max_queues.max_packet_tx_descs);
2906 *max_rx_sgl_size = min_t(u16, ENA_PKT_MAX_BUFS,
2907 get_feat_ctx->max_queues.max_packet_rx_descs);
2908
2909 return queue_size;
2910}
2911
2912/* ena_probe - Device Initialization Routine
2913 * @pdev: PCI device information struct
2914 * @ent: entry in ena_pci_tbl
2915 *
2916 * Returns 0 on success, negative on failure
2917 *
2918 * ena_probe initializes an adapter identified by a pci_dev structure.
2919 * The OS initialization, configuring of the adapter private structure,
2920 * and a hardware reset occur.
2921 */
2922static int ena_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2923{
2924 struct ena_com_dev_get_features_ctx get_feat_ctx;
2925 static int version_printed;
2926 struct net_device *netdev;
2927 struct ena_adapter *adapter;
2928 struct ena_com_dev *ena_dev = NULL;
2929 static int adapters_found;
2930 int io_queue_num, bars, rc;
2931 int queue_size;
2932 u16 tx_sgl_size = 0;
2933 u16 rx_sgl_size = 0;
2934 bool wd_state;
2935
2936 dev_dbg(&pdev->dev, "%s\n", __func__);
2937
2938 if (version_printed++ == 0)
2939 dev_info(&pdev->dev, "%s", version);
2940
2941 rc = pci_enable_device_mem(pdev);
2942 if (rc) {
2943 dev_err(&pdev->dev, "pci_enable_device_mem() failed!\n");
2944 return rc;
2945 }
2946
2947 pci_set_master(pdev);
2948
2949 ena_dev = vzalloc(sizeof(*ena_dev));
2950 if (!ena_dev) {
2951 rc = -ENOMEM;
2952 goto err_disable_device;
2953 }
2954
2955 bars = pci_select_bars(pdev, IORESOURCE_MEM) & ENA_BAR_MASK;
2956 rc = pci_request_selected_regions(pdev, bars, DRV_MODULE_NAME);
2957 if (rc) {
2958 dev_err(&pdev->dev, "pci_request_selected_regions failed %d\n",
2959 rc);
2960 goto err_free_ena_dev;
2961 }
2962
2963 ena_dev->reg_bar = ioremap(pci_resource_start(pdev, ENA_REG_BAR),
2964 pci_resource_len(pdev, ENA_REG_BAR));
2965 if (!ena_dev->reg_bar) {
2966 dev_err(&pdev->dev, "failed to remap regs bar\n");
2967 rc = -EFAULT;
2968 goto err_free_region;
2969 }
2970
2971 ena_dev->dmadev = &pdev->dev;
2972
2973 rc = ena_device_init(ena_dev, pdev, &get_feat_ctx, &wd_state);
2974 if (rc) {
2975 dev_err(&pdev->dev, "ena device init failed\n");
2976 if (rc == -ETIME)
2977 rc = -EPROBE_DEFER;
2978 goto err_free_region;
2979 }
2980
184b49c8 2981 ena_set_push_mode(pdev, ena_dev, &get_feat_ctx);
1738cd3e
NB		 2982
2983 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2984 ena_dev->mem_bar = ioremap_wc(pci_resource_start(pdev, ENA_MEM_BAR),
2985 pci_resource_len(pdev, ENA_MEM_BAR));
2986 if (!ena_dev->mem_bar) {
2987 rc = -EFAULT;
2988 goto err_device_destroy;
2989 }
2990 }
2991
2992 /* initial Tx interrupt delay, Assumes 1 usec granularity.
2993 * Updated during device initialization with the real granularity
2994 */
2995 ena_dev->intr_moder_tx_interval = ENA_INTR_INITIAL_TX_INTERVAL_USECS;
2996 io_queue_num = ena_calc_io_queue_num(pdev, ena_dev, &get_feat_ctx);
2997 queue_size = ena_calc_queue_size(pdev, ena_dev, &tx_sgl_size,
2998 &rx_sgl_size, &get_feat_ctx);
2999 if ((queue_size <= 0) || (io_queue_num <= 0)) {
3000 rc = -EFAULT;
3001 goto err_device_destroy;
3002 }
3003
3004 dev_info(&pdev->dev, "creating %d io queues. queue size: %d\n",
3005 io_queue_num, queue_size);
3006
3007 /* dev zeroed in init_etherdev */
3008 netdev = alloc_etherdev_mq(sizeof(struct ena_adapter), io_queue_num);
3009 if (!netdev) {
3010 dev_err(&pdev->dev, "alloc_etherdev_mq failed\n");
3011 rc = -ENOMEM;
3012 goto err_device_destroy;
3013 }
3014
3015 SET_NETDEV_DEV(netdev, &pdev->dev);
3016
3017 adapter = netdev_priv(netdev);
3018 pci_set_drvdata(pdev, adapter);
3019
3020 adapter->ena_dev = ena_dev;
3021 adapter->netdev = netdev;
3022 adapter->pdev = pdev;
3023
3024 ena_set_conf_feat_params(adapter, &get_feat_ctx);
3025
3026 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
3027
3028 adapter->tx_ring_size = queue_size;
3029 adapter->rx_ring_size = queue_size;
3030
3031 adapter->max_tx_sgl_size = tx_sgl_size;
3032 adapter->max_rx_sgl_size = rx_sgl_size;
3033
3034 adapter->num_queues = io_queue_num;
3035 adapter->last_monitored_tx_qid = 0;
3036
3037 adapter->rx_copybreak = ENA_DEFAULT_RX_COPYBREAK;
3038 adapter->wd_state = wd_state;
3039
3040 snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d", adapters_found);
3041
3042 rc = ena_com_init_interrupt_moderation(adapter->ena_dev);
3043 if (rc) {
3044 dev_err(&pdev->dev,
3045 "Failed to query interrupt moderation feature\n");
3046 goto err_netdev_destroy;
3047 }
3048 ena_init_io_rings(adapter);
3049
3050 netdev->netdev_ops = &ena_netdev_ops;
3051 netdev->watchdog_timeo = TX_TIMEOUT;
3052 ena_set_ethtool_ops(netdev);
3053
3054 netdev->priv_flags |= IFF_UNICAST_FLT;
3055
3056 u64_stats_init(&adapter->syncp);
3057
3058 rc = ena_enable_msix_and_set_admin_interrupts(adapter, io_queue_num);
3059 if (rc) {
3060 dev_err(&pdev->dev,
3061 "Failed to enable and set the admin interrupts\n");
3062 goto err_worker_destroy;
3063 }
3064 rc = ena_rss_init_default(adapter);
3065 if (rc && (rc != -EPERM)) {
3066 dev_err(&pdev->dev, "Cannot init RSS rc: %d\n", rc);
3067 goto err_free_msix;
3068 }
3069
3070 ena_config_debug_area(adapter);
3071
3072 memcpy(adapter->netdev->perm_addr, adapter->mac_addr, netdev->addr_len);
3073
3074 netif_carrier_off(netdev);
3075
3076 rc = register_netdev(netdev);
3077 if (rc) {
3078 dev_err(&pdev->dev, "Cannot register net device\n");
3079 goto err_rss;
3080 }
3081
3082 INIT_WORK(&adapter->suspend_io_task, ena_device_io_suspend);
3083 INIT_WORK(&adapter->resume_io_task, ena_device_io_resume);
3084 INIT_WORK(&adapter->reset_task, ena_fw_reset_device);
3085
3086 adapter->last_keep_alive_jiffies = jiffies;
3087
f850b4a7
WY		 3088 setup_timer(&adapter->timer_service, ena_timer_service,
3089 (unsigned long)adapter);
3090 mod_timer(&adapter->timer_service, round_jiffies(jiffies + HZ));
1738cd3e
NB		 3091
3092 dev_info(&pdev->dev, "%s found at mem %lx, mac addr %pM Queues %d\n",
3093 DEVICE_NAME, (long)pci_resource_start(pdev, 0),
3094 netdev->dev_addr, io_queue_num);
3095
3096 set_bit(ENA_FLAG_DEVICE_RUNNING, &adapter->flags);
3097
3098 adapters_found++;
3099
3100 return 0;
3101
3102err_rss:
3103 ena_com_delete_debug_area(ena_dev);
3104 ena_com_rss_destroy(ena_dev);
3105err_free_msix:
3106 ena_com_dev_reset(ena_dev);
3107 ena_free_mgmnt_irq(adapter);
3108 ena_disable_msix(adapter);
3109err_worker_destroy:
3110 ena_com_destroy_interrupt_moderation(ena_dev);
3111 del_timer(&adapter->timer_service);
3112 cancel_work_sync(&adapter->suspend_io_task);
3113 cancel_work_sync(&adapter->resume_io_task);
3114err_netdev_destroy:
3115 free_netdev(netdev);
3116err_device_destroy:
3117 ena_com_delete_host_info(ena_dev);
3118 ena_com_admin_destroy(ena_dev);
3119err_free_region:
3120 ena_release_bars(ena_dev, pdev);
3121err_free_ena_dev:
1738cd3e
NB		 3122 vfree(ena_dev);
3123err_disable_device:
3124 pci_disable_device(pdev);
3125 return rc;
3126}
3127
3128/*****************************************************************************/
3129static int ena_sriov_configure(struct pci_dev *dev, int numvfs)
3130{
3131 int rc;
3132
3133 if (numvfs > 0) {
3134 rc = pci_enable_sriov(dev, numvfs);
3135 if (rc != 0) {
3136 dev_err(&dev->dev,
3137 "pci_enable_sriov failed to enable: %d vfs with the error: %d\n",
3138 numvfs, rc);
3139 return rc;
3140 }
3141
3142 return numvfs;
3143 }
3144
3145 if (numvfs == 0) {
3146 pci_disable_sriov(dev);
3147 return 0;
3148 }
3149
3150 return -EINVAL;
3151}
3152
3153/*****************************************************************************/
3154/*****************************************************************************/
3155
3156/* ena_remove - Device Removal Routine
3157 * @pdev: PCI device information struct
3158 *
3159 * ena_remove is called by the PCI subsystem to alert the driver
3160 * that it should release a PCI device.
3161 */
3162static void ena_remove(struct pci_dev *pdev)
3163{
3164 struct ena_adapter *adapter = pci_get_drvdata(pdev);
3165 struct ena_com_dev *ena_dev;
3166 struct net_device *netdev;
3167
3168 if (!adapter)
3169 /* This device didn't load properly and it's resources
3170 * already released, nothing to do
3171 */
3172 return;
3173
3174 ena_dev = adapter->ena_dev;
3175 netdev = adapter->netdev;
3176
3177#ifdef CONFIG_RFS_ACCEL
3178 if ((adapter->msix_vecs >= 1) && (netdev->rx_cpu_rmap)) {
3179 free_irq_cpu_rmap(netdev->rx_cpu_rmap);
3180 netdev->rx_cpu_rmap = NULL;
3181 }
3182#endif /* CONFIG_RFS_ACCEL */
3183
3184 unregister_netdev(netdev);
3185 del_timer_sync(&adapter->timer_service);
3186
3187 cancel_work_sync(&adapter->reset_task);
3188
3189 cancel_work_sync(&adapter->suspend_io_task);
3190
3191 cancel_work_sync(&adapter->resume_io_task);
3192
dee93ee4
NB		 3193 /* Reset the device only if the device is running. */
3194 if (test_bit(ENA_FLAG_DEVICE_RUNNING, &adapter->flags))
3195 ena_com_dev_reset(ena_dev);
1738cd3e
NB		 3196
3197 ena_free_mgmnt_irq(adapter);
3198
3199 ena_disable_msix(adapter);
3200
3201 free_netdev(netdev);
3202
3203 ena_com_mmio_reg_read_request_destroy(ena_dev);
3204
3205 ena_com_abort_admin_commands(ena_dev);
3206
3207 ena_com_wait_for_abort_completion(ena_dev);
3208
3209 ena_com_admin_destroy(ena_dev);
3210
3211 ena_com_rss_destroy(ena_dev);
3212
3213 ena_com_delete_debug_area(ena_dev);
3214
3215 ena_com_delete_host_info(ena_dev);
3216
3217 ena_release_bars(ena_dev, pdev);
3218
1738cd3e
NB		 3219 pci_disable_device(pdev);
3220
3221 ena_com_destroy_interrupt_moderation(ena_dev);
3222
3223 vfree(ena_dev);
3224}
3225
3226static struct pci_driver ena_pci_driver = {
3227 .name = DRV_MODULE_NAME,
3228 .id_table = ena_pci_tbl,
3229 .probe = ena_probe,
3230 .remove = ena_remove,
3231 .sriov_configure = ena_sriov_configure,
3232};
3233
3234static int __init ena_init(void)
3235{
3236 pr_info("%s", version);
3237
3238 ena_wq = create_singlethread_workqueue(DRV_MODULE_NAME);
3239 if (!ena_wq) {
3240 pr_err("Failed to create workqueue\n");
3241 return -ENOMEM;
3242 }
3243
3244 return pci_register_driver(&ena_pci_driver);
3245}
3246
3247static void __exit ena_cleanup(void)
3248{
3249 pci_unregister_driver(&ena_pci_driver);
3250
3251 if (ena_wq) {
3252 destroy_workqueue(ena_wq);
3253 ena_wq = NULL;
3254 }
3255}
3256
3257/******************************************************************************
3258 ******************************** AENQ Handlers *******************************
3259 *****************************************************************************/
3260/* ena_update_on_link_change:
3261 * Notify the network interface about the change in link status
3262 */
3263static void ena_update_on_link_change(void *adapter_data,
3264 struct ena_admin_aenq_entry *aenq_e)
3265{
3266 struct ena_adapter *adapter = (struct ena_adapter *)adapter_data;
3267 struct ena_admin_aenq_link_change_desc *aenq_desc =
3268 (struct ena_admin_aenq_link_change_desc *)aenq_e;
3269 int status = aenq_desc->flags &
3270 ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK;
3271
3272 if (status) {
3273 netdev_dbg(adapter->netdev, "%s\n", __func__);
3274 set_bit(ENA_FLAG_LINK_UP, &adapter->flags);
3275 netif_carrier_on(adapter->netdev);
3276 } else {
3277 clear_bit(ENA_FLAG_LINK_UP, &adapter->flags);
3278 netif_carrier_off(adapter->netdev);
3279 }
3280}
3281
3282static void ena_keep_alive_wd(void *adapter_data,
3283 struct ena_admin_aenq_entry *aenq_e)
3284{
3285 struct ena_adapter *adapter = (struct ena_adapter *)adapter_data;
3286
3287 adapter->last_keep_alive_jiffies = jiffies;
3288}
3289
3290static void ena_notification(void *adapter_data,
3291 struct ena_admin_aenq_entry *aenq_e)
3292{
3293 struct ena_adapter *adapter = (struct ena_adapter *)adapter_data;
3294
3295 WARN(aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION,
3296 "Invalid group(%x) expected %x\n",
3297 aenq_e->aenq_common_desc.group,
3298 ENA_ADMIN_NOTIFICATION);
3299
3300 switch (aenq_e->aenq_common_desc.syndrom) {
3301 case ENA_ADMIN_SUSPEND:
3302 /* Suspend just the IO queues.
3303 * We deliberately don't suspend admin so the timer and
3304 * the keep_alive events should remain.
3305 */
3306 queue_work(ena_wq, &adapter->suspend_io_task);
3307 break;
3308 case ENA_ADMIN_RESUME:
3309 queue_work(ena_wq, &adapter->resume_io_task);
3310 break;
3311 default:
3312 netif_err(adapter, drv, adapter->netdev,
3313 "Invalid aenq notification link state %d\n",
3314 aenq_e->aenq_common_desc.syndrom);
3315 }
3316}
3317
3318/* This handler will called for unknown event group or unimplemented handlers*/
3319static void unimplemented_aenq_handler(void *data,
3320 struct ena_admin_aenq_entry *aenq_e)
3321{
3322 struct ena_adapter *adapter = (struct ena_adapter *)data;
3323
3324 netif_err(adapter, drv, adapter->netdev,
3325 "Unknown event was received or event with unimplemented handler\n");
3326}
3327
3328static struct ena_aenq_handlers aenq_handlers = {
3329 .handlers = {
3330 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
3331 [ENA_ADMIN_NOTIFICATION] = ena_notification,
3332 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive_wd,
3333 },
3334 .unimplemented_handler = unimplemented_aenq_handler
3335};
3336
3337module_init(ena_init);
3338module_exit(ena_cleanup);
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