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net: ena: update ena driver to version 1.1.7
[mirror_ubuntu-zesty-kernel.git] / drivers / net / ethernet / amazon / ena / ena_netdev.h
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1738cd3e
NB
1/*
2 * Copyright 2015 Amazon.com, Inc. or its affiliates.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef ENA_H
34#define ENA_H
35
36#include <linux/bitops.h>
37#include <linux/etherdevice.h>
38#include <linux/inetdevice.h>
39#include <linux/interrupt.h>
40#include <linux/netdevice.h>
41#include <linux/skbuff.h>
42
43#include "ena_com.h"
44#include "ena_eth_com.h"
45
46#define DRV_MODULE_VER_MAJOR 1
6a2db9f9 47#define DRV_MODULE_VER_MINOR 1
23de50b1 48#define DRV_MODULE_VER_SUBMINOR 7
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NB
49
50#define DRV_MODULE_NAME "ena"
51#ifndef DRV_MODULE_VERSION
52#define DRV_MODULE_VERSION \
53 __stringify(DRV_MODULE_VER_MAJOR) "." \
54 __stringify(DRV_MODULE_VER_MINOR) "." \
55 __stringify(DRV_MODULE_VER_SUBMINOR)
56#endif
57
58#define DEVICE_NAME "Elastic Network Adapter (ENA)"
59
60/* 1 for AENQ + ADMIN */
61#define ENA_MAX_MSIX_VEC(io_queues) (1 + (io_queues))
62
63#define ENA_REG_BAR 0
64#define ENA_MEM_BAR 2
65#define ENA_BAR_MASK (BIT(ENA_REG_BAR) | BIT(ENA_MEM_BAR))
66
67#define ENA_DEFAULT_RING_SIZE (1024)
68
69#define ENA_TX_WAKEUP_THRESH (MAX_SKB_FRAGS + 2)
70#define ENA_DEFAULT_RX_COPYBREAK (128 - NET_IP_ALIGN)
71
72/* limit the buffer size to 600 bytes to handle MTU changes from very
73 * small to very large, in which case the number of buffers per packet
74 * could exceed ENA_PKT_MAX_BUFS
75 */
76#define ENA_DEFAULT_MIN_RX_BUFF_ALLOC_SIZE 600
77
78#define ENA_MIN_MTU 128
79
80#define ENA_NAME_MAX_LEN 20
81#define ENA_IRQNAME_SIZE 40
82
83#define ENA_PKT_MAX_BUFS 19
84
85#define ENA_RX_RSS_TABLE_LOG_SIZE 7
86#define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
87
88#define ENA_HASH_KEY_SIZE 40
89
90/* The number of tx packet completions that will be handled each NAPI poll
91 * cycle is ring_size / ENA_TX_POLL_BUDGET_DIVIDER.
92 */
93#define ENA_TX_POLL_BUDGET_DIVIDER 4
94
95/* Refill Rx queue when number of available descriptors is below
96 * QUEUE_SIZE / ENA_RX_REFILL_THRESH_DIVIDER
97 */
98#define ENA_RX_REFILL_THRESH_DIVIDER 8
99
100/* Number of queues to check for missing queues per timer service */
101#define ENA_MONITORED_TX_QUEUES 4
102/* Max timeout packets before device reset */
e748e282 103#define MAX_NUM_OF_TIMEOUTED_PACKETS 128
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NB
104
105#define ENA_TX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1))
106
107#define ENA_RX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1))
108#define ENA_RX_RING_IDX_ADD(idx, n, ring_size) \
109 (((idx) + (n)) & ((ring_size) - 1))
110
111#define ENA_IO_TXQ_IDX(q) (2 * (q))
112#define ENA_IO_RXQ_IDX(q) (2 * (q) + 1)
113
114#define ENA_MGMNT_IRQ_IDX 0
115#define ENA_IO_IRQ_FIRST_IDX 1
116#define ENA_IO_IRQ_IDX(q) (ENA_IO_IRQ_FIRST_IDX + (q))
117
118/* ENA device should send keep alive msg every 1 sec.
e748e282 119 * We wait for 6 sec just to be on the safe side.
1738cd3e 120 */
e748e282 121#define ENA_DEVICE_KALIVE_TIMEOUT (6 * HZ)
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NB
122
123#define ENA_MMIO_DISABLE_REG_READ BIT(0)
124
125struct ena_irq {
126 irq_handler_t handler;
127 void *data;
128 int cpu;
129 u32 vector;
130 cpumask_t affinity_hint_mask;
131 char name[ENA_IRQNAME_SIZE];
132};
133
134struct ena_napi {
135 struct napi_struct napi ____cacheline_aligned;
136 struct ena_ring *tx_ring;
137 struct ena_ring *rx_ring;
138 u32 qid;
139};
140
141struct ena_tx_buffer {
142 struct sk_buff *skb;
143 /* num of ena desc for this specific skb
144 * (includes data desc and metadata desc)
145 */
146 u32 tx_descs;
147 /* num of buffers used by this skb */
148 u32 num_of_bufs;
8422614c
NB
149
150 /* Used for detect missing tx packets to limit the number of prints */
151 u32 print_once;
152 /* Save the last jiffies to detect missing tx packets
153 *
154 * sets to non zero value on ena_start_xmit and set to zero on
155 * napi and timer_Service_routine.
156 *
157 * while this value is not protected by lock,
158 * a given packet is not expected to be handled by ena_start_xmit
159 * and by napi/timer_service at the same time.
160 */
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NB
161 unsigned long last_jiffies;
162 struct ena_com_buf bufs[ENA_PKT_MAX_BUFS];
163} ____cacheline_aligned;
164
165struct ena_rx_buffer {
166 struct sk_buff *skb;
167 struct page *page;
168 u32 page_offset;
169 struct ena_com_buf ena_buf;
170} ____cacheline_aligned;
171
172struct ena_stats_tx {
173 u64 cnt;
174 u64 bytes;
175 u64 queue_stop;
176 u64 prepare_ctx_err;
177 u64 queue_wakeup;
178 u64 dma_mapping_err;
179 u64 linearize;
180 u64 linearize_failed;
181 u64 napi_comp;
182 u64 tx_poll;
183 u64 doorbells;
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NB
184 u64 bad_req_id;
185};
186
187struct ena_stats_rx {
188 u64 cnt;
189 u64 bytes;
190 u64 refil_partial;
191 u64 bad_csum;
192 u64 page_alloc_fail;
193 u64 skb_alloc_fail;
194 u64 dma_mapping_err;
195 u64 bad_desc_num;
196 u64 rx_copybreak_pkt;
d09b6090 197 u64 empty_rx_ring;
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NB
198};
199
200struct ena_ring {
201 /* Holds the empty requests for TX out of order completions */
202 u16 *free_tx_ids;
203 union {
204 struct ena_tx_buffer *tx_buffer_info;
205 struct ena_rx_buffer *rx_buffer_info;
206 };
207
208 /* cache ptr to avoid using the adapter */
209 struct device *dev;
210 struct pci_dev *pdev;
211 struct napi_struct *napi;
212 struct net_device *netdev;
213 struct ena_com_dev *ena_dev;
214 struct ena_adapter *adapter;
215 struct ena_com_io_cq *ena_com_io_cq;
216 struct ena_com_io_sq *ena_com_io_sq;
217
218 u16 next_to_use;
219 u16 next_to_clean;
220 u16 rx_copybreak;
221 u16 qid;
222 u16 mtu;
223 u16 sgl_size;
224
225 /* The maximum header length the device can handle */
226 u8 tx_max_header_size;
227
228 /* cpu for TPH */
229 int cpu;
230 /* number of tx/rx_buffer_info's entries */
231 int ring_size;
232
233 enum ena_admin_placement_policy_type tx_mem_queue_type;
234
235 struct ena_com_rx_buf_info ena_bufs[ENA_PKT_MAX_BUFS];
236 u32 smoothed_interval;
237 u32 per_napi_packets;
238 u32 per_napi_bytes;
239 enum ena_intr_moder_level moder_tbl_idx;
240 struct u64_stats_sync syncp;
241 union {
242 struct ena_stats_tx tx_stats;
243 struct ena_stats_rx rx_stats;
244 };
d09b6090 245 int empty_rx_queue;
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NB
246} ____cacheline_aligned;
247
248struct ena_stats_dev {
249 u64 tx_timeout;
250 u64 io_suspend;
251 u64 io_resume;
252 u64 wd_expired;
253 u64 interface_up;
254 u64 interface_down;
255 u64 admin_q_pause;
e487b3b0 256 u64 rx_drops;
1738cd3e
NB
257};
258
259enum ena_flags_t {
260 ENA_FLAG_DEVICE_RUNNING,
261 ENA_FLAG_DEV_UP,
262 ENA_FLAG_LINK_UP,
1738cd3e
NB
263 ENA_FLAG_TRIGGER_RESET
264};
265
266/* adapter specific private data structure */
267struct ena_adapter {
268 struct ena_com_dev *ena_dev;
269 /* OS defined structs */
270 struct net_device *netdev;
271 struct pci_dev *pdev;
272
273 /* rx packets that shorter that this len will be copied to the skb
274 * header
275 */
276 u32 rx_copybreak;
277 u32 max_mtu;
278
279 int num_queues;
280
1738cd3e
NB
281 int msix_vecs;
282
283 u32 tx_usecs, rx_usecs; /* interrupt moderation */
284 u32 tx_frames, rx_frames; /* interrupt moderation */
285
286 u32 tx_ring_size;
287 u32 rx_ring_size;
288
289 u32 msg_enable;
290
291 u16 max_tx_sgl_size;
292 u16 max_rx_sgl_size;
293
294 u8 mac_addr[ETH_ALEN];
295
296 char name[ENA_NAME_MAX_LEN];
297
298 unsigned long flags;
299 /* TX */
300 struct ena_ring tx_ring[ENA_MAX_NUM_IO_QUEUES]
301 ____cacheline_aligned_in_smp;
302
303 /* RX */
304 struct ena_ring rx_ring[ENA_MAX_NUM_IO_QUEUES]
305 ____cacheline_aligned_in_smp;
306
307 struct ena_napi ena_napi[ENA_MAX_NUM_IO_QUEUES];
308
309 struct ena_irq irq_tbl[ENA_MAX_MSIX_VEC(ENA_MAX_NUM_IO_QUEUES)];
310
311 /* timer service */
312 struct work_struct reset_task;
313 struct work_struct suspend_io_task;
314 struct work_struct resume_io_task;
315 struct timer_list timer_service;
316
317 bool wd_state;
318 unsigned long last_keep_alive_jiffies;
319
320 struct u64_stats_sync syncp;
321 struct ena_stats_dev dev_stats;
322
323 /* last queue index that was checked for uncompleted tx packets */
324 u32 last_monitored_tx_qid;
325};
326
327void ena_set_ethtool_ops(struct net_device *netdev);
328
329void ena_dump_stats_to_dmesg(struct ena_adapter *adapter);
330
331void ena_dump_stats_to_buf(struct ena_adapter *adapter, u8 *buf);
332
333int ena_get_sset_count(struct net_device *netdev, int sset);
334
335#endif /* !(ENA_H) */