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nvme: Display raw APST configuration via DYNAMIC_DEBUG
[mirror_ubuntu-zesty-kernel.git] / drivers / nvme / host / core.c
CommitLineData
21d34711
CH		 1/*
2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 */
14
15#include <linux/blkdev.h>
16#include <linux/blk-mq.h>
5fd4ce1b 17#include <linux/delay.h>
21d34711 18#include <linux/errno.h>
1673f1f0 19#include <linux/hdreg.h>
21d34711 20#include <linux/kernel.h>
5bae7f73
CH		 21#include <linux/module.h>
22#include <linux/list_sort.h>
21d34711
CH		 23#include <linux/slab.h>
24#include <linux/types.h>
1673f1f0
CH		 25#include <linux/pr.h>
26#include <linux/ptrace.h>
27#include <linux/nvme_ioctl.h>
28#include <linux/t10-pi.h>
441d14c0 29#include <linux/pm_qos.h>
1673f1f0
CH		 30#include <scsi/sg.h>
31#include <asm/unaligned.h>
21d34711
CH		 32
33#include "nvme.h"
038bd4cb 34#include "fabrics.h"
21d34711 35
f3ca80fc
CH		 36#define NVME_MINORS (1U << MINORBITS)
37
ba0ba7d3
ML		 38unsigned char admin_timeout = 60;
39module_param(admin_timeout, byte, 0644);
40MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
576d55d6 41EXPORT_SYMBOL_GPL(admin_timeout);
ba0ba7d3
ML		 42
43unsigned char nvme_io_timeout = 30;
44module_param_named(io_timeout, nvme_io_timeout, byte, 0644);
45MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
576d55d6 46EXPORT_SYMBOL_GPL(nvme_io_timeout);
ba0ba7d3
ML		 47
48unsigned char shutdown_timeout = 5;
49module_param(shutdown_timeout, byte, 0644);
50MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
51
f80ec966
KB		 52unsigned int nvme_max_retries = 5;
53module_param_named(max_retries, nvme_max_retries, uint, 0644);
54MODULE_PARM_DESC(max_retries, "max number of retries a command may have");
55EXPORT_SYMBOL_GPL(nvme_max_retries);
5bae7f73 56
f3ca80fc
CH		 57static int nvme_char_major;
58module_param(nvme_char_major, int, 0);
59
441d14c0
AL		 60static unsigned long default_ps_max_latency_us = 25000;
61module_param(default_ps_max_latency_us, ulong, 0644);
62MODULE_PARM_DESC(default_ps_max_latency_us,
63 "max power saving latency for new devices; use PM QOS to change per device");
64
f3ca80fc 65static LIST_HEAD(nvme_ctrl_list);
9f2482b9 66static DEFINE_SPINLOCK(dev_list_lock);
1673f1f0 67
f3ca80fc
CH		 68static struct class *nvme_class;
69
c55a2fd4
ML		 70void nvme_cancel_request(struct request *req, void *data, bool reserved)
71{
72 int status;
73
74 if (!blk_mq_request_started(req))
75 return;
76
77 dev_dbg_ratelimited(((struct nvme_ctrl *) data)->device,
78 "Cancelling I/O %d", req->tag);
79
80 status = NVME_SC_ABORT_REQ;
81 if (blk_queue_dying(req->q))
82 status |= NVME_SC_DNR;
83 blk_mq_complete_request(req, status);
84}
85EXPORT_SYMBOL_GPL(nvme_cancel_request);
86
bb8d261e
CH		 87bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl,
88 enum nvme_ctrl_state new_state)
89{
f6b6a28e 90 enum nvme_ctrl_state old_state;
bb8d261e
CH		 91 bool changed = false;
92
93 spin_lock_irq(&ctrl->lock);
f6b6a28e
GKB		 94
95 old_state = ctrl->state;
bb8d261e
CH		 96 switch (new_state) {
97 case NVME_CTRL_LIVE:
98 switch (old_state) {
7d2e8008 99 case NVME_CTRL_NEW:
bb8d261e 100 case NVME_CTRL_RESETTING:
def61eca 101 case NVME_CTRL_RECONNECTING:
bb8d261e
CH		 102 changed = true;
103 /* FALLTHRU */
104 default:
105 break;
106 }
107 break;
108 case NVME_CTRL_RESETTING:
109 switch (old_state) {
110 case NVME_CTRL_NEW:
def61eca
CH		 111 case NVME_CTRL_LIVE:
112 case NVME_CTRL_RECONNECTING:
113 changed = true;
114 /* FALLTHRU */
115 default:
116 break;
117 }
118 break;
119 case NVME_CTRL_RECONNECTING:
120 switch (old_state) {
bb8d261e
CH		 121 case NVME_CTRL_LIVE:
122 changed = true;
123 /* FALLTHRU */
124 default:
125 break;
126 }
127 break;
128 case NVME_CTRL_DELETING:
129 switch (old_state) {
130 case NVME_CTRL_LIVE:
131 case NVME_CTRL_RESETTING:
def61eca 132 case NVME_CTRL_RECONNECTING:
bb8d261e
CH		 133 changed = true;
134 /* FALLTHRU */
135 default:
136 break;
137 }
138 break;
0ff9d4e1
KB		 139 case NVME_CTRL_DEAD:
140 switch (old_state) {
141 case NVME_CTRL_DELETING:
142 changed = true;
143 /* FALLTHRU */
144 default:
145 break;
146 }
147 break;
bb8d261e
CH		 148 default:
149 break;
150 }
bb8d261e
CH		 151
152 if (changed)
153 ctrl->state = new_state;
154
f6b6a28e
GKB		 155 spin_unlock_irq(&ctrl->lock);
156
bb8d261e
CH		 157 return changed;
158}
159EXPORT_SYMBOL_GPL(nvme_change_ctrl_state);
160
1673f1f0
CH		 161static void nvme_free_ns(struct kref *kref)
162{
163 struct nvme_ns *ns = container_of(kref, struct nvme_ns, kref);
164
b0b4e09c
MB		 165 if (ns->ndev)
166 nvme_nvm_unregister(ns);
1673f1f0 167
b0b4e09c
MB		 168 if (ns->disk) {
169 spin_lock(&dev_list_lock);
170 ns->disk->private_data = NULL;
171 spin_unlock(&dev_list_lock);
172 }
1673f1f0 173
1673f1f0 174 put_disk(ns->disk);
075790eb
KB		 175 ida_simple_remove(&ns->ctrl->ns_ida, ns->instance);
176 nvme_put_ctrl(ns->ctrl);
1673f1f0
CH		 177 kfree(ns);
178}
179
5bae7f73 180static void nvme_put_ns(struct nvme_ns *ns)
1673f1f0
CH		 181{
182 kref_put(&ns->kref, nvme_free_ns);
183}
184
185static struct nvme_ns *nvme_get_ns_from_disk(struct gendisk *disk)
186{
187 struct nvme_ns *ns;
188
189 spin_lock(&dev_list_lock);
190 ns = disk->private_data;
e439bb12
SG		 191 if (ns) {
192 if (!kref_get_unless_zero(&ns->kref))
193 goto fail;
194 if (!try_module_get(ns->ctrl->ops->module))
195 goto fail_put_ns;
196 }
1673f1f0
CH		 197 spin_unlock(&dev_list_lock);
198
199 return ns;
e439bb12
SG		 200
201fail_put_ns:
202 kref_put(&ns->kref, nvme_free_ns);
203fail:
204 spin_unlock(&dev_list_lock);
205 return NULL;
1673f1f0
CH		 206}
207
7688faa6
CH		 208void nvme_requeue_req(struct request *req)
209{
a6eaa884 210 blk_mq_requeue_request(req, !blk_mq_queue_stopped(req->q));
7688faa6 211}
576d55d6 212EXPORT_SYMBOL_GPL(nvme_requeue_req);
7688faa6 213
4160982e 214struct request *nvme_alloc_request(struct request_queue *q,
eb71f435 215 struct nvme_command *cmd, unsigned int flags, int qid)
21d34711 216{
21d34711 217 struct request *req;
21d34711 218
eb71f435
CH		 219 if (qid == NVME_QID_ANY) {
220 req = blk_mq_alloc_request(q, nvme_is_write(cmd), flags);
221 } else {
222 req = blk_mq_alloc_request_hctx(q, nvme_is_write(cmd), flags,
223 qid ? qid - 1 : 0);
224 }
21d34711 225 if (IS_ERR(req))
4160982e 226 return req;
21d34711
CH		 227
228 req->cmd_type = REQ_TYPE_DRV_PRIV;
229 req->cmd_flags |= REQ_FAILFAST_DRIVER;
d49187e9 230 nvme_req(req)->cmd = cmd;
21d34711 231
4160982e
CH		 232 return req;
233}
576d55d6 234EXPORT_SYMBOL_GPL(nvme_alloc_request);
4160982e 235
8093f7ca
ML		 236static inline void nvme_setup_flush(struct nvme_ns *ns,
237 struct nvme_command *cmnd)
238{
239 memset(cmnd, 0, sizeof(*cmnd));
240 cmnd->common.opcode = nvme_cmd_flush;
241 cmnd->common.nsid = cpu_to_le32(ns->ns_id);
242}
243
244static inline int nvme_setup_discard(struct nvme_ns *ns, struct request *req,
245 struct nvme_command *cmnd)
246{
247 struct nvme_dsm_range *range;
8093f7ca
ML		 248 unsigned int nr_bytes = blk_rq_bytes(req);
249
250 range = kmalloc(sizeof(*range), GFP_ATOMIC);
251 if (!range)
252 return BLK_MQ_RQ_QUEUE_BUSY;
253
254 range->cattr = cpu_to_le32(0);
255 range->nlb = cpu_to_le32(nr_bytes >> ns->lba_shift);
256 range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
257
258 memset(cmnd, 0, sizeof(*cmnd));
259 cmnd->dsm.opcode = nvme_cmd_dsm;
260 cmnd->dsm.nsid = cpu_to_le32(ns->ns_id);
261 cmnd->dsm.nr = 0;
262 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
263
f9d03f96
CH		 264 req->special_vec.bv_page = virt_to_page(range);
265 req->special_vec.bv_offset = offset_in_page(range);
266 req->special_vec.bv_len = sizeof(*range);
267 req->rq_flags |= RQF_SPECIAL_PAYLOAD;
8093f7ca 268
bac0000a 269 return BLK_MQ_RQ_QUEUE_OK;
8093f7ca 270}
8093f7ca 271
8093f7ca
ML		 272static inline void nvme_setup_rw(struct nvme_ns *ns, struct request *req,
273 struct nvme_command *cmnd)
274{
275 u16 control = 0;
276 u32 dsmgmt = 0;
277
278 if (req->cmd_flags & REQ_FUA)
279 control |= NVME_RW_FUA;
280 if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD))
281 control |= NVME_RW_LR;
282
283 if (req->cmd_flags & REQ_RAHEAD)
284 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
285
286 memset(cmnd, 0, sizeof(*cmnd));
287 cmnd->rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read);
8093f7ca
ML		 288 cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
289 cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
290 cmnd->rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
291
292 if (ns->ms) {
293 switch (ns->pi_type) {
294 case NVME_NS_DPS_PI_TYPE3:
295 control |= NVME_RW_PRINFO_PRCHK_GUARD;
296 break;
297 case NVME_NS_DPS_PI_TYPE1:
298 case NVME_NS_DPS_PI_TYPE2:
299 control |= NVME_RW_PRINFO_PRCHK_GUARD |
300 NVME_RW_PRINFO_PRCHK_REF;
301 cmnd->rw.reftag = cpu_to_le32(
302 nvme_block_nr(ns, blk_rq_pos(req)));
303 break;
304 }
305 if (!blk_integrity_rq(req))
306 control |= NVME_RW_PRINFO_PRACT;
307 }
308
309 cmnd->rw.control = cpu_to_le16(control);
310 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
311}
312
313int nvme_setup_cmd(struct nvme_ns *ns, struct request *req,
314 struct nvme_command *cmd)
315{
bac0000a 316 int ret = BLK_MQ_RQ_QUEUE_OK;
8093f7ca
ML		 317
318 if (req->cmd_type == REQ_TYPE_DRV_PRIV)
d49187e9 319 memcpy(cmd, nvme_req(req)->cmd, sizeof(*cmd));
3a5e02ce 320 else if (req_op(req) == REQ_OP_FLUSH)
8093f7ca 321 nvme_setup_flush(ns, cmd);
c2df40df 322 else if (req_op(req) == REQ_OP_DISCARD)
8093f7ca
ML		 323 ret = nvme_setup_discard(ns, req, cmd);
324 else
325 nvme_setup_rw(ns, req, cmd);
326
721b3917
JS		 327 cmd->common.command_id = req->tag;
328
8093f7ca
ML		 329 return ret;
330}
331EXPORT_SYMBOL_GPL(nvme_setup_cmd);
332
4160982e
CH		 333/*
334 * Returns 0 on success. If the result is negative, it's a Linux error code;
335 * if the result is positive, it's an NVM Express status code
336 */
337int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
d49187e9 338 union nvme_result *result, void *buffer, unsigned bufflen,
eb71f435 339 unsigned timeout, int qid, int at_head, int flags)
4160982e
CH		 340{
341 struct request *req;
342 int ret;
343
eb71f435 344 req = nvme_alloc_request(q, cmd, flags, qid);
4160982e
CH		 345 if (IS_ERR(req))
346 return PTR_ERR(req);
347
348 req->timeout = timeout ? timeout : ADMIN_TIMEOUT;
349
21d34711
CH		 350 if (buffer && bufflen) {
351 ret = blk_rq_map_kern(q, req, buffer, bufflen, GFP_KERNEL);
352 if (ret)
353 goto out;
4160982e
CH		 354 }
355
eb71f435 356 blk_execute_rq(req->q, NULL, req, at_head);
d49187e9
CH		 357 if (result)
358 *result = nvme_req(req)->result;
4160982e
CH		 359 ret = req->errors;
360 out:
361 blk_mq_free_request(req);
362 return ret;
363}
eb71f435 364EXPORT_SYMBOL_GPL(__nvme_submit_sync_cmd);
4160982e
CH		 365
366int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
367 void *buffer, unsigned bufflen)
368{
eb71f435
CH		 369 return __nvme_submit_sync_cmd(q, cmd, NULL, buffer, bufflen, 0,
370 NVME_QID_ANY, 0, 0);
4160982e 371}
576d55d6 372EXPORT_SYMBOL_GPL(nvme_submit_sync_cmd);
4160982e 373
0b7f1f26
KB		 374int __nvme_submit_user_cmd(struct request_queue *q, struct nvme_command *cmd,
375 void __user *ubuffer, unsigned bufflen,
376 void __user *meta_buffer, unsigned meta_len, u32 meta_seed,
377 u32 *result, unsigned timeout)
4160982e 378{
7a5abb4b 379 bool write = nvme_is_write(cmd);
0b7f1f26
KB		 380 struct nvme_ns *ns = q->queuedata;
381 struct gendisk *disk = ns ? ns->disk : NULL;
4160982e 382 struct request *req;
0b7f1f26
KB		 383 struct bio *bio = NULL;
384 void *meta = NULL;
4160982e
CH		 385 int ret;
386
eb71f435 387 req = nvme_alloc_request(q, cmd, 0, NVME_QID_ANY);
4160982e
CH		 388 if (IS_ERR(req))
389 return PTR_ERR(req);
390
391 req->timeout = timeout ? timeout : ADMIN_TIMEOUT;
392
393 if (ubuffer && bufflen) {
21d34711
CH		 394 ret = blk_rq_map_user(q, req, NULL, ubuffer, bufflen,
395 GFP_KERNEL);
396 if (ret)
397 goto out;
398 bio = req->bio;
21d34711 399
0b7f1f26
KB		 400 if (!disk)
401 goto submit;
402 bio->bi_bdev = bdget_disk(disk, 0);
403 if (!bio->bi_bdev) {
404 ret = -ENODEV;
405 goto out_unmap;
406 }
407
e9fc63d6 408 if (meta_buffer && meta_len) {
0b7f1f26
KB		 409 struct bio_integrity_payload *bip;
410
411 meta = kmalloc(meta_len, GFP_KERNEL);
412 if (!meta) {
413 ret = -ENOMEM;
414 goto out_unmap;
415 }
416
417 if (write) {
418 if (copy_from_user(meta, meta_buffer,
419 meta_len)) {
420 ret = -EFAULT;
421 goto out_free_meta;
422 }
423 }
424
425 bip = bio_integrity_alloc(bio, GFP_KERNEL, 1);
06c1e390
KB		 426 if (IS_ERR(bip)) {
427 ret = PTR_ERR(bip);
0b7f1f26
KB		 428 goto out_free_meta;
429 }
430
431 bip->bip_iter.bi_size = meta_len;
432 bip->bip_iter.bi_sector = meta_seed;
433
434 ret = bio_integrity_add_page(bio, virt_to_page(meta),
435 meta_len, offset_in_page(meta));
436 if (ret != meta_len) {
437 ret = -ENOMEM;
438 goto out_free_meta;
439 }
440 }
441 }
442 submit:
443 blk_execute_rq(req->q, disk, req, 0);
444 ret = req->errors;
21d34711 445 if (result)
d49187e9 446 *result = le32_to_cpu(nvme_req(req)->result.u32);
0b7f1f26
KB		 447 if (meta && !ret && !write) {
448 if (copy_to_user(meta_buffer, meta, meta_len))
449 ret = -EFAULT;
450 }
451 out_free_meta:
452 kfree(meta);
453 out_unmap:
454 if (bio) {
455 if (disk && bio->bi_bdev)
456 bdput(bio->bi_bdev);
457 blk_rq_unmap_user(bio);
458 }
21d34711
CH		 459 out:
460 blk_mq_free_request(req);
461 return ret;
462}
463
0b7f1f26
KB		 464int nvme_submit_user_cmd(struct request_queue *q, struct nvme_command *cmd,
465 void __user *ubuffer, unsigned bufflen, u32 *result,
466 unsigned timeout)
467{
468 return __nvme_submit_user_cmd(q, cmd, ubuffer, bufflen, NULL, 0, 0,
469 result, timeout);
470}
471
038bd4cb
SG		 472static void nvme_keep_alive_end_io(struct request *rq, int error)
473{
474 struct nvme_ctrl *ctrl = rq->end_io_data;
475
476 blk_mq_free_request(rq);
477
478 if (error) {
479 dev_err(ctrl->device,
480 "failed nvme_keep_alive_end_io error=%d\n", error);
481 return;
482 }
483
484 schedule_delayed_work(&ctrl->ka_work, ctrl->kato * HZ);
485}
486
487static int nvme_keep_alive(struct nvme_ctrl *ctrl)
488{
489 struct nvme_command c;
490 struct request *rq;
491
492 memset(&c, 0, sizeof(c));
493 c.common.opcode = nvme_admin_keep_alive;
494
495 rq = nvme_alloc_request(ctrl->admin_q, &c, BLK_MQ_REQ_RESERVED,
496 NVME_QID_ANY);
497 if (IS_ERR(rq))
498 return PTR_ERR(rq);
499
500 rq->timeout = ctrl->kato * HZ;
501 rq->end_io_data = ctrl;
502
503 blk_execute_rq_nowait(rq->q, NULL, rq, 0, nvme_keep_alive_end_io);
504
505 return 0;
506}
507
508static void nvme_keep_alive_work(struct work_struct *work)
509{
510 struct nvme_ctrl *ctrl = container_of(to_delayed_work(work),
511 struct nvme_ctrl, ka_work);
512
513 if (nvme_keep_alive(ctrl)) {
514 /* allocation failure, reset the controller */
515 dev_err(ctrl->device, "keep-alive failed\n");
516 ctrl->ops->reset_ctrl(ctrl);
517 return;
518 }
519}
520
521void nvme_start_keep_alive(struct nvme_ctrl *ctrl)
522{
523 if (unlikely(ctrl->kato == 0))
524 return;
525
526 INIT_DELAYED_WORK(&ctrl->ka_work, nvme_keep_alive_work);
527 schedule_delayed_work(&ctrl->ka_work, ctrl->kato * HZ);
528}
529EXPORT_SYMBOL_GPL(nvme_start_keep_alive);
530
531void nvme_stop_keep_alive(struct nvme_ctrl *ctrl)
532{
533 if (unlikely(ctrl->kato == 0))
534 return;
535
536 cancel_delayed_work_sync(&ctrl->ka_work);
537}
538EXPORT_SYMBOL_GPL(nvme_stop_keep_alive);
539
1c63dc66 540int nvme_identify_ctrl(struct nvme_ctrl *dev, struct nvme_id_ctrl **id)
21d34711
CH		 541{
542 struct nvme_command c = { };
543 int error;
544
545 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
546 c.identify.opcode = nvme_admin_identify;
fa606826 547 c.identify.cns = cpu_to_le32(NVME_ID_CNS_CTRL);
21d34711
CH		 548
549 *id = kmalloc(sizeof(struct nvme_id_ctrl), GFP_KERNEL);
550 if (!*id)
551 return -ENOMEM;
552
553 error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
554 sizeof(struct nvme_id_ctrl));
555 if (error)
556 kfree(*id);
557 return error;
558}
559
540c801c
KB		 560static int nvme_identify_ns_list(struct nvme_ctrl *dev, unsigned nsid, __le32 *ns_list)
561{
562 struct nvme_command c = { };
563
564 c.identify.opcode = nvme_admin_identify;
fa606826 565 c.identify.cns = cpu_to_le32(NVME_ID_CNS_NS_ACTIVE_LIST);
540c801c
KB		 566 c.identify.nsid = cpu_to_le32(nsid);
567 return nvme_submit_sync_cmd(dev->admin_q, &c, ns_list, 0x1000);
568}
569
1c63dc66 570int nvme_identify_ns(struct nvme_ctrl *dev, unsigned nsid,
21d34711
CH		 571 struct nvme_id_ns **id)
572{
573 struct nvme_command c = { };
574 int error;
575
576 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
577 c.identify.opcode = nvme_admin_identify,
578 c.identify.nsid = cpu_to_le32(nsid),
579
580 *id = kmalloc(sizeof(struct nvme_id_ns), GFP_KERNEL);
581 if (!*id)
582 return -ENOMEM;
583
584 error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
585 sizeof(struct nvme_id_ns));
586 if (error)
587 kfree(*id);
588 return error;
589}
590
1c63dc66 591int nvme_get_features(struct nvme_ctrl *dev, unsigned fid, unsigned nsid,
1a6fe74d 592 void *buffer, size_t buflen, u32 *result)
21d34711
CH		 593{
594 struct nvme_command c;
d49187e9 595 union nvme_result res;
1cb3cce5 596 int ret;
21d34711
CH		 597
598 memset(&c, 0, sizeof(c));
599 c.features.opcode = nvme_admin_get_features;
600 c.features.nsid = cpu_to_le32(nsid);
21d34711
CH		 601 c.features.fid = cpu_to_le32(fid);
602
d49187e9 603 ret = __nvme_submit_sync_cmd(dev->admin_q, &c, &res, buffer, buflen, 0,
eb71f435 604 NVME_QID_ANY, 0, 0);
9b47f77a 605 if (ret >= 0 && result)
d49187e9 606 *result = le32_to_cpu(res.u32);
1cb3cce5 607 return ret;
21d34711
CH		 608}
609
1c63dc66 610int nvme_set_features(struct nvme_ctrl *dev, unsigned fid, unsigned dword11,
1a6fe74d 611 void *buffer, size_t buflen, u32 *result)
21d34711
CH		 612{
613 struct nvme_command c;
d49187e9 614 union nvme_result res;
1cb3cce5 615 int ret;
21d34711
CH		 616
617 memset(&c, 0, sizeof(c));
618 c.features.opcode = nvme_admin_set_features;
21d34711
CH		 619 c.features.fid = cpu_to_le32(fid);
620 c.features.dword11 = cpu_to_le32(dword11);
621
d49187e9 622 ret = __nvme_submit_sync_cmd(dev->admin_q, &c, &res,
1a6fe74d 623 buffer, buflen, 0, NVME_QID_ANY, 0, 0);
9b47f77a 624 if (ret >= 0 && result)
d49187e9 625 *result = le32_to_cpu(res.u32);
1cb3cce5 626 return ret;
21d34711
CH		 627}
628
1c63dc66 629int nvme_get_log_page(struct nvme_ctrl *dev, struct nvme_smart_log **log)
21d34711
CH		 630{
631 struct nvme_command c = { };
632 int error;
633
634 c.common.opcode = nvme_admin_get_log_page,
635 c.common.nsid = cpu_to_le32(0xFFFFFFFF),
636 c.common.cdw10[0] = cpu_to_le32(
637 (((sizeof(struct nvme_smart_log) / 4) - 1) << 16) |
638 NVME_LOG_SMART),
639
640 *log = kmalloc(sizeof(struct nvme_smart_log), GFP_KERNEL);
641 if (!*log)
642 return -ENOMEM;
643
644 error = nvme_submit_sync_cmd(dev->admin_q, &c, *log,
645 sizeof(struct nvme_smart_log));
646 if (error)
647 kfree(*log);
648 return error;
649}
1673f1f0 650
9a0be7ab
CH		 651int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count)
652{
653 u32 q_count = (*count - 1) | ((*count - 1) << 16);
654 u32 result;
655 int status, nr_io_queues;
656
1a6fe74d 657 status = nvme_set_features(ctrl, NVME_FEAT_NUM_QUEUES, q_count, NULL, 0,
9a0be7ab 658 &result);
f5fa90dc 659 if (status < 0)
9a0be7ab
CH		 660 return status;
661
f5fa90dc
CH		 662 /*
663 * Degraded controllers might return an error when setting the queue
664 * count. We still want to be able to bring them online and offer
665 * access to the admin queue, as that might be only way to fix them up.
666 */
667 if (status > 0) {
668 dev_err(ctrl->dev, "Could not set queue count (%d)\n", status);
669 *count = 0;
670 } else {
671 nr_io_queues = min(result & 0xffff, result >> 16) + 1;
672 *count = min(*count, nr_io_queues);
673 }
674
9a0be7ab
CH		 675 return 0;
676}
576d55d6 677EXPORT_SYMBOL_GPL(nvme_set_queue_count);
9a0be7ab 678
1673f1f0
CH		 679static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
680{
681 struct nvme_user_io io;
682 struct nvme_command c;
683 unsigned length, meta_len;
684 void __user *metadata;
685
686 if (copy_from_user(&io, uio, sizeof(io)))
687 return -EFAULT;
63088ec7
KB		 688 if (io.flags)
689 return -EINVAL;
1673f1f0
CH		 690
691 switch (io.opcode) {
692 case nvme_cmd_write:
693 case nvme_cmd_read:
694 case nvme_cmd_compare:
695 break;
696 default:
697 return -EINVAL;
698 }
699
700 length = (io.nblocks + 1) << ns->lba_shift;
701 meta_len = (io.nblocks + 1) * ns->ms;
702 metadata = (void __user *)(uintptr_t)io.metadata;
703
704 if (ns->ext) {
705 length += meta_len;
706 meta_len = 0;
707 } else if (meta_len) {
708 if ((io.metadata & 3) || !io.metadata)
709 return -EINVAL;
710 }
711
712 memset(&c, 0, sizeof(c));
713 c.rw.opcode = io.opcode;
714 c.rw.flags = io.flags;
715 c.rw.nsid = cpu_to_le32(ns->ns_id);
716 c.rw.slba = cpu_to_le64(io.slba);
717 c.rw.length = cpu_to_le16(io.nblocks);
718 c.rw.control = cpu_to_le16(io.control);
719 c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
720 c.rw.reftag = cpu_to_le32(io.reftag);
721 c.rw.apptag = cpu_to_le16(io.apptag);
722 c.rw.appmask = cpu_to_le16(io.appmask);
723
724 return __nvme_submit_user_cmd(ns->queue, &c,
725 (void __user *)(uintptr_t)io.addr, length,
726 metadata, meta_len, io.slba, NULL, 0);
727}
728
f3ca80fc 729static int nvme_user_cmd(struct nvme_ctrl *ctrl, struct nvme_ns *ns,
1673f1f0
CH		 730 struct nvme_passthru_cmd __user *ucmd)
731{
732 struct nvme_passthru_cmd cmd;
733 struct nvme_command c;
734 unsigned timeout = 0;
735 int status;
736
737 if (!capable(CAP_SYS_ADMIN))
738 return -EACCES;
739 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
740 return -EFAULT;
63088ec7
KB		 741 if (cmd.flags)
742 return -EINVAL;
1673f1f0
CH		 743
744 memset(&c, 0, sizeof(c));
745 c.common.opcode = cmd.opcode;
746 c.common.flags = cmd.flags;
747 c.common.nsid = cpu_to_le32(cmd.nsid);
748 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
749 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
750 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
751 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
752 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
753 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
754 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
755 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
756
757 if (cmd.timeout_ms)
758 timeout = msecs_to_jiffies(cmd.timeout_ms);
759
760 status = nvme_submit_user_cmd(ns ? ns->queue : ctrl->admin_q, &c,
d1ea7be5 761 (void __user *)(uintptr_t)cmd.addr, cmd.data_len,
1673f1f0
CH		 762 &cmd.result, timeout);
763 if (status >= 0) {
764 if (put_user(cmd.result, &ucmd->result))
765 return -EFAULT;
766 }
767
768 return status;
769}
770
771static int nvme_ioctl(struct block_device *bdev, fmode_t mode,
772 unsigned int cmd, unsigned long arg)
773{
774 struct nvme_ns *ns = bdev->bd_disk->private_data;
775
776 switch (cmd) {
777 case NVME_IOCTL_ID:
778 force_successful_syscall_return();
779 return ns->ns_id;
780 case NVME_IOCTL_ADMIN_CMD:
781 return nvme_user_cmd(ns->ctrl, NULL, (void __user *)arg);
782 case NVME_IOCTL_IO_CMD:
783 return nvme_user_cmd(ns->ctrl, ns, (void __user *)arg);
784 case NVME_IOCTL_SUBMIT_IO:
785 return nvme_submit_io(ns, (void __user *)arg);
44907332 786#ifdef CONFIG_BLK_DEV_NVME_SCSI
1673f1f0
CH		 787 case SG_GET_VERSION_NUM:
788 return nvme_sg_get_version_num((void __user *)arg);
789 case SG_IO:
790 return nvme_sg_io(ns, (void __user *)arg);
44907332 791#endif
1673f1f0
CH		 792 default:
793 return -ENOTTY;
794 }
795}
796
797#ifdef CONFIG_COMPAT
798static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode,
799 unsigned int cmd, unsigned long arg)
800{
801 switch (cmd) {
802 case SG_IO:
803 return -ENOIOCTLCMD;
804 }
805 return nvme_ioctl(bdev, mode, cmd, arg);
806}
807#else
808#define nvme_compat_ioctl NULL
809#endif
810
811static int nvme_open(struct block_device *bdev, fmode_t mode)
812{
813 return nvme_get_ns_from_disk(bdev->bd_disk) ? 0 : -ENXIO;
814}
815
816static void nvme_release(struct gendisk *disk, fmode_t mode)
817{
e439bb12
SG		 818 struct nvme_ns *ns = disk->private_data;
819
820 module_put(ns->ctrl->ops->module);
821 nvme_put_ns(ns);
1673f1f0
CH		 822}
823
824static int nvme_getgeo(struct block_device *bdev, struct hd_geometry *geo)
825{
826 /* some standard values */
827 geo->heads = 1 << 6;
828 geo->sectors = 1 << 5;
829 geo->cylinders = get_capacity(bdev->bd_disk) >> 11;
830 return 0;
831}
832
833#ifdef CONFIG_BLK_DEV_INTEGRITY
834static void nvme_init_integrity(struct nvme_ns *ns)
835{
836 struct blk_integrity integrity;
837
fa9a89fc 838 memset(&integrity, 0, sizeof(integrity));
1673f1f0
CH		 839 switch (ns->pi_type) {
840 case NVME_NS_DPS_PI_TYPE3:
841 integrity.profile = &t10_pi_type3_crc;
ba36c21b
NB		 842 integrity.tag_size = sizeof(u16) + sizeof(u32);
843 integrity.flags |= BLK_INTEGRITY_DEVICE_CAPABLE;
1673f1f0
CH		 844 break;
845 case NVME_NS_DPS_PI_TYPE1:
846 case NVME_NS_DPS_PI_TYPE2:
847 integrity.profile = &t10_pi_type1_crc;
ba36c21b
NB		 848 integrity.tag_size = sizeof(u16);
849 integrity.flags |= BLK_INTEGRITY_DEVICE_CAPABLE;
1673f1f0
CH		 850 break;
851 default:
852 integrity.profile = NULL;
853 break;
854 }
855 integrity.tuple_size = ns->ms;
856 blk_integrity_register(ns->disk, &integrity);
857 blk_queue_max_integrity_segments(ns->queue, 1);
858}
859#else
860static void nvme_init_integrity(struct nvme_ns *ns)
861{
862}
863#endif /* CONFIG_BLK_DEV_INTEGRITY */
864
865static void nvme_config_discard(struct nvme_ns *ns)
866{
08095e70 867 struct nvme_ctrl *ctrl = ns->ctrl;
1673f1f0 868 u32 logical_block_size = queue_logical_block_size(ns->queue);
08095e70
KB		 869
870 if (ctrl->quirks & NVME_QUIRK_DISCARD_ZEROES)
871 ns->queue->limits.discard_zeroes_data = 1;
872 else
873 ns->queue->limits.discard_zeroes_data = 0;
874
1673f1f0
CH		 875 ns->queue->limits.discard_alignment = logical_block_size;
876 ns->queue->limits.discard_granularity = logical_block_size;
bd0fc288 877 blk_queue_max_discard_sectors(ns->queue, UINT_MAX);
1673f1f0
CH		 878 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
879}
880
ac81bfa9 881static int nvme_revalidate_ns(struct nvme_ns *ns, struct nvme_id_ns **id)
1673f1f0 882{
ac81bfa9 883 if (nvme_identify_ns(ns->ctrl, ns->ns_id, id)) {
b0b4e09c 884 dev_warn(ns->ctrl->dev, "%s: Identify failure\n", __func__);
1673f1f0
CH		 885 return -ENODEV;
886 }
1673f1f0 887
ac81bfa9
MB		 888 if ((*id)->ncap == 0) {
889 kfree(*id);
890 return -ENODEV;
1673f1f0
CH		 891 }
892
8ef2074d 893 if (ns->ctrl->vs >= NVME_VS(1, 1, 0))
ac81bfa9 894 memcpy(ns->eui, (*id)->eui64, sizeof(ns->eui));
8ef2074d 895 if (ns->ctrl->vs >= NVME_VS(1, 2, 0))
ac81bfa9
MB		 896 memcpy(ns->uuid, (*id)->nguid, sizeof(ns->uuid));
897
898 return 0;
899}
900
901static void __nvme_revalidate_disk(struct gendisk *disk, struct nvme_id_ns *id)
902{
903 struct nvme_ns *ns = disk->private_data;
904 u8 lbaf, pi_type;
905 u16 old_ms;
906 unsigned short bs;
2b9b6e86 907
1673f1f0
CH		 908 old_ms = ns->ms;
909 lbaf = id->flbas & NVME_NS_FLBAS_LBA_MASK;
910 ns->lba_shift = id->lbaf[lbaf].ds;
911 ns->ms = le16_to_cpu(id->lbaf[lbaf].ms);
912 ns->ext = ns->ms && (id->flbas & NVME_NS_FLBAS_META_EXT);
913
914 /*
915 * If identify namespace failed, use default 512 byte block size so
916 * block layer can use before failing read/write for 0 capacity.
917 */
918 if (ns->lba_shift == 0)
919 ns->lba_shift = 9;
920 bs = 1 << ns->lba_shift;
1673f1f0
CH		 921 /* XXX: PI implementation requires metadata equal t10 pi tuple size */
922 pi_type = ns->ms == sizeof(struct t10_pi_tuple) ?
923 id->dps & NVME_NS_DPS_PI_MASK : 0;
924
925 blk_mq_freeze_queue(disk->queue);
926 if (blk_get_integrity(disk) && (ns->pi_type != pi_type ||
927 ns->ms != old_ms ||
928 bs != queue_logical_block_size(disk->queue) ||
929 (ns->ms && ns->ext)))
930 blk_integrity_unregister(disk);
931
932 ns->pi_type = pi_type;
933 blk_queue_logical_block_size(ns->queue, bs);
934
4b9d5b15 935 if (ns->ms && !blk_get_integrity(disk) && !ns->ext)
1673f1f0 936 nvme_init_integrity(ns);
1673f1f0
CH		 937 if (ns->ms && !(ns->ms == 8 && ns->pi_type) && !blk_get_integrity(disk))
938 set_capacity(disk, 0);
939 else
940 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
941
942 if (ns->ctrl->oncs & NVME_CTRL_ONCS_DSM)
943 nvme_config_discard(ns);
944 blk_mq_unfreeze_queue(disk->queue);
ac81bfa9 945}
1673f1f0 946
ac81bfa9
MB		 947static int nvme_revalidate_disk(struct gendisk *disk)
948{
949 struct nvme_ns *ns = disk->private_data;
950 struct nvme_id_ns *id = NULL;
951 int ret;
952
953 if (test_bit(NVME_NS_DEAD, &ns->flags)) {
954 set_capacity(disk, 0);
955 return -ENODEV;
956 }
957
958 ret = nvme_revalidate_ns(ns, &id);
959 if (ret)
960 return ret;
961
962 __nvme_revalidate_disk(disk, id);
1673f1f0 963 kfree(id);
ac81bfa9 964
1673f1f0
CH		 965 return 0;
966}
967
968static char nvme_pr_type(enum pr_type type)
969{
970 switch (type) {
971 case PR_WRITE_EXCLUSIVE:
972 return 1;
973 case PR_EXCLUSIVE_ACCESS:
974 return 2;
975 case PR_WRITE_EXCLUSIVE_REG_ONLY:
976 return 3;
977 case PR_EXCLUSIVE_ACCESS_REG_ONLY:
978 return 4;
979 case PR_WRITE_EXCLUSIVE_ALL_REGS:
980 return 5;
981 case PR_EXCLUSIVE_ACCESS_ALL_REGS:
982 return 6;
983 default:
984 return 0;
985 }
986};
987
988static int nvme_pr_command(struct block_device *bdev, u32 cdw10,
989 u64 key, u64 sa_key, u8 op)
990{
991 struct nvme_ns *ns = bdev->bd_disk->private_data;
992 struct nvme_command c;
993 u8 data[16] = { 0, };
994
995 put_unaligned_le64(key, &data[0]);
996 put_unaligned_le64(sa_key, &data[8]);
997
998 memset(&c, 0, sizeof(c));
999 c.common.opcode = op;
1000 c.common.nsid = cpu_to_le32(ns->ns_id);
1001 c.common.cdw10[0] = cpu_to_le32(cdw10);
1002
1003 return nvme_submit_sync_cmd(ns->queue, &c, data, 16);
1004}
1005
1006static int nvme_pr_register(struct block_device *bdev, u64 old,
1007 u64 new, unsigned flags)
1008{
1009 u32 cdw10;
1010
1011 if (flags & ~PR_FL_IGNORE_KEY)
1012 return -EOPNOTSUPP;
1013
1014 cdw10 = old ? 2 : 0;
1015 cdw10 |= (flags & PR_FL_IGNORE_KEY) ? 1 << 3 : 0;
1016 cdw10 |= (1 << 30) | (1 << 31); /* PTPL=1 */
1017 return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_register);
1018}
1019
1020static int nvme_pr_reserve(struct block_device *bdev, u64 key,
1021 enum pr_type type, unsigned flags)
1022{
1023 u32 cdw10;
1024
1025 if (flags & ~PR_FL_IGNORE_KEY)
1026 return -EOPNOTSUPP;
1027
1028 cdw10 = nvme_pr_type(type) << 8;
1029 cdw10 |= ((flags & PR_FL_IGNORE_KEY) ? 1 << 3 : 0);
1030 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_acquire);
1031}
1032
1033static int nvme_pr_preempt(struct block_device *bdev, u64 old, u64 new,
1034 enum pr_type type, bool abort)
1035{
1036 u32 cdw10 = nvme_pr_type(type) << 8 | abort ? 2 : 1;
1037 return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_acquire);
1038}
1039
1040static int nvme_pr_clear(struct block_device *bdev, u64 key)
1041{
8c0b3915 1042 u32 cdw10 = 1 | (key ? 1 << 3 : 0);
1673f1f0
CH		 1043 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_register);
1044}
1045
1046static int nvme_pr_release(struct block_device *bdev, u64 key, enum pr_type type)
1047{
1048 u32 cdw10 = nvme_pr_type(type) << 8 | key ? 1 << 3 : 0;
1049 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_release);
1050}
1051
1052static const struct pr_ops nvme_pr_ops = {
1053 .pr_register = nvme_pr_register,
1054 .pr_reserve = nvme_pr_reserve,
1055 .pr_release = nvme_pr_release,
1056 .pr_preempt = nvme_pr_preempt,
1057 .pr_clear = nvme_pr_clear,
1058};
1059
5bae7f73 1060static const struct block_device_operations nvme_fops = {
1673f1f0
CH		 1061 .owner = THIS_MODULE,
1062 .ioctl = nvme_ioctl,
1063 .compat_ioctl = nvme_compat_ioctl,
1064 .open = nvme_open,
1065 .release = nvme_release,
1066 .getgeo = nvme_getgeo,
1067 .revalidate_disk= nvme_revalidate_disk,
1068 .pr_ops = &nvme_pr_ops,
1069};
1070
5fd4ce1b
CH		 1071static int nvme_wait_ready(struct nvme_ctrl *ctrl, u64 cap, bool enabled)
1072{
1073 unsigned long timeout =
1074 ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1075 u32 csts, bit = enabled ? NVME_CSTS_RDY : 0;
1076 int ret;
1077
1078 while ((ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts)) == 0) {
0df1e4f5
KB		 1079 if (csts == ~0)
1080 return -ENODEV;
5fd4ce1b
CH		 1081 if ((csts & NVME_CSTS_RDY) == bit)
1082 break;
1083
1084 msleep(100);
1085 if (fatal_signal_pending(current))
1086 return -EINTR;
1087 if (time_after(jiffies, timeout)) {
1b3c47c1 1088 dev_err(ctrl->device,
5fd4ce1b
CH		 1089 "Device not ready; aborting %s\n", enabled ?
1090 "initialisation" : "reset");
1091 return -ENODEV;
1092 }
1093 }
1094
1095 return ret;
1096}
1097
1098/*
1099 * If the device has been passed off to us in an enabled state, just clear
1100 * the enabled bit. The spec says we should set the 'shutdown notification
1101 * bits', but doing so may cause the device to complete commands to the
1102 * admin queue ... and we don't know what memory that might be pointing at!
1103 */
1104int nvme_disable_ctrl(struct nvme_ctrl *ctrl, u64 cap)
1105{
1106 int ret;
1107
1108 ctrl->ctrl_config &= ~NVME_CC_SHN_MASK;
1109 ctrl->ctrl_config &= ~NVME_CC_ENABLE;
1110
1111 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
1112 if (ret)
1113 return ret;
54adc010 1114
b5a10c5f 1115 if (ctrl->quirks & NVME_QUIRK_DELAY_BEFORE_CHK_RDY)
54adc010
GP		 1116 msleep(NVME_QUIRK_DELAY_AMOUNT);
1117
5fd4ce1b
CH		 1118 return nvme_wait_ready(ctrl, cap, false);
1119}
576d55d6 1120EXPORT_SYMBOL_GPL(nvme_disable_ctrl);
5fd4ce1b
CH		 1121
1122int nvme_enable_ctrl(struct nvme_ctrl *ctrl, u64 cap)
1123{
1124 /*
1125 * Default to a 4K page size, with the intention to update this
1126 * path in the future to accomodate architectures with differing
1127 * kernel and IO page sizes.
1128 */
1129 unsigned dev_page_min = NVME_CAP_MPSMIN(cap) + 12, page_shift = 12;
1130 int ret;
1131
1132 if (page_shift < dev_page_min) {
1b3c47c1 1133 dev_err(ctrl->device,
5fd4ce1b
CH		 1134 "Minimum device page size %u too large for host (%u)\n",
1135 1 << dev_page_min, 1 << page_shift);
1136 return -ENODEV;
1137 }
1138
1139 ctrl->page_size = 1 << page_shift;
1140
1141 ctrl->ctrl_config = NVME_CC_CSS_NVM;
1142 ctrl->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT;
1143 ctrl->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
1144 ctrl->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
1145 ctrl->ctrl_config |= NVME_CC_ENABLE;
1146
1147 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
1148 if (ret)
1149 return ret;
1150 return nvme_wait_ready(ctrl, cap, true);
1151}
576d55d6 1152EXPORT_SYMBOL_GPL(nvme_enable_ctrl);
5fd4ce1b
CH		 1153
1154int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl)
1155{
1156 unsigned long timeout = SHUTDOWN_TIMEOUT + jiffies;
1157 u32 csts;
1158 int ret;
1159
1160 ctrl->ctrl_config &= ~NVME_CC_SHN_MASK;
1161 ctrl->ctrl_config |= NVME_CC_SHN_NORMAL;
1162
1163 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
1164 if (ret)
1165 return ret;
1166
1167 while ((ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts)) == 0) {
1168 if ((csts & NVME_CSTS_SHST_MASK) == NVME_CSTS_SHST_CMPLT)
1169 break;
1170
1171 msleep(100);
1172 if (fatal_signal_pending(current))
1173 return -EINTR;
1174 if (time_after(jiffies, timeout)) {
1b3c47c1 1175 dev_err(ctrl->device,
5fd4ce1b
CH		 1176 "Device shutdown incomplete; abort shutdown\n");
1177 return -ENODEV;
1178 }
1179 }
1180
1181 return ret;
1182}
576d55d6 1183EXPORT_SYMBOL_GPL(nvme_shutdown_ctrl);
5fd4ce1b 1184
da35825d
CH		 1185static void nvme_set_queue_limits(struct nvme_ctrl *ctrl,
1186 struct request_queue *q)
1187{
7c88cb00
JA		 1188 bool vwc = false;
1189
da35825d 1190 if (ctrl->max_hw_sectors) {
45686b61
CH		 1191 u32 max_segments =
1192 (ctrl->max_hw_sectors / (ctrl->page_size >> 9)) + 1;
1193
da35825d 1194 blk_queue_max_hw_sectors(q, ctrl->max_hw_sectors);
45686b61 1195 blk_queue_max_segments(q, min_t(u32, max_segments, USHRT_MAX));
da35825d 1196 }
e6282aef
KB		 1197 if (ctrl->quirks & NVME_QUIRK_STRIPE_SIZE)
1198 blk_queue_chunk_sectors(q, ctrl->max_hw_sectors);
da35825d 1199 blk_queue_virt_boundary(q, ctrl->page_size - 1);
7c88cb00
JA		 1200 if (ctrl->vwc & NVME_CTRL_VWC_PRESENT)
1201 vwc = true;
1202 blk_queue_write_cache(q, vwc, vwc);
da35825d
CH		 1203}
1204
441d14c0
AL		 1205static void nvme_configure_apst(struct nvme_ctrl *ctrl)
1206{
1207 /*
1208 * APST (Autonomous Power State Transition) lets us program a
1209 * table of power state transitions that the controller will
1210 * perform automatically. We configure it with a simple
1211 * heuristic: we are willing to spend at most 2% of the time
1212 * transitioning between power states. Therefore, when running
1213 * in any given state, we will enter the next lower-power
1214 * non-operational state after waiting 100 * (enlat + exlat)
1215 * microseconds, as long as that state's total latency is under
1216 * the requested maximum latency.
1217 *
1218 * We will not autonomously enter any non-operational state for
1219 * which the total latency exceeds ps_max_latency_us. Users
1220 * can set ps_max_latency_us to zero to turn off APST.
1221 */
1222
1223 unsigned apste;
1224 struct nvme_feat_auto_pst *table;
1802953d
AL		 1225 u64 max_lat_us = 0;
1226 int max_ps = -1;
441d14c0
AL		 1227 int ret;
1228
1229 /*
1230 * If APST isn't supported or if we haven't been initialized yet,
1231 * then don't do anything.
1232 */
1233 if (!ctrl->apsta)
1234 return;
1235
1236 if (ctrl->npss > 31) {
1237 dev_warn(ctrl->device, "NPSS is invalid; not using APST\n");
1238 return;
1239 }
1240
1241 table = kzalloc(sizeof(*table), GFP_KERNEL);
1242 if (!table)
1243 return;
1244
1245 if (ctrl->ps_max_latency_us == 0) {
1246 /* Turn off APST. */
1247 apste = 0;
1802953d 1248 dev_dbg(ctrl->device, "APST disabled\n");
441d14c0
AL		 1249 } else {
1250 __le64 target = cpu_to_le64(0);
1251 int state;
1252
1253 /*
1254 * Walk through all states from lowest- to highest-power.
1255 * According to the spec, lower-numbered states use more
1256 * power. NPSS, despite the name, is the index of the
1257 * lowest-power state, not the number of states.
1258 */
1259 for (state = (int)ctrl->npss; state >= 0; state--) {
1260 u64 total_latency_us, transition_ms;
1261
1262 if (target)
1263 table->entries[state] = target;
1264
788e6a48
AL		 1265 /*
1266 * Don't allow transitions to the deepest state
1267 * if it's quirked off.
1268 */
1269 if (state == ctrl->npss &&
1270 (ctrl->quirks & NVME_QUIRK_NO_DEEPEST_PS))
1271 continue;
1272
441d14c0
AL		 1273 /*
1274 * Is this state a useful non-operational state for
1275 * higher-power states to autonomously transition to?
1276 */
1277 if (!(ctrl->psd[state].flags &
1278 NVME_PS_FLAGS_NON_OP_STATE))
1279 continue;
1280
1281 total_latency_us =
1282 (u64)le32_to_cpu(ctrl->psd[state].entry_lat) +
1283 + le32_to_cpu(ctrl->psd[state].exit_lat);
1284 if (total_latency_us > ctrl->ps_max_latency_us)
1285 continue;
1286
1287 /*
1288 * This state is good. Use it as the APST idle
1289 * target for higher power states.
1290 */
1291 transition_ms = total_latency_us + 19;
1292 do_div(transition_ms, 20);
1293 if (transition_ms > (1 << 24) - 1)
1294 transition_ms = (1 << 24) - 1;
1295
1296 target = cpu_to_le64((state << 3) |
1297 (transition_ms << 8));
1802953d
AL		 1298
1299 if (max_ps == -1)
1300 max_ps = state;
1301
1302 if (total_latency_us > max_lat_us)
1303 max_lat_us = total_latency_us;
441d14c0
AL		 1304 }
1305
1306 apste = 1;
1802953d
AL		 1307
1308 if (max_ps == -1) {
1309 dev_dbg(ctrl->device, "APST enabled but no non-operational states are available\n");
1310 } else {
1311 dev_dbg(ctrl->device, "APST enabled: max PS = %d, max round-trip latency = %lluus, table = %*phN\n",
1312 max_ps, max_lat_us, (int)sizeof(*table), table);
1313 }
441d14c0
AL		 1314 }
1315
1316 ret = nvme_set_features(ctrl, NVME_FEAT_AUTO_PST, apste,
1317 table, sizeof(*table), NULL);
1318 if (ret)
1319 dev_err(ctrl->device, "failed to set APST feature (%d)\n", ret);
1320
1321 kfree(table);
1322}
1323
1324static void nvme_set_latency_tolerance(struct device *dev, s32 val)
1325{
1326 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
1327 u64 latency;
1328
1329 switch (val) {
1330 case PM_QOS_LATENCY_TOLERANCE_NO_CONSTRAINT:
1331 case PM_QOS_LATENCY_ANY:
1332 latency = U64_MAX;
1333 break;
1334
1335 default:
1336 latency = val;
1337 }
1338
1339 if (ctrl->ps_max_latency_us != latency) {
1340 ctrl->ps_max_latency_us = latency;
1341 nvme_configure_apst(ctrl);
1342 }
1343}
1344
225a9366
AL		 1345struct nvme_core_quirk_entry {
1346 /*
1347 * NVMe model and firmware strings are padded with spaces. For
1348 * simplicity, strings in the quirk table are padded with NULLs
1349 * instead.
1350 */
1351 u16 vid;
1352 const char *mn;
1353 const char *fr;
1354 unsigned long quirks;
1355};
1356
1357static const struct nvme_core_quirk_entry core_quirks[] = {
bc3fb815
AL		 1358 {
1359 /*
1360 * This Toshiba device seems to die using any APST states. See:
1361 * https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1678184/comments/11
1362 */
1363 .vid = 0x1179,
1364 .mn = "THNSF5256GPUK TOSHIBA",
1365 .quirks = NVME_QUIRK_NO_APST,
1366 }
225a9366
AL		 1367};
1368
1369/* match is null-terminated but idstr is space-padded. */
1370static bool string_matches(const char *idstr, const char *match, size_t len)
1371{
1372 size_t matchlen;
1373
1374 if (!match)
1375 return true;
1376
1377 matchlen = strlen(match);
1378 WARN_ON_ONCE(matchlen > len);
1379
1380 if (memcmp(idstr, match, matchlen))
1381 return false;
1382
1383 for (; matchlen < len; matchlen++)
1384 if (idstr[matchlen] != ' ')
1385 return false;
1386
1387 return true;
1388}
1389
1390static bool quirk_matches(const struct nvme_id_ctrl *id,
1391 const struct nvme_core_quirk_entry *q)
1392{
1393 return q->vid == le16_to_cpu(id->vid) &&
1394 string_matches(id->mn, q->mn, sizeof(id->mn)) &&
1395 string_matches(id->fr, q->fr, sizeof(id->fr));
1396}
1397
7fd8930f
CH		 1398/*
1399 * Initialize the cached copies of the Identify data and various controller
1400 * register in our nvme_ctrl structure. This should be called as soon as
1401 * the admin queue is fully up and running.
1402 */
1403int nvme_init_identify(struct nvme_ctrl *ctrl)
1404{
1405 struct nvme_id_ctrl *id;
1406 u64 cap;
1407 int ret, page_shift;
a229dbf6 1408 u32 max_hw_sectors;
441d14c0 1409 u8 prev_apsta;
7fd8930f 1410
f3ca80fc
CH		 1411 ret = ctrl->ops->reg_read32(ctrl, NVME_REG_VS, &ctrl->vs);
1412 if (ret) {
1b3c47c1 1413 dev_err(ctrl->device, "Reading VS failed (%d)\n", ret);
f3ca80fc
CH		 1414 return ret;
1415 }
1416
7fd8930f
CH		 1417 ret = ctrl->ops->reg_read64(ctrl, NVME_REG_CAP, &cap);
1418 if (ret) {
1b3c47c1 1419 dev_err(ctrl->device, "Reading CAP failed (%d)\n", ret);
7fd8930f
CH		 1420 return ret;
1421 }
1422 page_shift = NVME_CAP_MPSMIN(cap) + 12;
1423
8ef2074d 1424 if (ctrl->vs >= NVME_VS(1, 1, 0))
f3ca80fc
CH		 1425 ctrl->subsystem = NVME_CAP_NSSRC(cap);
1426
7fd8930f
CH		 1427 ret = nvme_identify_ctrl(ctrl, &id);
1428 if (ret) {
1b3c47c1 1429 dev_err(ctrl->device, "Identify Controller failed (%d)\n", ret);
7fd8930f
CH		 1430 return -EIO;
1431 }
1432
225a9366
AL		 1433 if (!ctrl->identified) {
1434 /*
1435 * Check for quirks. Quirk can depend on firmware version,
1436 * so, in principle, the set of quirks present can change
1437 * across a reset. As a possible future enhancement, we
1438 * could re-scan for quirks every time we reinitialize
1439 * the device, but we'd have to make sure that the driver
1440 * behaves intelligently if the quirks change.
1441 */
1442
1443 int i;
1444
1445 for (i = 0; i < ARRAY_SIZE(core_quirks); i++) {
1446 if (quirk_matches(id, &core_quirks[i]))
1447 ctrl->quirks |= core_quirks[i].quirks;
1448 }
1449 }
1450
118472ab 1451 ctrl->vid = le16_to_cpu(id->vid);
7fd8930f 1452 ctrl->oncs = le16_to_cpup(&id->oncs);
6bf25d16 1453 atomic_set(&ctrl->abort_limit, id->acl + 1);
7fd8930f 1454 ctrl->vwc = id->vwc;
931e1c22 1455 ctrl->cntlid = le16_to_cpup(&id->cntlid);
7fd8930f
CH		 1456 memcpy(ctrl->serial, id->sn, sizeof(id->sn));
1457 memcpy(ctrl->model, id->mn, sizeof(id->mn));
1458 memcpy(ctrl->firmware_rev, id->fr, sizeof(id->fr));
1459 if (id->mdts)
a229dbf6 1460 max_hw_sectors = 1 << (id->mdts + page_shift - 9);
7fd8930f 1461 else
a229dbf6
CH		 1462 max_hw_sectors = UINT_MAX;
1463 ctrl->max_hw_sectors =
1464 min_not_zero(ctrl->max_hw_sectors, max_hw_sectors);
7fd8930f 1465
da35825d 1466 nvme_set_queue_limits(ctrl, ctrl->admin_q);
07bfcd09 1467 ctrl->sgls = le32_to_cpu(id->sgls);
038bd4cb 1468 ctrl->kas = le16_to_cpu(id->kas);
07bfcd09 1469
441d14c0
AL		 1470 ctrl->npss = id->npss;
1471 prev_apsta = ctrl->apsta;
1472 ctrl->apsta = (ctrl->quirks & NVME_QUIRK_NO_APST) ? 0 : id->apsta;
1473 memcpy(ctrl->psd, id->psd, sizeof(ctrl->psd));
1474
07bfcd09
CH		 1475 if (ctrl->ops->is_fabrics) {
1476 ctrl->icdoff = le16_to_cpu(id->icdoff);
1477 ctrl->ioccsz = le32_to_cpu(id->ioccsz);
1478 ctrl->iorcsz = le32_to_cpu(id->iorcsz);
1479 ctrl->maxcmd = le16_to_cpu(id->maxcmd);
1480
1481 /*
1482 * In fabrics we need to verify the cntlid matches the
1483 * admin connect
1484 */
1485 if (ctrl->cntlid != le16_to_cpu(id->cntlid))
1486 ret = -EINVAL;
038bd4cb
SG		 1487
1488 if (!ctrl->opts->discovery_nqn && !ctrl->kas) {
1489 dev_err(ctrl->dev,
1490 "keep-alive support is mandatory for fabrics\n");
1491 ret = -EINVAL;
1492 }
07bfcd09
CH		 1493 } else {
1494 ctrl->cntlid = le16_to_cpu(id->cntlid);
1495 }
da35825d 1496
7fd8930f 1497 kfree(id);
225a9366 1498
441d14c0
AL		 1499 if (ctrl->apsta && !prev_apsta)
1500 dev_pm_qos_expose_latency_tolerance(ctrl->device);
1501 else if (!ctrl->apsta && prev_apsta)
1502 dev_pm_qos_hide_latency_tolerance(ctrl->device);
1503
1504 nvme_configure_apst(ctrl);
1505
225a9366 1506 ctrl->identified = true;
441d14c0 1507
07bfcd09 1508 return ret;
7fd8930f 1509}
576d55d6 1510EXPORT_SYMBOL_GPL(nvme_init_identify);
7fd8930f 1511
f3ca80fc 1512static int nvme_dev_open(struct inode *inode, struct file *file)
1673f1f0 1513{
f3ca80fc
CH		 1514 struct nvme_ctrl *ctrl;
1515 int instance = iminor(inode);
1516 int ret = -ENODEV;
1673f1f0 1517
f3ca80fc
CH		 1518 spin_lock(&dev_list_lock);
1519 list_for_each_entry(ctrl, &nvme_ctrl_list, node) {
1520 if (ctrl->instance != instance)
1521 continue;
1522
1523 if (!ctrl->admin_q) {
1524 ret = -EWOULDBLOCK;
1525 break;
1526 }
1527 if (!kref_get_unless_zero(&ctrl->kref))
1528 break;
1529 file->private_data = ctrl;
1530 ret = 0;
1531 break;
1532 }
1533 spin_unlock(&dev_list_lock);
1534
1535 return ret;
1673f1f0
CH		 1536}
1537
f3ca80fc 1538static int nvme_dev_release(struct inode *inode, struct file *file)
1673f1f0 1539{
f3ca80fc
CH		 1540 nvme_put_ctrl(file->private_data);
1541 return 0;
1542}
1543
bfd89471
CH		 1544static int nvme_dev_user_cmd(struct nvme_ctrl *ctrl, void __user *argp)
1545{
1546 struct nvme_ns *ns;
1547 int ret;
1548
1549 mutex_lock(&ctrl->namespaces_mutex);
1550 if (list_empty(&ctrl->namespaces)) {
1551 ret = -ENOTTY;
1552 goto out_unlock;
1553 }
1554
1555 ns = list_first_entry(&ctrl->namespaces, struct nvme_ns, list);
1556 if (ns != list_last_entry(&ctrl->namespaces, struct nvme_ns, list)) {
1b3c47c1 1557 dev_warn(ctrl->device,
bfd89471
CH		 1558 "NVME_IOCTL_IO_CMD not supported when multiple namespaces present!\n");
1559 ret = -EINVAL;
1560 goto out_unlock;
1561 }
1562
1b3c47c1 1563 dev_warn(ctrl->device,
bfd89471
CH		 1564 "using deprecated NVME_IOCTL_IO_CMD ioctl on the char device!\n");
1565 kref_get(&ns->kref);
1566 mutex_unlock(&ctrl->namespaces_mutex);
1567
1568 ret = nvme_user_cmd(ctrl, ns, argp);
1569 nvme_put_ns(ns);
1570 return ret;
1571
1572out_unlock:
1573 mutex_unlock(&ctrl->namespaces_mutex);
1574 return ret;
1575}
1576
f3ca80fc
CH		 1577static long nvme_dev_ioctl(struct file *file, unsigned int cmd,
1578 unsigned long arg)
1579{
1580 struct nvme_ctrl *ctrl = file->private_data;
1581 void __user *argp = (void __user *)arg;
f3ca80fc
CH		 1582
1583 switch (cmd) {
1584 case NVME_IOCTL_ADMIN_CMD:
1585 return nvme_user_cmd(ctrl, NULL, argp);
1586 case NVME_IOCTL_IO_CMD:
bfd89471 1587 return nvme_dev_user_cmd(ctrl, argp);
f3ca80fc 1588 case NVME_IOCTL_RESET:
1b3c47c1 1589 dev_warn(ctrl->device, "resetting controller\n");
f3ca80fc
CH		 1590 return ctrl->ops->reset_ctrl(ctrl);
1591 case NVME_IOCTL_SUBSYS_RESET:
1592 return nvme_reset_subsystem(ctrl);
9ec3bb2f
KB		 1593 case NVME_IOCTL_RESCAN:
1594 nvme_queue_scan(ctrl);
1595 return 0;
f3ca80fc
CH		 1596 default:
1597 return -ENOTTY;
1598 }
1599}
1600
1601static const struct file_operations nvme_dev_fops = {
1602 .owner = THIS_MODULE,
1603 .open = nvme_dev_open,
1604 .release = nvme_dev_release,
1605 .unlocked_ioctl = nvme_dev_ioctl,
1606 .compat_ioctl = nvme_dev_ioctl,
1607};
1608
1609static ssize_t nvme_sysfs_reset(struct device *dev,
1610 struct device_attribute *attr, const char *buf,
1611 size_t count)
1612{
1613 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
1614 int ret;
1615
1616 ret = ctrl->ops->reset_ctrl(ctrl);
1617 if (ret < 0)
1618 return ret;
1619 return count;
1673f1f0 1620}
f3ca80fc 1621static DEVICE_ATTR(reset_controller, S_IWUSR, NULL, nvme_sysfs_reset);
1673f1f0 1622
9ec3bb2f
KB		 1623static ssize_t nvme_sysfs_rescan(struct device *dev,
1624 struct device_attribute *attr, const char *buf,
1625 size_t count)
1626{
1627 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
1628
1629 nvme_queue_scan(ctrl);
1630 return count;
1631}
1632static DEVICE_ATTR(rescan_controller, S_IWUSR, NULL, nvme_sysfs_rescan);
1633
118472ab
KB		 1634static ssize_t wwid_show(struct device *dev, struct device_attribute *attr,
1635 char *buf)
1636{
40267efd 1637 struct nvme_ns *ns = nvme_get_ns_from_dev(dev);
118472ab
KB		 1638 struct nvme_ctrl *ctrl = ns->ctrl;
1639 int serial_len = sizeof(ctrl->serial);
1640 int model_len = sizeof(ctrl->model);
1641
1642 if (memchr_inv(ns->uuid, 0, sizeof(ns->uuid)))
1643 return sprintf(buf, "eui.%16phN\n", ns->uuid);
1644
1645 if (memchr_inv(ns->eui, 0, sizeof(ns->eui)))
1646 return sprintf(buf, "eui.%8phN\n", ns->eui);
1647
1648 while (ctrl->serial[serial_len - 1] == ' ')
1649 serial_len--;
1650 while (ctrl->model[model_len - 1] == ' ')
1651 model_len--;
1652
1653 return sprintf(buf, "nvme.%04x-%*phN-%*phN-%08x\n", ctrl->vid,
1654 serial_len, ctrl->serial, model_len, ctrl->model, ns->ns_id);
1655}
1656static DEVICE_ATTR(wwid, S_IRUGO, wwid_show, NULL);
1657
2b9b6e86
KB		 1658static ssize_t uuid_show(struct device *dev, struct device_attribute *attr,
1659 char *buf)
1660{
40267efd 1661 struct nvme_ns *ns = nvme_get_ns_from_dev(dev);
2b9b6e86
KB		 1662 return sprintf(buf, "%pU\n", ns->uuid);
1663}
1664static DEVICE_ATTR(uuid, S_IRUGO, uuid_show, NULL);
1665
1666static ssize_t eui_show(struct device *dev, struct device_attribute *attr,
1667 char *buf)
1668{
40267efd 1669 struct nvme_ns *ns = nvme_get_ns_from_dev(dev);
2b9b6e86
KB		 1670 return sprintf(buf, "%8phd\n", ns->eui);
1671}
1672static DEVICE_ATTR(eui, S_IRUGO, eui_show, NULL);
1673
1674static ssize_t nsid_show(struct device *dev, struct device_attribute *attr,
1675 char *buf)
1676{
40267efd 1677 struct nvme_ns *ns = nvme_get_ns_from_dev(dev);
2b9b6e86
KB		 1678 return sprintf(buf, "%d\n", ns->ns_id);
1679}
1680static DEVICE_ATTR(nsid, S_IRUGO, nsid_show, NULL);
1681
1682static struct attribute *nvme_ns_attrs[] = {
118472ab 1683 &dev_attr_wwid.attr,
2b9b6e86
KB		 1684 &dev_attr_uuid.attr,
1685 &dev_attr_eui.attr,
1686 &dev_attr_nsid.attr,
1687 NULL,
1688};
1689
1a353d85 1690static umode_t nvme_ns_attrs_are_visible(struct kobject *kobj,
2b9b6e86
KB		 1691 struct attribute *a, int n)
1692{
1693 struct device *dev = container_of(kobj, struct device, kobj);
40267efd 1694 struct nvme_ns *ns = nvme_get_ns_from_dev(dev);
2b9b6e86
KB		 1695
1696 if (a == &dev_attr_uuid.attr) {
1697 if (!memchr_inv(ns->uuid, 0, sizeof(ns->uuid)))
1698 return 0;
1699 }
1700 if (a == &dev_attr_eui.attr) {
1701 if (!memchr_inv(ns->eui, 0, sizeof(ns->eui)))
1702 return 0;
1703 }
1704 return a->mode;
1705}
1706
1707static const struct attribute_group nvme_ns_attr_group = {
1708 .attrs = nvme_ns_attrs,
1a353d85 1709 .is_visible = nvme_ns_attrs_are_visible,
2b9b6e86
KB		 1710};
1711
931e1c22 1712#define nvme_show_str_function(field) \
779ff756
KB		 1713static ssize_t field##_show(struct device *dev, \
1714 struct device_attribute *attr, char *buf) \
1715{ \
1716 struct nvme_ctrl *ctrl = dev_get_drvdata(dev); \
1717 return sprintf(buf, "%.*s\n", (int)sizeof(ctrl->field), ctrl->field); \
1718} \
1719static DEVICE_ATTR(field, S_IRUGO, field##_show, NULL);
1720
931e1c22
ML		 1721#define nvme_show_int_function(field) \
1722static ssize_t field##_show(struct device *dev, \
1723 struct device_attribute *attr, char *buf) \
1724{ \
1725 struct nvme_ctrl *ctrl = dev_get_drvdata(dev); \
1726 return sprintf(buf, "%d\n", ctrl->field); \
1727} \
1728static DEVICE_ATTR(field, S_IRUGO, field##_show, NULL);
1729
1730nvme_show_str_function(model);
1731nvme_show_str_function(serial);
1732nvme_show_str_function(firmware_rev);
1733nvme_show_int_function(cntlid);
779ff756 1734
1a353d85
ML		 1735static ssize_t nvme_sysfs_delete(struct device *dev,
1736 struct device_attribute *attr, const char *buf,
1737 size_t count)
1738{
1739 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
1740
1741 if (device_remove_file_self(dev, attr))
1742 ctrl->ops->delete_ctrl(ctrl);
1743 return count;
1744}
1745static DEVICE_ATTR(delete_controller, S_IWUSR, NULL, nvme_sysfs_delete);
1746
1747static ssize_t nvme_sysfs_show_transport(struct device *dev,
1748 struct device_attribute *attr,
1749 char *buf)
1750{
1751 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
1752
1753 return snprintf(buf, PAGE_SIZE, "%s\n", ctrl->ops->name);
1754}
1755static DEVICE_ATTR(transport, S_IRUGO, nvme_sysfs_show_transport, NULL);
1756
1757static ssize_t nvme_sysfs_show_subsysnqn(struct device *dev,
1758 struct device_attribute *attr,
1759 char *buf)
1760{
1761 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
1762
1763 return snprintf(buf, PAGE_SIZE, "%s\n",
1764 ctrl->ops->get_subsysnqn(ctrl));
1765}
1766static DEVICE_ATTR(subsysnqn, S_IRUGO, nvme_sysfs_show_subsysnqn, NULL);
1767
1768static ssize_t nvme_sysfs_show_address(struct device *dev,
1769 struct device_attribute *attr,
1770 char *buf)
1771{
1772 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
1773
1774 return ctrl->ops->get_address(ctrl, buf, PAGE_SIZE);
1775}
1776static DEVICE_ATTR(address, S_IRUGO, nvme_sysfs_show_address, NULL);
1777
779ff756
KB		 1778static struct attribute *nvme_dev_attrs[] = {
1779 &dev_attr_reset_controller.attr,
9ec3bb2f 1780 &dev_attr_rescan_controller.attr,
779ff756
KB		 1781 &dev_attr_model.attr,
1782 &dev_attr_serial.attr,
1783 &dev_attr_firmware_rev.attr,
931e1c22 1784 &dev_attr_cntlid.attr,
1a353d85
ML		 1785 &dev_attr_delete_controller.attr,
1786 &dev_attr_transport.attr,
1787 &dev_attr_subsysnqn.attr,
1788 &dev_attr_address.attr,
779ff756
KB		 1789 NULL
1790};
1791
1a353d85
ML		 1792#define CHECK_ATTR(ctrl, a, name) \
1793 if ((a) == &dev_attr_##name.attr && \
1794 !(ctrl)->ops->get_##name) \
1795 return 0
1796
1797static umode_t nvme_dev_attrs_are_visible(struct kobject *kobj,
1798 struct attribute *a, int n)
1799{
1800 struct device *dev = container_of(kobj, struct device, kobj);
1801 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
1802
1803 if (a == &dev_attr_delete_controller.attr) {
1804 if (!ctrl->ops->delete_ctrl)
1805 return 0;
1806 }
1807
1808 CHECK_ATTR(ctrl, a, subsysnqn);
1809 CHECK_ATTR(ctrl, a, address);
1810
1811 return a->mode;
1812}
1813
779ff756 1814static struct attribute_group nvme_dev_attrs_group = {
1a353d85
ML		 1815 .attrs = nvme_dev_attrs,
1816 .is_visible = nvme_dev_attrs_are_visible,
779ff756
KB		 1817};
1818
1819static const struct attribute_group *nvme_dev_attr_groups[] = {
1820 &nvme_dev_attrs_group,
1821 NULL,
1822};
1823
5bae7f73
CH		 1824static int ns_cmp(void *priv, struct list_head *a, struct list_head *b)
1825{
1826 struct nvme_ns *nsa = container_of(a, struct nvme_ns, list);
1827 struct nvme_ns *nsb = container_of(b, struct nvme_ns, list);
1828
1829 return nsa->ns_id - nsb->ns_id;
1830}
1831
32f0c4af 1832static struct nvme_ns *nvme_find_get_ns(struct nvme_ctrl *ctrl, unsigned nsid)
5bae7f73 1833{
32f0c4af 1834 struct nvme_ns *ns, *ret = NULL;
69d3b8ac 1835
32f0c4af 1836 mutex_lock(&ctrl->namespaces_mutex);
5bae7f73 1837 list_for_each_entry(ns, &ctrl->namespaces, list) {
32f0c4af
KB		 1838 if (ns->ns_id == nsid) {
1839 kref_get(&ns->kref);
1840 ret = ns;
1841 break;
1842 }
5bae7f73
CH		 1843 if (ns->ns_id > nsid)
1844 break;
1845 }
32f0c4af
KB		 1846 mutex_unlock(&ctrl->namespaces_mutex);
1847 return ret;
5bae7f73
CH		 1848}
1849
1850static void nvme_alloc_ns(struct nvme_ctrl *ctrl, unsigned nsid)
1851{
1852 struct nvme_ns *ns;
1853 struct gendisk *disk;
ac81bfa9
MB		 1854 struct nvme_id_ns *id;
1855 char disk_name[DISK_NAME_LEN];
5bae7f73
CH		 1856 int node = dev_to_node(ctrl->dev);
1857
1858 ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node);
1859 if (!ns)
1860 return;
1861
075790eb
KB		 1862 ns->instance = ida_simple_get(&ctrl->ns_ida, 1, 0, GFP_KERNEL);
1863 if (ns->instance < 0)
1864 goto out_free_ns;
1865
5bae7f73
CH		 1866 ns->queue = blk_mq_init_queue(ctrl->tagset);
1867 if (IS_ERR(ns->queue))
075790eb 1868 goto out_release_instance;
5bae7f73
CH		 1869 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
1870 ns->queue->queuedata = ns;
1871 ns->ctrl = ctrl;
1872
5bae7f73
CH		 1873 kref_init(&ns->kref);
1874 ns->ns_id = nsid;
5bae7f73 1875 ns->lba_shift = 9; /* set to a default value for 512 until disk is validated */
5bae7f73
CH		 1876
1877 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
da35825d 1878 nvme_set_queue_limits(ctrl, ns->queue);
5bae7f73 1879
ac81bfa9 1880 sprintf(disk_name, "nvme%dn%d", ctrl->instance, ns->instance);
5bae7f73 1881
ac81bfa9
MB		 1882 if (nvme_revalidate_ns(ns, &id))
1883 goto out_free_queue;
1884
3dc87dd0
MB		 1885 if (nvme_nvm_ns_supported(ns, id) &&
1886 nvme_nvm_register(ns, disk_name, node)) {
1887 dev_warn(ctrl->dev, "%s: LightNVM init failure\n", __func__);
1888 goto out_free_id;
1889 }
ac81bfa9 1890
3dc87dd0
MB		 1891 disk = alloc_disk_node(0, node);
1892 if (!disk)
1893 goto out_free_id;
ac81bfa9 1894
3dc87dd0
MB		 1895 disk->fops = &nvme_fops;
1896 disk->private_data = ns;
1897 disk->queue = ns->queue;
1898 disk->flags = GENHD_FL_EXT_DEVT;
1899 memcpy(disk->disk_name, disk_name, DISK_NAME_LEN);
1900 ns->disk = disk;
1901
1902 __nvme_revalidate_disk(disk, id);
5bae7f73 1903
32f0c4af
KB		 1904 mutex_lock(&ctrl->namespaces_mutex);
1905 list_add_tail(&ns->list, &ctrl->namespaces);
1906 mutex_unlock(&ctrl->namespaces_mutex);
1907
5bae7f73 1908 kref_get(&ctrl->kref);
ac81bfa9
MB		 1909
1910 kfree(id);
1911
0d52c756 1912 device_add_disk(ctrl->device, ns->disk);
2b9b6e86
KB		 1913 if (sysfs_create_group(&disk_to_dev(ns->disk)->kobj,
1914 &nvme_ns_attr_group))
1915 pr_warn("%s: failed to create sysfs group for identification\n",
1916 ns->disk->disk_name);
3dc87dd0
MB		 1917 if (ns->ndev && nvme_nvm_register_sysfs(ns))
1918 pr_warn("%s: failed to register lightnvm sysfs group for identification\n",
1919 ns->disk->disk_name);
5bae7f73 1920 return;
ac81bfa9
MB		 1921 out_free_id:
1922 kfree(id);
5bae7f73
CH		 1923 out_free_queue:
1924 blk_cleanup_queue(ns->queue);
075790eb
KB		 1925 out_release_instance:
1926 ida_simple_remove(&ctrl->ns_ida, ns->instance);
5bae7f73
CH		 1927 out_free_ns:
1928 kfree(ns);
1929}
1930
1931static void nvme_ns_remove(struct nvme_ns *ns)
1932{
646017a6
KB		 1933 if (test_and_set_bit(NVME_NS_REMOVING, &ns->flags))
1934 return;
69d3b8ac 1935
b0b4e09c 1936 if (ns->disk && ns->disk->flags & GENHD_FL_UP) {
5bae7f73
CH		 1937 if (blk_get_integrity(ns->disk))
1938 blk_integrity_unregister(ns->disk);
2b9b6e86
KB		 1939 sysfs_remove_group(&disk_to_dev(ns->disk)->kobj,
1940 &nvme_ns_attr_group);
3dc87dd0
MB		 1941 if (ns->ndev)
1942 nvme_nvm_unregister_sysfs(ns);
5bae7f73 1943 del_gendisk(ns->disk);
5bae7f73
CH		 1944 blk_mq_abort_requeue_list(ns->queue);
1945 blk_cleanup_queue(ns->queue);
1946 }
32f0c4af
KB		 1947
1948 mutex_lock(&ns->ctrl->namespaces_mutex);
5bae7f73 1949 list_del_init(&ns->list);
32f0c4af
KB		 1950 mutex_unlock(&ns->ctrl->namespaces_mutex);
1951
5bae7f73
CH		 1952 nvme_put_ns(ns);
1953}
1954
540c801c
KB		 1955static void nvme_validate_ns(struct nvme_ctrl *ctrl, unsigned nsid)
1956{
1957 struct nvme_ns *ns;
1958
32f0c4af 1959 ns = nvme_find_get_ns(ctrl, nsid);
540c801c 1960 if (ns) {
b0b4e09c 1961 if (ns->disk && revalidate_disk(ns->disk))
540c801c 1962 nvme_ns_remove(ns);
32f0c4af 1963 nvme_put_ns(ns);
540c801c
KB		 1964 } else
1965 nvme_alloc_ns(ctrl, nsid);
1966}
1967
47b0e50a
SB		 1968static void nvme_remove_invalid_namespaces(struct nvme_ctrl *ctrl,
1969 unsigned nsid)
1970{
1971 struct nvme_ns *ns, *next;
1972
1973 list_for_each_entry_safe(ns, next, &ctrl->namespaces, list) {
1974 if (ns->ns_id > nsid)
1975 nvme_ns_remove(ns);
1976 }
1977}
1978
540c801c
KB		 1979static int nvme_scan_ns_list(struct nvme_ctrl *ctrl, unsigned nn)
1980{
1981 struct nvme_ns *ns;
1982 __le32 *ns_list;
1983 unsigned i, j, nsid, prev = 0, num_lists = DIV_ROUND_UP(nn, 1024);
1984 int ret = 0;
1985
1986 ns_list = kzalloc(0x1000, GFP_KERNEL);
1987 if (!ns_list)
1988 return -ENOMEM;
1989
1990 for (i = 0; i < num_lists; i++) {
1991 ret = nvme_identify_ns_list(ctrl, prev, ns_list);
1992 if (ret)
47b0e50a 1993 goto free;
540c801c
KB		 1994
1995 for (j = 0; j < min(nn, 1024U); j++) {
1996 nsid = le32_to_cpu(ns_list[j]);
1997 if (!nsid)
1998 goto out;
1999
2000 nvme_validate_ns(ctrl, nsid);
2001
2002 while (++prev < nsid) {
32f0c4af
KB		 2003 ns = nvme_find_get_ns(ctrl, prev);
2004 if (ns) {
540c801c 2005 nvme_ns_remove(ns);
32f0c4af
KB		 2006 nvme_put_ns(ns);
2007 }
540c801c
KB		 2008 }
2009 }
2010 nn -= j;
2011 }
2012 out:
47b0e50a
SB		 2013 nvme_remove_invalid_namespaces(ctrl, prev);
2014 free:
540c801c
KB		 2015 kfree(ns_list);
2016 return ret;
2017}
2018
5955be21 2019static void nvme_scan_ns_sequential(struct nvme_ctrl *ctrl, unsigned nn)
5bae7f73 2020{
5bae7f73
CH		 2021 unsigned i;
2022
540c801c
KB		 2023 for (i = 1; i <= nn; i++)
2024 nvme_validate_ns(ctrl, i);
2025
47b0e50a 2026 nvme_remove_invalid_namespaces(ctrl, nn);
5bae7f73
CH		 2027}
2028
5955be21 2029static void nvme_scan_work(struct work_struct *work)
5bae7f73 2030{
5955be21
CH		 2031 struct nvme_ctrl *ctrl =
2032 container_of(work, struct nvme_ctrl, scan_work);
5bae7f73 2033 struct nvme_id_ctrl *id;
540c801c 2034 unsigned nn;
5bae7f73 2035
5955be21
CH		 2036 if (ctrl->state != NVME_CTRL_LIVE)
2037 return;
2038
5bae7f73
CH		 2039 if (nvme_identify_ctrl(ctrl, &id))
2040 return;
540c801c
KB		 2041
2042 nn = le32_to_cpu(id->nn);
8ef2074d 2043 if (ctrl->vs >= NVME_VS(1, 1, 0) &&
540c801c
KB		 2044 !(ctrl->quirks & NVME_QUIRK_IDENTIFY_CNS)) {
2045 if (!nvme_scan_ns_list(ctrl, nn))
2046 goto done;
2047 }
5955be21 2048 nvme_scan_ns_sequential(ctrl, nn);
540c801c 2049 done:
32f0c4af 2050 mutex_lock(&ctrl->namespaces_mutex);
540c801c 2051 list_sort(NULL, &ctrl->namespaces, ns_cmp);
69d3b8ac 2052 mutex_unlock(&ctrl->namespaces_mutex);
5bae7f73
CH		 2053 kfree(id);
2054}
5955be21
CH		 2055
2056void nvme_queue_scan(struct nvme_ctrl *ctrl)
2057{
2058 /*
2059 * Do not queue new scan work when a controller is reset during
2060 * removal.
2061 */
2062 if (ctrl->state == NVME_CTRL_LIVE)
2063 schedule_work(&ctrl->scan_work);
2064}
2065EXPORT_SYMBOL_GPL(nvme_queue_scan);
5bae7f73 2066
32f0c4af
KB		 2067/*
2068 * This function iterates the namespace list unlocked to allow recovery from
2069 * controller failure. It is up to the caller to ensure the namespace list is
2070 * not modified by scan work while this function is executing.
2071 */
5bae7f73
CH		 2072void nvme_remove_namespaces(struct nvme_ctrl *ctrl)
2073{
2074 struct nvme_ns *ns, *next;
2075
0ff9d4e1
KB		 2076 /*
2077 * The dead states indicates the controller was not gracefully
2078 * disconnected. In that case, we won't be able to flush any data while
2079 * removing the namespaces' disks; fail all the queues now to avoid
2080 * potentially having to clean up the failed sync later.
2081 */
2082 if (ctrl->state == NVME_CTRL_DEAD)
2083 nvme_kill_queues(ctrl);
2084
5bae7f73
CH		 2085 list_for_each_entry_safe(ns, next, &ctrl->namespaces, list)
2086 nvme_ns_remove(ns);
2087}
576d55d6 2088EXPORT_SYMBOL_GPL(nvme_remove_namespaces);
5bae7f73 2089
f866fc42
CH		 2090static void nvme_async_event_work(struct work_struct *work)
2091{
2092 struct nvme_ctrl *ctrl =
2093 container_of(work, struct nvme_ctrl, async_event_work);
2094
2095 spin_lock_irq(&ctrl->lock);
2096 while (ctrl->event_limit > 0) {
2097 int aer_idx = --ctrl->event_limit;
2098
2099 spin_unlock_irq(&ctrl->lock);
2100 ctrl->ops->submit_async_event(ctrl, aer_idx);
2101 spin_lock_irq(&ctrl->lock);
2102 }
2103 spin_unlock_irq(&ctrl->lock);
2104}
2105
7bf58533
CH		 2106void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status,
2107 union nvme_result *res)
f866fc42 2108{
7bf58533
CH		 2109 u32 result = le32_to_cpu(res->u32);
2110 bool done = true;
f866fc42 2111
7bf58533
CH		 2112 switch (le16_to_cpu(status) >> 1) {
2113 case NVME_SC_SUCCESS:
2114 done = false;
2115 /*FALLTHRU*/
2116 case NVME_SC_ABORT_REQ:
f866fc42
CH		 2117 ++ctrl->event_limit;
2118 schedule_work(&ctrl->async_event_work);
7bf58533
CH		 2119 break;
2120 default:
2121 break;
f866fc42
CH		 2122 }
2123
7bf58533 2124 if (done)
f866fc42
CH		 2125 return;
2126
2127 switch (result & 0xff07) {
2128 case NVME_AER_NOTICE_NS_CHANGED:
2129 dev_info(ctrl->device, "rescanning\n");
2130 nvme_queue_scan(ctrl);
2131 break;
2132 default:
2133 dev_warn(ctrl->device, "async event result %08x\n", result);
2134 }
2135}
2136EXPORT_SYMBOL_GPL(nvme_complete_async_event);
2137
2138void nvme_queue_async_events(struct nvme_ctrl *ctrl)
2139{
2140 ctrl->event_limit = NVME_NR_AERS;
2141 schedule_work(&ctrl->async_event_work);
2142}
2143EXPORT_SYMBOL_GPL(nvme_queue_async_events);
2144
f3ca80fc
CH		 2145static DEFINE_IDA(nvme_instance_ida);
2146
2147static int nvme_set_instance(struct nvme_ctrl *ctrl)
2148{
2149 int instance, error;
2150
2151 do {
2152 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
2153 return -ENODEV;
2154
2155 spin_lock(&dev_list_lock);
2156 error = ida_get_new(&nvme_instance_ida, &instance);
2157 spin_unlock(&dev_list_lock);
2158 } while (error == -EAGAIN);
2159
2160 if (error)
2161 return -ENODEV;
2162
2163 ctrl->instance = instance;
2164 return 0;
2165}
2166
2167static void nvme_release_instance(struct nvme_ctrl *ctrl)
2168{
2169 spin_lock(&dev_list_lock);
2170 ida_remove(&nvme_instance_ida, ctrl->instance);
2171 spin_unlock(&dev_list_lock);
2172}
2173
53029b04 2174void nvme_uninit_ctrl(struct nvme_ctrl *ctrl)
576d55d6 2175{
f866fc42 2176 flush_work(&ctrl->async_event_work);
5955be21
CH		 2177 flush_work(&ctrl->scan_work);
2178 nvme_remove_namespaces(ctrl);
2179
53029b04 2180 device_destroy(nvme_class, MKDEV(nvme_char_major, ctrl->instance));
f3ca80fc
CH		 2181
2182 spin_lock(&dev_list_lock);
2183 list_del(&ctrl->node);
2184 spin_unlock(&dev_list_lock);
53029b04 2185}
576d55d6 2186EXPORT_SYMBOL_GPL(nvme_uninit_ctrl);
53029b04
KB		 2187
2188static void nvme_free_ctrl(struct kref *kref)
2189{
2190 struct nvme_ctrl *ctrl = container_of(kref, struct nvme_ctrl, kref);
f3ca80fc
CH		 2191
2192 put_device(ctrl->device);
2193 nvme_release_instance(ctrl);
075790eb 2194 ida_destroy(&ctrl->ns_ida);
f3ca80fc
CH		 2195
2196 ctrl->ops->free_ctrl(ctrl);
2197}
2198
2199void nvme_put_ctrl(struct nvme_ctrl *ctrl)
2200{
2201 kref_put(&ctrl->kref, nvme_free_ctrl);
2202}
576d55d6 2203EXPORT_SYMBOL_GPL(nvme_put_ctrl);
f3ca80fc
CH		 2204
2205/*
2206 * Initialize a NVMe controller structures. This needs to be called during
2207 * earliest initialization so that we have the initialized structured around
2208 * during probing.
2209 */
2210int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev,
2211 const struct nvme_ctrl_ops *ops, unsigned long quirks)
2212{
2213 int ret;
2214
bb8d261e
CH		 2215 ctrl->state = NVME_CTRL_NEW;
2216 spin_lock_init(&ctrl->lock);
f3ca80fc 2217 INIT_LIST_HEAD(&ctrl->namespaces);
69d3b8ac 2218 mutex_init(&ctrl->namespaces_mutex);
f3ca80fc
CH		 2219 kref_init(&ctrl->kref);
2220 ctrl->dev = dev;
2221 ctrl->ops = ops;
2222 ctrl->quirks = quirks;
5955be21 2223 INIT_WORK(&ctrl->scan_work, nvme_scan_work);
f866fc42 2224 INIT_WORK(&ctrl->async_event_work, nvme_async_event_work);
f3ca80fc
CH		 2225
2226 ret = nvme_set_instance(ctrl);
2227 if (ret)
2228 goto out;
2229
779ff756 2230 ctrl->device = device_create_with_groups(nvme_class, ctrl->dev,
f3ca80fc 2231 MKDEV(nvme_char_major, ctrl->instance),
f4f0f63e 2232 ctrl, nvme_dev_attr_groups,
779ff756 2233 "nvme%d", ctrl->instance);
f3ca80fc
CH		 2234 if (IS_ERR(ctrl->device)) {
2235 ret = PTR_ERR(ctrl->device);
2236 goto out_release_instance;
2237 }
2238 get_device(ctrl->device);
075790eb 2239 ida_init(&ctrl->ns_ida);
f3ca80fc 2240
f3ca80fc
CH		 2241 spin_lock(&dev_list_lock);
2242 list_add_tail(&ctrl->node, &nvme_ctrl_list);
2243 spin_unlock(&dev_list_lock);
2244
441d14c0
AL		 2245 /*
2246 * Initialize latency tolerance controls. The sysfs files won't
2247 * be visible to userspace unless the device actually supports APST.
2248 */
2249 ctrl->device->power.set_latency_tolerance = nvme_set_latency_tolerance;
2250 dev_pm_qos_update_user_latency_tolerance(ctrl->device,
2251 min(default_ps_max_latency_us, (unsigned long)S32_MAX));
2252
f3ca80fc 2253 return 0;
f3ca80fc
CH		 2254out_release_instance:
2255 nvme_release_instance(ctrl);
2256out:
2257 return ret;
2258}
576d55d6 2259EXPORT_SYMBOL_GPL(nvme_init_ctrl);
f3ca80fc 2260
69d9a99c
KB		 2261/**
2262 * nvme_kill_queues(): Ends all namespace queues
2263 * @ctrl: the dead controller that needs to end
2264 *
2265 * Call this function when the driver determines it is unable to get the
2266 * controller in a state capable of servicing IO.
2267 */
2268void nvme_kill_queues(struct nvme_ctrl *ctrl)
2269{
2270 struct nvme_ns *ns;
2271
32f0c4af
KB		 2272 mutex_lock(&ctrl->namespaces_mutex);
2273 list_for_each_entry(ns, &ctrl->namespaces, list) {
69d9a99c
KB		 2274 /*
2275 * Revalidating a dead namespace sets capacity to 0. This will
2276 * end buffered writers dirtying pages that can't be synced.
2277 */
398e4464
KB		 2278 if (!ns->disk || test_and_set_bit(NVME_NS_DEAD, &ns->flags))
2279 continue;
2280 revalidate_disk(ns->disk);
69d9a99c
KB		 2281 blk_set_queue_dying(ns->queue);
2282 blk_mq_abort_requeue_list(ns->queue);
2283 blk_mq_start_stopped_hw_queues(ns->queue, true);
69d9a99c 2284 }
32f0c4af 2285 mutex_unlock(&ctrl->namespaces_mutex);
69d9a99c 2286}
237045fc 2287EXPORT_SYMBOL_GPL(nvme_kill_queues);
69d9a99c 2288
25646264 2289void nvme_stop_queues(struct nvme_ctrl *ctrl)
363c9aac
SG		 2290{
2291 struct nvme_ns *ns;
2292
32f0c4af 2293 mutex_lock(&ctrl->namespaces_mutex);
a6eaa884 2294 list_for_each_entry(ns, &ctrl->namespaces, list)
3174dd33 2295 blk_mq_quiesce_queue(ns->queue);
32f0c4af 2296 mutex_unlock(&ctrl->namespaces_mutex);
363c9aac 2297}
576d55d6 2298EXPORT_SYMBOL_GPL(nvme_stop_queues);
363c9aac 2299
25646264 2300void nvme_start_queues(struct nvme_ctrl *ctrl)
363c9aac
SG		 2301{
2302 struct nvme_ns *ns;
2303
32f0c4af
KB		 2304 mutex_lock(&ctrl->namespaces_mutex);
2305 list_for_each_entry(ns, &ctrl->namespaces, list) {
363c9aac
SG		 2306 blk_mq_start_stopped_hw_queues(ns->queue, true);
2307 blk_mq_kick_requeue_list(ns->queue);
2308 }
32f0c4af 2309 mutex_unlock(&ctrl->namespaces_mutex);
363c9aac 2310}
576d55d6 2311EXPORT_SYMBOL_GPL(nvme_start_queues);
363c9aac 2312
5bae7f73
CH		 2313int __init nvme_core_init(void)
2314{
2315 int result;
2316
f3ca80fc
CH		 2317 result = __register_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme",
2318 &nvme_dev_fops);
2319 if (result < 0)
b09dcf58 2320 return result;
f3ca80fc
CH		 2321 else if (result > 0)
2322 nvme_char_major = result;
2323
2324 nvme_class = class_create(THIS_MODULE, "nvme");
2325 if (IS_ERR(nvme_class)) {
2326 result = PTR_ERR(nvme_class);
2327 goto unregister_chrdev;
2328 }
2329
5bae7f73 2330 return 0;
f3ca80fc
CH		 2331
2332 unregister_chrdev:
2333 __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
f3ca80fc 2334 return result;
5bae7f73
CH		 2335}
2336
2337void nvme_core_exit(void)
2338{
f3ca80fc
CH		 2339 class_destroy(nvme_class);
2340 __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
5bae7f73 2341}
576d55d6
ML		 2342
2343MODULE_LICENSE("GPL");
2344MODULE_VERSION("1.0");
2345module_init(nvme_core_init);
2346module_exit(nvme_core_exit);
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