[mirror_ubuntu-zesty-kernel.git] / drivers / scsi / cxlflash / common.h

/*
 * CXL Flash Device Driver
 *
 * Written by: Manoj N. Kumar <manoj@linux.vnet.ibm.com>, IBM Corporation
 *             Matthew R. Ochs <mrochs@linux.vnet.ibm.com>, IBM Corporation
 *
 * Copyright (C) 2015 IBM Corporation
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */

#ifndef _CXLFLASH_COMMON_H
#define _CXLFLASH_COMMON_H

#include <linux/irq_poll.h>
#include <linux/list.h>
#include <linux/rwsem.h>
#include <linux/types.h>
#include <scsi/scsi.h>
#include <scsi/scsi_cmnd.h>
#include <scsi/scsi_device.h>

extern const struct file_operations cxlflash_cxl_fops;

#define MAX_CONTEXT	CXLFLASH_MAX_CONTEXT	/* num contexts per afu */
#define MAX_FC_PORTS	CXLFLASH_MAX_FC_PORTS	/* max ports per AFU */
#define LEGACY_FC_PORTS	2			/* legacy ports per AFU */

#define CHAN2PORTBANK(_x)	((_x) >> ilog2(CXLFLASH_NUM_FC_PORTS_PER_BANK))
#define CHAN2BANKPORT(_x)	((_x) & (CXLFLASH_NUM_FC_PORTS_PER_BANK - 1))

#define CHAN2PORTMASK(_x)	(1 << (_x))	/* channel to port mask */
#define PORTMASK2CHAN(_x)	(ilog2((_x)))	/* port mask to channel */
#define PORTNUM2CHAN(_x)	((_x) - 1)	/* port number to channel */

#define CXLFLASH_BLOCK_SIZE	4096	/* 4K blocks */
#define CXLFLASH_MAX_XFER_SIZE	16777216	/* 16MB transfer */
#define CXLFLASH_MAX_SECTORS	(CXLFLASH_MAX_XFER_SIZE/512)	/* SCSI wants
								   max_sectors
								   in units of
								   512 byte
								   sectors
								*/

#define MAX_RHT_PER_CONTEXT (PAGE_SIZE / sizeof(struct sisl_rht_entry))

/* AFU command retry limit */
#define MC_RETRY_CNT         5	/* sufficient for SCSI check and
				   certain AFU errors */

/* Command management definitions */
#define CXLFLASH_NUM_CMDS	(2 * CXLFLASH_MAX_CMDS)	/* Must be a pow2 for
							   alignment and more
							   efficient array
							   index derivation
							 */

#define CXLFLASH_MAX_CMDS               256
#define CXLFLASH_MAX_CMDS_PER_LUN       CXLFLASH_MAX_CMDS

/* RRQ for master issued cmds */
#define NUM_RRQ_ENTRY                   CXLFLASH_MAX_CMDS

/* SQ for master issued cmds */
#define NUM_SQ_ENTRY			CXLFLASH_MAX_CMDS


static inline void check_sizes(void)
{
	BUILD_BUG_ON_NOT_POWER_OF_2(CXLFLASH_NUM_FC_PORTS_PER_BANK);
}

/* AFU defines a fixed size of 4K for command buffers (borrow 4K page define) */
#define CMD_BUFSIZE     SIZE_4K

enum cxlflash_lr_state {
	LINK_RESET_INVALID,
	LINK_RESET_REQUIRED,
	LINK_RESET_COMPLETE
};

enum cxlflash_init_state {
	INIT_STATE_NONE,
	INIT_STATE_PCI,
	INIT_STATE_AFU,
	INIT_STATE_SCSI
};

enum cxlflash_state {
	STATE_NORMAL,	/* Normal running state, everything good */
	STATE_RESET,	/* Reset state, trying to reset/recover */
	STATE_FAILTERM	/* Failed/terminating state, error out users/threads */
};

/*
 * Each context has its own set of resource handles that is visible
 * only from that context.
 */

struct cxlflash_cfg {
	struct afu *afu;
	struct cxl_context *mcctx;

	struct pci_dev *dev;
	struct pci_device_id *dev_id;
	struct Scsi_Host *host;
	int num_fc_ports;

	ulong cxlflash_regs_pci;

	struct work_struct work_q;
	enum cxlflash_init_state init_state;
	enum cxlflash_lr_state lr_state;
	int lr_port;
	atomic_t scan_host_needed;

	struct cxl_afu *cxl_afu;

	atomic_t recovery_threads;
	struct mutex ctx_recovery_mutex;
	struct mutex ctx_tbl_list_mutex;
	struct rw_semaphore ioctl_rwsem;
	struct ctx_info *ctx_tbl[MAX_CONTEXT];
	struct list_head ctx_err_recovery; /* contexts w/ recovery pending */
	struct file_operations cxl_fops;

	/* Parameters that are LUN table related */
	int last_lun_index[MAX_FC_PORTS];
	int promote_lun_index;
	struct list_head lluns; /* list of llun_info structs */

	wait_queue_head_t tmf_waitq;
	spinlock_t tmf_slock;
	bool tmf_active;
	wait_queue_head_t reset_waitq;
	enum cxlflash_state state;
};

struct afu_cmd {
	struct sisl_ioarcb rcb;	/* IOARCB (cache line aligned) */
	struct sisl_ioasa sa;	/* IOASA must follow IOARCB */
	struct afu *parent;
	struct scsi_cmnd *scp;
	struct completion cevent;
	struct list_head queue;

	u8 cmd_tmf:1;

	/* As per the SISLITE spec the IOARCB EA has to be 16-byte aligned.
	 * However for performance reasons the IOARCB/IOASA should be
	 * cache line aligned.
	 */
} __aligned(cache_line_size());

static inline struct afu_cmd *sc_to_afuc(struct scsi_cmnd *sc)
{
	return PTR_ALIGN(scsi_cmd_priv(sc), __alignof__(struct afu_cmd));
}

static inline struct afu_cmd *sc_to_afucz(struct scsi_cmnd *sc)
{
	struct afu_cmd *afuc = sc_to_afuc(sc);

	memset(afuc, 0, sizeof(*afuc));
	return afuc;
}

struct afu {
	/* Stuff requiring alignment go first. */
	struct sisl_ioarcb sq[NUM_SQ_ENTRY];		/* 16K SQ */
	u64 rrq_entry[NUM_RRQ_ENTRY];			/* 2K RRQ */

	/* Beware of alignment till here. Preferably introduce new
	 * fields after this point
	 */

	int (*send_cmd)(struct afu *, struct afu_cmd *);
	void (*context_reset)(struct afu_cmd *);

	/* AFU HW */
	struct cxl_ioctl_start_work work;
	struct cxlflash_afu_map __iomem *afu_map;	/* entire MMIO map */
	struct sisl_host_map __iomem *host_map;		/* MC host map */
	struct sisl_ctrl_map __iomem *ctrl_map;		/* MC control map */

	ctx_hndl_t ctx_hndl;	/* master's context handle */

	atomic_t hsq_credits;
	spinlock_t hsq_slock;
	struct sisl_ioarcb *hsq_start;
	struct sisl_ioarcb *hsq_end;
	struct sisl_ioarcb *hsq_curr;
	spinlock_t hrrq_slock;
	u64 *hrrq_start;
	u64 *hrrq_end;
	u64 *hrrq_curr;
	bool toggle;
	atomic_t cmds_active;	/* Number of currently active AFU commands */
	s64 room;
	spinlock_t rrin_slock; /* Lock to rrin queuing and cmd_room updates */
	u64 hb;
	u32 internal_lun;	/* User-desired LUN mode for this AFU */

	char version[16];
	u64 interface_version;

	u32 irqpoll_weight;
	struct irq_poll irqpoll;
	struct cxlflash_cfg *parent; /* Pointer back to parent cxlflash_cfg */

};

static inline bool afu_is_irqpoll_enabled(struct afu *afu)
{
	return !!afu->irqpoll_weight;
}

static inline bool afu_is_cmd_mode(struct afu *afu, u64 cmd_mode)
{
	u64 afu_cap = afu->interface_version >> SISL_INTVER_CAP_SHIFT;

	return afu_cap & cmd_mode;
}

static inline bool afu_is_sq_cmd_mode(struct afu *afu)
{
	return afu_is_cmd_mode(afu, SISL_INTVER_CAP_SQ_CMD_MODE);
}

static inline bool afu_is_ioarrin_cmd_mode(struct afu *afu)
{
	return afu_is_cmd_mode(afu, SISL_INTVER_CAP_IOARRIN_CMD_MODE);
}

static inline u64 lun_to_lunid(u64 lun)
{
	__be64 lun_id;

	int_to_scsilun(lun, (struct scsi_lun *)&lun_id);
	return be64_to_cpu(lun_id);
}

static inline struct fc_port_bank __iomem *get_fc_port_bank(
					    struct cxlflash_cfg *cfg, int i)
{
	struct afu *afu = cfg->afu;

	return &afu->afu_map->global.bank[CHAN2PORTBANK(i)];
}

static inline __be64 __iomem *get_fc_port_regs(struct cxlflash_cfg *cfg, int i)
{
	struct fc_port_bank __iomem *fcpb = get_fc_port_bank(cfg, i);

	return &fcpb->fc_port_regs[CHAN2BANKPORT(i)][0];
}

static inline __be64 __iomem *get_fc_port_luns(struct cxlflash_cfg *cfg, int i)
{
	struct fc_port_bank __iomem *fcpb = get_fc_port_bank(cfg, i);

	return &fcpb->fc_port_luns[CHAN2BANKPORT(i)][0];
}

int cxlflash_afu_sync(struct afu *, ctx_hndl_t, res_hndl_t, u8);
void cxlflash_list_init(void);
void cxlflash_term_global_luns(void);
void cxlflash_free_errpage(void);
int cxlflash_ioctl(struct scsi_device *, int, void __user *);
void cxlflash_stop_term_user_contexts(struct cxlflash_cfg *);
int cxlflash_mark_contexts_error(struct cxlflash_cfg *);
void cxlflash_term_local_luns(struct cxlflash_cfg *);
void cxlflash_restore_luntable(struct cxlflash_cfg *);

#endif /* ifndef _CXLFLASH_COMMON_H */
Commit	Line	Data
c21e0bbf MO	1	/*
	2	* CXL Flash Device Driver
	3	*
	4	* Written by: Manoj N. Kumar <manoj@linux.vnet.ibm.com>, IBM Corporation
	5	* Matthew R. Ochs <mrochs@linux.vnet.ibm.com>, IBM Corporation
	6	*
	7	* Copyright (C) 2015 IBM Corporation
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License
	11	* as published by the Free Software Foundation; either version
	12	* 2 of the License, or (at your option) any later version.
	13	*/
	14
	15	#ifndef _CXLFLASH_COMMON_H
	16	#define _CXLFLASH_COMMON_H
	17
2588f222	18	#include <linux/irq_poll.h>
c21e0bbf	19	#include <linux/list.h>
0a27ae51	20	#include <linux/rwsem.h>
c21e0bbf MO	21	#include <linux/types.h>
c21e0bbf MO	22	#include <scsi/scsi.h>
5fbb96c8	23	#include <scsi/scsi_cmnd.h>
c21e0bbf MO	24	#include <scsi/scsi_device.h>
c21e0bbf MO	25
17ead26f	26	extern const struct file_operations cxlflash_cxl_fops;
c21e0bbf	27
66d4bce4	28	#define MAX_CONTEXT CXLFLASH_MAX_CONTEXT /* num contexts per afu */
a290b480 MO	29	#define MAX_FC_PORTS CXLFLASH_MAX_FC_PORTS /* max ports per AFU */
	30	#define LEGACY_FC_PORTS 2 /* legacy ports per AFU */
	31
	32	#define CHAN2PORTBANK(_x) ((_x) >> ilog2(CXLFLASH_NUM_FC_PORTS_PER_BANK))
	33	#define CHAN2BANKPORT(_x) ((_x) & (CXLFLASH_NUM_FC_PORTS_PER_BANK - 1))
c21e0bbf	34
e8e17ea6 MO	35	#define CHAN2PORTMASK(_x) (1 << (_x)) /* channel to port mask */
	36	#define PORTMASK2CHAN(_x) (ilog2((_x))) /* port mask to channel */
	37	#define PORTNUM2CHAN(_x) ((_x) - 1) /* port number to channel */
	38
c21e0bbf MO	39	#define CXLFLASH_BLOCK_SIZE 4096 /* 4K blocks */
	40	#define CXLFLASH_MAX_XFER_SIZE 16777216 /* 16MB transfer */
	41	#define CXLFLASH_MAX_SECTORS (CXLFLASH_MAX_XFER_SIZE/512) /* SCSI wants
	42	max_sectors
	43	in units of
	44	512 byte
	45	sectors
	46	*/
	47
c21e0bbf MO	48	#define MAX_RHT_PER_CONTEXT (PAGE_SIZE / sizeof(struct sisl_rht_entry))
	49
	50	/* AFU command retry limit */
	51	#define MC_RETRY_CNT 5 /* sufficient for SCSI check and
	52	certain AFU errors */
	53
	54	/* Command management definitions */
	55	#define CXLFLASH_NUM_CMDS (2 * CXLFLASH_MAX_CMDS) /* Must be a pow2 for
	56	alignment and more
	57	efficient array
	58	index derivation
	59	*/
	60
83430833	61	#define CXLFLASH_MAX_CMDS 256
c21e0bbf MO	62	#define CXLFLASH_MAX_CMDS_PER_LUN CXLFLASH_MAX_CMDS
c21e0bbf MO	63
83430833 MK	64	/* RRQ for master issued cmds */
	65	#define NUM_RRQ_ENTRY CXLFLASH_MAX_CMDS
	66
bae0ac69 MO	67	/* SQ for master issued cmds */
	68	#define NUM_SQ_ENTRY CXLFLASH_MAX_CMDS
	69
c21e0bbf MO	70
	71	static inline void check_sizes(void)
	72	{
a290b480	73	BUILD_BUG_ON_NOT_POWER_OF_2(CXLFLASH_NUM_FC_PORTS_PER_BANK);
c21e0bbf MO	74	}
	75
	76	/* AFU defines a fixed size of 4K for command buffers (borrow 4K page define) */
	77	#define CMD_BUFSIZE SIZE_4K
	78
c21e0bbf MO	79	enum cxlflash_lr_state {
	80	LINK_RESET_INVALID,
	81	LINK_RESET_REQUIRED,
	82	LINK_RESET_COMPLETE
	83	};
	84
	85	enum cxlflash_init_state {
	86	INIT_STATE_NONE,
	87	INIT_STATE_PCI,
	88	INIT_STATE_AFU,
	89	INIT_STATE_SCSI
	90	};
	91
5cdac81a MO	92	enum cxlflash_state {
5cdac81a MO	93	STATE_NORMAL, /* Normal running state, everything good */
439e85c1	94	STATE_RESET, /* Reset state, trying to reset/recover */
5cdac81a MO	95	STATE_FAILTERM /* Failed/terminating state, error out users/threads */
	96	};
	97
c21e0bbf MO	98	/*
	99	* Each context has its own set of resource handles that is visible
	100	* only from that context.
	101	*/
	102
	103	struct cxlflash_cfg {
	104	struct afu *afu;
	105	struct cxl_context *mcctx;
	106
	107	struct pci_dev *dev;
	108	struct pci_device_id *dev_id;
	109	struct Scsi_Host *host;
66d4bce4	110	int num_fc_ports;
c21e0bbf MO	111
	112	ulong cxlflash_regs_pci;
	113
c21e0bbf MO	114	struct work_struct work_q;
	115	enum cxlflash_init_state init_state;
	116	enum cxlflash_lr_state lr_state;
	117	int lr_port;
ef51074a	118	atomic_t scan_host_needed;
c21e0bbf MO	119
c21e0bbf MO	120	struct cxl_afu *cxl_afu;
c21e0bbf	121
65be2c79 MO	122	atomic_t recovery_threads;
	123	struct mutex ctx_recovery_mutex;
	124	struct mutex ctx_tbl_list_mutex;
0a27ae51	125	struct rw_semaphore ioctl_rwsem;
65be2c79 MO	126	struct ctx_info *ctx_tbl[MAX_CONTEXT];
	127	struct list_head ctx_err_recovery; /* contexts w/ recovery pending */
	128	struct file_operations cxl_fops;
	129
2cb79266	130	/* Parameters that are LUN table related */
66d4bce4	131	int last_lun_index[MAX_FC_PORTS];
2cb79266	132	int promote_lun_index;
65be2c79 MO	133	struct list_head lluns; /* list of llun_info structs */
65be2c79 MO	134
c21e0bbf	135	wait_queue_head_t tmf_waitq;
018d1dc9	136	spinlock_t tmf_slock;
c21e0bbf	137	bool tmf_active;
439e85c1	138	wait_queue_head_t reset_waitq;
5cdac81a	139	enum cxlflash_state state;
c21e0bbf MO	140	};
	141
	142	struct afu_cmd {
	143	struct sisl_ioarcb rcb; /* IOARCB (cache line aligned) */
	144	struct sisl_ioasa sa; /* IOASA must follow IOARCB */
c21e0bbf	145	struct afu *parent;
fe7f9698	146	struct scsi_cmnd *scp;
9ba848ac	147	struct completion cevent;
7bb512aa	148	struct list_head queue;
c21e0bbf MO	149
	150	u8 cmd_tmf:1;
	151
	152	/* As per the SISLITE spec the IOARCB EA has to be 16-byte aligned.
	153	* However for performance reasons the IOARCB/IOASA should be
	154	* cache line aligned.
	155	*/
	156	} __aligned(cache_line_size());
	157
5fbb96c8 MO	158	static inline struct afu_cmd sc_to_afuc(struct scsi_cmnd sc)
	159	{
	160	return PTR_ALIGN(scsi_cmd_priv(sc), __alignof__(struct afu_cmd));
	161	}
	162
	163	static inline struct afu_cmd sc_to_afucz(struct scsi_cmnd sc)
	164	{
	165	struct afu_cmd *afuc = sc_to_afuc(sc);
	166
	167	memset(afuc, 0, sizeof(*afuc));
	168	return afuc;
	169	}
	170
c21e0bbf MO	171	struct afu {
c21e0bbf MO	172	/* Stuff requiring alignment go first. */
bae0ac69 MO	173	struct sisl_ioarcb sq[NUM_SQ_ENTRY]; /* 16K SQ */
bae0ac69 MO	174	u64 rrq_entry[NUM_RRQ_ENTRY]; /* 2K RRQ */
c21e0bbf MO	175
	176	/* Beware of alignment till here. Preferably introduce new
	177	* fields after this point
	178	*/
	179
48b4be36 MO	180	int (send_cmd)(struct afu , struct afu_cmd *);
	181	void (context_reset)(struct afu_cmd );
	182
c21e0bbf MO	183	/* AFU HW */
c21e0bbf MO	184	struct cxl_ioctl_start_work work;
1786f4a0 MO	185	struct cxlflash_afu_map __iomem afu_map; / entire MMIO map */
	186	struct sisl_host_map __iomem host_map; / MC host map */
	187	struct sisl_ctrl_map __iomem ctrl_map; / MC control map */
c21e0bbf MO	188
c21e0bbf MO	189	ctx_hndl_t ctx_hndl; /* master's context handle */
bae0ac69 MO	190
	191	atomic_t hsq_credits;
	192	spinlock_t hsq_slock;
	193	struct sisl_ioarcb *hsq_start;
	194	struct sisl_ioarcb *hsq_end;
	195	struct sisl_ioarcb *hsq_curr;
7bb512aa	196	spinlock_t hrrq_slock;
c21e0bbf MO	197	u64 *hrrq_start;
	198	u64 *hrrq_end;
	199	u64 *hrrq_curr;
	200	bool toggle;
de01283b	201	atomic_t cmds_active; /* Number of currently active AFU commands */
11f7b184 UK	202	s64 room;
11f7b184 UK	203	spinlock_t rrin_slock; /* Lock to rrin queuing and cmd_room updates */
c21e0bbf	204	u64 hb;
c21e0bbf MO	205	u32 internal_lun; /* User-desired LUN mode for this AFU */
c21e0bbf MO	206
e5ce067b	207	char version[16];
c21e0bbf MO	208	u64 interface_version;
c21e0bbf MO	209
2588f222 MO	210	u32 irqpoll_weight;
2588f222 MO	211	struct irq_poll irqpoll;
c21e0bbf MO	212	struct cxlflash_cfg parent; / Pointer back to parent cxlflash_cfg */
	213
	214	};
	215
2588f222 MO	216	static inline bool afu_is_irqpoll_enabled(struct afu *afu)
	217	{
	218	return !!afu->irqpoll_weight;
	219	}
	220
bae0ac69 MO	221	static inline bool afu_is_cmd_mode(struct afu *afu, u64 cmd_mode)
	222	{
	223	u64 afu_cap = afu->interface_version >> SISL_INTVER_CAP_SHIFT;
	224
	225	return afu_cap & cmd_mode;
	226	}
	227
	228	static inline bool afu_is_sq_cmd_mode(struct afu *afu)
	229	{
	230	return afu_is_cmd_mode(afu, SISL_INTVER_CAP_SQ_CMD_MODE);
	231	}
	232
	233	static inline bool afu_is_ioarrin_cmd_mode(struct afu *afu)
	234	{
	235	return afu_is_cmd_mode(afu, SISL_INTVER_CAP_IOARRIN_CMD_MODE);
	236	}
	237
c21e0bbf MO	238	static inline u64 lun_to_lunid(u64 lun)
c21e0bbf MO	239	{
1786f4a0	240	__be64 lun_id;
c21e0bbf MO	241
c21e0bbf MO	242	int_to_scsilun(lun, (struct scsi_lun *)&lun_id);
1786f4a0	243	return be64_to_cpu(lun_id);
c21e0bbf MO	244	}
c21e0bbf MO	245
a290b480 MO	246	static inline struct fc_port_bank __iomem *get_fc_port_bank(
a290b480 MO	247	struct cxlflash_cfg *cfg, int i)
c885d3fe MO	248	{
	249	struct afu *afu = cfg->afu;
	250
a290b480 MO	251	return &afu->afu_map->global.bank[CHAN2PORTBANK(i)];
	252	}
	253
	254	static inline __be64 __iomem get_fc_port_regs(struct cxlflash_cfg cfg, int i)
	255	{
	256	struct fc_port_bank __iomem *fcpb = get_fc_port_bank(cfg, i);
	257
	258	return &fcpb->fc_port_regs[CHAN2BANKPORT(i)][0];
c885d3fe MO	259	}
	260
	261	static inline __be64 __iomem get_fc_port_luns(struct cxlflash_cfg cfg, int i)
	262	{
a290b480	263	struct fc_port_bank __iomem *fcpb = get_fc_port_bank(cfg, i);
c885d3fe	264
a290b480	265	return &fcpb->fc_port_luns[CHAN2BANKPORT(i)][0];
c885d3fe MO	266	}
c885d3fe MO	267
c21e0bbf	268	int cxlflash_afu_sync(struct afu *, ctx_hndl_t, res_hndl_t, u8);
65be2c79 MO	269	void cxlflash_list_init(void);
	270	void cxlflash_term_global_luns(void);
	271	void cxlflash_free_errpage(void);
	272	int cxlflash_ioctl(struct scsi_device , int, void __user );
	273	void cxlflash_stop_term_user_contexts(struct cxlflash_cfg *);
	274	int cxlflash_mark_contexts_error(struct cxlflash_cfg *);
	275	void cxlflash_term_local_luns(struct cxlflash_cfg *);
2cb79266	276	void cxlflash_restore_luntable(struct cxlflash_cfg *);
65be2c79	277
c21e0bbf	278	#endif /* ifndef _CXLFLASH_COMMON_H */