[mirror_ubuntu-zesty-kernel.git] / drivers / scsi / cxlflash / common.h

/*
 * CXL Flash Device Driver
 *
 * Written by: Manoj N. Kumar <manoj@linux.vnet.ibm.com>, IBM Corporation
 *             Matthew R. Ochs <mrochs@linux.vnet.ibm.com>, IBM Corporation
 *
 * Copyright (C) 2015 IBM Corporation
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */

#ifndef _CXLFLASH_COMMON_H
#define _CXLFLASH_COMMON_H

#include <linux/irq_poll.h>
#include <linux/list.h>
#include <linux/rwsem.h>
#include <linux/types.h>
#include <scsi/scsi.h>
#include <scsi/scsi_cmnd.h>
#include <scsi/scsi_device.h>

extern const struct file_operations cxlflash_cxl_fops;

#define MAX_CONTEXT	CXLFLASH_MAX_CONTEXT	/* num contexts per afu */
#define MAX_FC_PORTS	CXLFLASH_MAX_FC_PORTS	/* max ports per AFU */
#define LEGACY_FC_PORTS	2			/* legacy ports per AFU */

#define CHAN2PORTBANK(_x)	((_x) >> ilog2(CXLFLASH_NUM_FC_PORTS_PER_BANK))
#define CHAN2BANKPORT(_x)	((_x) & (CXLFLASH_NUM_FC_PORTS_PER_BANK - 1))

#define CHAN2PORTMASK(_x)	(1 << (_x))	/* channel to port mask */
#define PORTMASK2CHAN(_x)	(ilog2((_x)))	/* port mask to channel */
#define PORTNUM2CHAN(_x)	((_x) - 1)	/* port number to channel */

#define CXLFLASH_BLOCK_SIZE	4096		/* 4K blocks */
#define CXLFLASH_MAX_XFER_SIZE	16777216	/* 16MB transfer */
#define CXLFLASH_MAX_SECTORS	(CXLFLASH_MAX_XFER_SIZE/512)	/* SCSI wants
								 * max_sectors
								 * in units of
								 * 512 byte
								 * sectors
								 */

#define MAX_RHT_PER_CONTEXT (PAGE_SIZE / sizeof(struct sisl_rht_entry))

/* AFU command retry limit */
#define MC_RETRY_CNT	5	/* Sufficient for SCSI and certain AFU errors */

/* Command management definitions */
#define CXLFLASH_MAX_CMDS               256
#define CXLFLASH_MAX_CMDS_PER_LUN       CXLFLASH_MAX_CMDS

/* RRQ for master issued cmds */
#define NUM_RRQ_ENTRY                   CXLFLASH_MAX_CMDS

/* SQ for master issued cmds */
#define NUM_SQ_ENTRY			CXLFLASH_MAX_CMDS

/* Hardware queue definitions */
#define CXLFLASH_DEF_HWQS		1
#define CXLFLASH_MAX_HWQS		8
#define PRIMARY_HWQ			0


static inline void check_sizes(void)
{
	BUILD_BUG_ON_NOT_POWER_OF_2(CXLFLASH_NUM_FC_PORTS_PER_BANK);
	BUILD_BUG_ON_NOT_POWER_OF_2(CXLFLASH_MAX_CMDS);
}

/* AFU defines a fixed size of 4K for command buffers (borrow 4K page define) */
#define CMD_BUFSIZE     SIZE_4K

enum cxlflash_lr_state {
	LINK_RESET_INVALID,
	LINK_RESET_REQUIRED,
	LINK_RESET_COMPLETE
};

enum cxlflash_init_state {
	INIT_STATE_NONE,
	INIT_STATE_PCI,
	INIT_STATE_AFU,
	INIT_STATE_SCSI
};

enum cxlflash_state {
	STATE_PROBING,	/* Initial state during probe */
	STATE_PROBED,	/* Temporary state, probe completed but EEH occurred */
	STATE_NORMAL,	/* Normal running state, everything good */
	STATE_RESET,	/* Reset state, trying to reset/recover */
	STATE_FAILTERM	/* Failed/terminating state, error out users/threads */
};

/*
 * Each context has its own set of resource handles that is visible
 * only from that context.
 */

struct cxlflash_cfg {
	struct afu *afu;

	struct pci_dev *dev;
	struct pci_device_id *dev_id;
	struct Scsi_Host *host;
	int num_fc_ports;

	ulong cxlflash_regs_pci;

	struct work_struct work_q;
	enum cxlflash_init_state init_state;
	enum cxlflash_lr_state lr_state;
	int lr_port;
	atomic_t scan_host_needed;

	struct cxl_afu *cxl_afu;

	atomic_t recovery_threads;
	struct mutex ctx_recovery_mutex;
	struct mutex ctx_tbl_list_mutex;
	struct rw_semaphore ioctl_rwsem;
	struct ctx_info *ctx_tbl[MAX_CONTEXT];
	struct list_head ctx_err_recovery; /* contexts w/ recovery pending */
	struct file_operations cxl_fops;

	/* Parameters that are LUN table related */
	int last_lun_index[MAX_FC_PORTS];
	int promote_lun_index;
	struct list_head lluns; /* list of llun_info structs */

	wait_queue_head_t tmf_waitq;
	spinlock_t tmf_slock;
	bool tmf_active;
	wait_queue_head_t reset_waitq;
	enum cxlflash_state state;
};

struct afu_cmd {
	struct sisl_ioarcb rcb;	/* IOARCB (cache line aligned) */
	struct sisl_ioasa sa;	/* IOASA must follow IOARCB */
	struct afu *parent;
	struct scsi_cmnd *scp;
	struct completion cevent;
	struct list_head queue;

	u8 cmd_tmf:1;
	u32 hwq_index;

	/* As per the SISLITE spec the IOARCB EA has to be 16-byte aligned.
	 * However for performance reasons the IOARCB/IOASA should be
	 * cache line aligned.
	 */
} __aligned(cache_line_size());

static inline struct afu_cmd *sc_to_afuc(struct scsi_cmnd *sc)
{
	return PTR_ALIGN(scsi_cmd_priv(sc), __alignof__(struct afu_cmd));
}

static inline struct afu_cmd *sc_to_afucz(struct scsi_cmnd *sc)
{
	struct afu_cmd *afuc = sc_to_afuc(sc);

	memset(afuc, 0, sizeof(*afuc));
	return afuc;
}

struct hwq {
	/* Stuff requiring alignment go first. */
	struct sisl_ioarcb sq[NUM_SQ_ENTRY];		/* 16K SQ */
	u64 rrq_entry[NUM_RRQ_ENTRY];			/* 2K RRQ */

	/* Beware of alignment till here. Preferably introduce new
	 * fields after this point
	 */
	struct afu *afu;
	struct cxl_context *ctx;
	struct cxl_ioctl_start_work work;
	struct sisl_host_map __iomem *host_map;		/* MC host map */
	struct sisl_ctrl_map __iomem *ctrl_map;		/* MC control map */
	ctx_hndl_t ctx_hndl;	/* master's context handle */
	u32 index;		/* Index of this hwq */

	atomic_t hsq_credits;
	spinlock_t hsq_slock;
	struct sisl_ioarcb *hsq_start;
	struct sisl_ioarcb *hsq_end;
	struct sisl_ioarcb *hsq_curr;
	spinlock_t hrrq_slock;
	u64 *hrrq_start;
	u64 *hrrq_end;
	u64 *hrrq_curr;
	bool toggle;

	s64 room;
	spinlock_t rrin_slock; /* Lock to rrin queuing and cmd_room updates */

	struct irq_poll irqpoll;
} __aligned(cache_line_size());

struct afu {
	struct hwq hwqs[CXLFLASH_MAX_HWQS];
	int (*send_cmd)(struct afu *, struct afu_cmd *);
	void (*context_reset)(struct afu_cmd *);

	/* AFU HW */
	struct cxlflash_afu_map __iomem *afu_map;	/* entire MMIO map */

	atomic_t cmds_active;	/* Number of currently active AFU commands */
	u64 hb;
	u32 internal_lun;	/* User-desired LUN mode for this AFU */
	u32 num_hwqs;		/* Number of hardware queues */
	u32 desired_hwqs;	/* Desired h/w queues, effective on AFU reset */

	char version[16];
	u64 interface_version;

	u32 irqpoll_weight;
	struct cxlflash_cfg *parent; /* Pointer back to parent cxlflash_cfg */
};

static inline struct hwq *get_hwq(struct afu *afu, u32 index)
{
	WARN_ON(index >= CXLFLASH_MAX_HWQS);

	return &afu->hwqs[index];
}

static inline bool afu_is_irqpoll_enabled(struct afu *afu)
{
	return !!afu->irqpoll_weight;
}

static inline bool afu_is_cmd_mode(struct afu *afu, u64 cmd_mode)
{
	u64 afu_cap = afu->interface_version >> SISL_INTVER_CAP_SHIFT;

	return afu_cap & cmd_mode;
}

static inline bool afu_is_sq_cmd_mode(struct afu *afu)
{
	return afu_is_cmd_mode(afu, SISL_INTVER_CAP_SQ_CMD_MODE);
}

static inline bool afu_is_ioarrin_cmd_mode(struct afu *afu)
{
	return afu_is_cmd_mode(afu, SISL_INTVER_CAP_IOARRIN_CMD_MODE);
}

static inline u64 lun_to_lunid(u64 lun)
{
	__be64 lun_id;

	int_to_scsilun(lun, (struct scsi_lun *)&lun_id);
	return be64_to_cpu(lun_id);
}

static inline struct fc_port_bank __iomem *get_fc_port_bank(
					    struct cxlflash_cfg *cfg, int i)
{
	struct afu *afu = cfg->afu;

	return &afu->afu_map->global.bank[CHAN2PORTBANK(i)];
}

static inline __be64 __iomem *get_fc_port_regs(struct cxlflash_cfg *cfg, int i)
{
	struct fc_port_bank __iomem *fcpb = get_fc_port_bank(cfg, i);

	return &fcpb->fc_port_regs[CHAN2BANKPORT(i)][0];
}

static inline __be64 __iomem *get_fc_port_luns(struct cxlflash_cfg *cfg, int i)
{
	struct fc_port_bank __iomem *fcpb = get_fc_port_bank(cfg, i);

	return &fcpb->fc_port_luns[CHAN2BANKPORT(i)][0];
}

int cxlflash_afu_sync(struct afu *afu, ctx_hndl_t c, res_hndl_t r, u8 mode);
void cxlflash_list_init(void);
void cxlflash_term_global_luns(void);
void cxlflash_free_errpage(void);
int cxlflash_ioctl(struct scsi_device *sdev, int cmd, void __user *arg);
void cxlflash_stop_term_user_contexts(struct cxlflash_cfg *cfg);
int cxlflash_mark_contexts_error(struct cxlflash_cfg *cfg);
void cxlflash_term_local_luns(struct cxlflash_cfg *cfg);
void cxlflash_restore_luntable(struct cxlflash_cfg *cfg);

#endif /* ifndef _CXLFLASH_COMMON_H */
Commit	Line	Data
c21e0bbf MO	1	/*
	2	* CXL Flash Device Driver
	3	*
	4	* Written by: Manoj N. Kumar <manoj@linux.vnet.ibm.com>, IBM Corporation
	5	* Matthew R. Ochs <mrochs@linux.vnet.ibm.com>, IBM Corporation
	6	*
	7	* Copyright (C) 2015 IBM Corporation
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License
	11	* as published by the Free Software Foundation; either version
	12	* 2 of the License, or (at your option) any later version.
	13	*/
	14
	15	#ifndef _CXLFLASH_COMMON_H
	16	#define _CXLFLASH_COMMON_H
	17
2588f222	18	#include <linux/irq_poll.h>
c21e0bbf	19	#include <linux/list.h>
0a27ae51	20	#include <linux/rwsem.h>
c21e0bbf MO	21	#include <linux/types.h>
c21e0bbf MO	22	#include <scsi/scsi.h>
5fbb96c8	23	#include <scsi/scsi_cmnd.h>
c21e0bbf MO	24	#include <scsi/scsi_device.h>
c21e0bbf MO	25
17ead26f	26	extern const struct file_operations cxlflash_cxl_fops;
c21e0bbf	27
66d4bce4	28	#define MAX_CONTEXT CXLFLASH_MAX_CONTEXT /* num contexts per afu */
a290b480 MO	29	#define MAX_FC_PORTS CXLFLASH_MAX_FC_PORTS /* max ports per AFU */
	30	#define LEGACY_FC_PORTS 2 /* legacy ports per AFU */
	31
	32	#define CHAN2PORTBANK(_x) ((_x) >> ilog2(CXLFLASH_NUM_FC_PORTS_PER_BANK))
	33	#define CHAN2BANKPORT(_x) ((_x) & (CXLFLASH_NUM_FC_PORTS_PER_BANK - 1))
c21e0bbf	34
e8e17ea6 MO	35	#define CHAN2PORTMASK(_x) (1 << (_x)) /* channel to port mask */
	36	#define PORTMASK2CHAN(_x) (ilog2((_x))) /* port mask to channel */
	37	#define PORTNUM2CHAN(_x) ((_x) - 1) /* port number to channel */
	38
39e9d618	39	#define CXLFLASH_BLOCK_SIZE 4096 /* 4K blocks */
c21e0bbf MO	40	#define CXLFLASH_MAX_XFER_SIZE 16777216 /* 16MB transfer */
c21e0bbf MO	41	#define CXLFLASH_MAX_SECTORS (CXLFLASH_MAX_XFER_SIZE/512) /* SCSI wants
39e9d618 MO	42	* max_sectors
	43	* in units of
	44	* 512 byte
	45	* sectors
	46	*/
c21e0bbf	47
c21e0bbf MO	48	#define MAX_RHT_PER_CONTEXT (PAGE_SIZE / sizeof(struct sisl_rht_entry))
	49
	50	/* AFU command retry limit */
39e9d618	51	#define MC_RETRY_CNT 5 /* Sufficient for SCSI and certain AFU errors */
c21e0bbf MO	52
c21e0bbf MO	53	/* Command management definitions */
83430833	54	#define CXLFLASH_MAX_CMDS 256
c21e0bbf MO	55	#define CXLFLASH_MAX_CMDS_PER_LUN CXLFLASH_MAX_CMDS
c21e0bbf MO	56
83430833 MK	57	/* RRQ for master issued cmds */
	58	#define NUM_RRQ_ENTRY CXLFLASH_MAX_CMDS
	59
bae0ac69 MO	60	/* SQ for master issued cmds */
	61	#define NUM_SQ_ENTRY CXLFLASH_MAX_CMDS
	62
bb85ef68 MO	63	/* Hardware queue definitions */
	64	#define CXLFLASH_DEF_HWQS 1
	65	#define CXLFLASH_MAX_HWQS 8
a583d00a UK	66	#define PRIMARY_HWQ 0
a583d00a UK	67
c21e0bbf MO	68
	69	static inline void check_sizes(void)
	70	{
a290b480	71	BUILD_BUG_ON_NOT_POWER_OF_2(CXLFLASH_NUM_FC_PORTS_PER_BANK);
db853d50	72	BUILD_BUG_ON_NOT_POWER_OF_2(CXLFLASH_MAX_CMDS);
c21e0bbf MO	73	}
	74
	75	/* AFU defines a fixed size of 4K for command buffers (borrow 4K page define) */
	76	#define CMD_BUFSIZE SIZE_4K
	77
c21e0bbf MO	78	enum cxlflash_lr_state {
	79	LINK_RESET_INVALID,
	80	LINK_RESET_REQUIRED,
	81	LINK_RESET_COMPLETE
	82	};
	83
	84	enum cxlflash_init_state {
	85	INIT_STATE_NONE,
	86	INIT_STATE_PCI,
	87	INIT_STATE_AFU,
	88	INIT_STATE_SCSI
	89	};
	90
5cdac81a	91	enum cxlflash_state {
f92ba507 MO	92	STATE_PROBING, /* Initial state during probe */
f92ba507 MO	93	STATE_PROBED, /* Temporary state, probe completed but EEH occurred */
5cdac81a	94	STATE_NORMAL, /* Normal running state, everything good */
439e85c1	95	STATE_RESET, /* Reset state, trying to reset/recover */
5cdac81a MO	96	STATE_FAILTERM /* Failed/terminating state, error out users/threads */
	97	};
	98
c21e0bbf MO	99	/*
	100	* Each context has its own set of resource handles that is visible
	101	* only from that context.
	102	*/
	103
	104	struct cxlflash_cfg {
	105	struct afu *afu;
c21e0bbf MO	106
	107	struct pci_dev *dev;
	108	struct pci_device_id *dev_id;
	109	struct Scsi_Host *host;
66d4bce4	110	int num_fc_ports;
c21e0bbf MO	111
	112	ulong cxlflash_regs_pci;
	113
c21e0bbf MO	114	struct work_struct work_q;
	115	enum cxlflash_init_state init_state;
	116	enum cxlflash_lr_state lr_state;
	117	int lr_port;
ef51074a	118	atomic_t scan_host_needed;
c21e0bbf MO	119
c21e0bbf MO	120	struct cxl_afu *cxl_afu;
c21e0bbf	121
65be2c79 MO	122	atomic_t recovery_threads;
	123	struct mutex ctx_recovery_mutex;
	124	struct mutex ctx_tbl_list_mutex;
0a27ae51	125	struct rw_semaphore ioctl_rwsem;
65be2c79 MO	126	struct ctx_info *ctx_tbl[MAX_CONTEXT];
	127	struct list_head ctx_err_recovery; /* contexts w/ recovery pending */
	128	struct file_operations cxl_fops;
	129
2cb79266	130	/* Parameters that are LUN table related */
66d4bce4	131	int last_lun_index[MAX_FC_PORTS];
2cb79266	132	int promote_lun_index;
65be2c79 MO	133	struct list_head lluns; /* list of llun_info structs */
65be2c79 MO	134
c21e0bbf	135	wait_queue_head_t tmf_waitq;
018d1dc9	136	spinlock_t tmf_slock;
c21e0bbf	137	bool tmf_active;
439e85c1	138	wait_queue_head_t reset_waitq;
5cdac81a	139	enum cxlflash_state state;
c21e0bbf MO	140	};
	141
	142	struct afu_cmd {
	143	struct sisl_ioarcb rcb; /* IOARCB (cache line aligned) */
	144	struct sisl_ioasa sa; /* IOASA must follow IOARCB */
c21e0bbf	145	struct afu *parent;
fe7f9698	146	struct scsi_cmnd *scp;
9ba848ac	147	struct completion cevent;
7bb512aa	148	struct list_head queue;
c21e0bbf MO	149
c21e0bbf MO	150	u8 cmd_tmf:1;
a583d00a	151	u32 hwq_index;
c21e0bbf MO	152
	153	/* As per the SISLITE spec the IOARCB EA has to be 16-byte aligned.
	154	* However for performance reasons the IOARCB/IOASA should be
	155	* cache line aligned.
	156	*/
	157	} __aligned(cache_line_size());
	158
5fbb96c8 MO	159	static inline struct afu_cmd sc_to_afuc(struct scsi_cmnd sc)
	160	{
	161	return PTR_ALIGN(scsi_cmd_priv(sc), __alignof__(struct afu_cmd));
	162	}
	163
	164	static inline struct afu_cmd sc_to_afucz(struct scsi_cmnd sc)
	165	{
	166	struct afu_cmd *afuc = sc_to_afuc(sc);
	167
	168	memset(afuc, 0, sizeof(*afuc));
	169	return afuc;
	170	}
	171
a583d00a	172	struct hwq {
c21e0bbf	173	/* Stuff requiring alignment go first. */
bae0ac69 MO	174	struct sisl_ioarcb sq[NUM_SQ_ENTRY]; /* 16K SQ */
bae0ac69 MO	175	u64 rrq_entry[NUM_RRQ_ENTRY]; /* 2K RRQ */
c21e0bbf MO	176
	177	/* Beware of alignment till here. Preferably introduce new
	178	* fields after this point
	179	*/
a583d00a UK	180	struct afu *afu;
a583d00a UK	181	struct cxl_context *ctx;
c21e0bbf	182	struct cxl_ioctl_start_work work;
1786f4a0 MO	183	struct sisl_host_map __iomem host_map; / MC host map */
1786f4a0 MO	184	struct sisl_ctrl_map __iomem ctrl_map; / MC control map */
c21e0bbf	185	ctx_hndl_t ctx_hndl; /* master's context handle */
a583d00a	186	u32 index; /* Index of this hwq */
bae0ac69 MO	187
	188	atomic_t hsq_credits;
	189	spinlock_t hsq_slock;
	190	struct sisl_ioarcb *hsq_start;
	191	struct sisl_ioarcb *hsq_end;
	192	struct sisl_ioarcb *hsq_curr;
7bb512aa	193	spinlock_t hrrq_slock;
c21e0bbf MO	194	u64 *hrrq_start;
	195	u64 *hrrq_end;
	196	u64 *hrrq_curr;
	197	bool toggle;
a583d00a	198
11f7b184 UK	199	s64 room;
11f7b184 UK	200	spinlock_t rrin_slock; /* Lock to rrin queuing and cmd_room updates */
a583d00a UK	201
	202	struct irq_poll irqpoll;
	203	} __aligned(cache_line_size());
	204
	205	struct afu {
bb85ef68	206	struct hwq hwqs[CXLFLASH_MAX_HWQS];
a583d00a UK	207	int (send_cmd)(struct afu , struct afu_cmd *);
	208	void (context_reset)(struct afu_cmd );
	209
	210	/* AFU HW */
	211	struct cxlflash_afu_map __iomem afu_map; / entire MMIO map */
	212
	213	atomic_t cmds_active; /* Number of currently active AFU commands */
c21e0bbf	214	u64 hb;
c21e0bbf	215	u32 internal_lun; /* User-desired LUN mode for this AFU */
bb85ef68 MO	216	u32 num_hwqs; /* Number of hardware queues */
bb85ef68 MO	217	u32 desired_hwqs; /* Desired h/w queues, effective on AFU reset */
c21e0bbf	218
e5ce067b	219	char version[16];
c21e0bbf MO	220	u64 interface_version;
c21e0bbf MO	221
2588f222	222	u32 irqpoll_weight;
c21e0bbf	223	struct cxlflash_cfg parent; / Pointer back to parent cxlflash_cfg */
c21e0bbf MO	224	};
c21e0bbf MO	225
a583d00a UK	226	static inline struct hwq get_hwq(struct afu afu, u32 index)
a583d00a UK	227	{
bb85ef68	228	WARN_ON(index >= CXLFLASH_MAX_HWQS);
a583d00a UK	229
	230	return &afu->hwqs[index];
	231	}
	232
2588f222 MO	233	static inline bool afu_is_irqpoll_enabled(struct afu *afu)
	234	{
	235	return !!afu->irqpoll_weight;
	236	}
	237
bae0ac69 MO	238	static inline bool afu_is_cmd_mode(struct afu *afu, u64 cmd_mode)
	239	{
	240	u64 afu_cap = afu->interface_version >> SISL_INTVER_CAP_SHIFT;
	241
	242	return afu_cap & cmd_mode;
	243	}
	244
	245	static inline bool afu_is_sq_cmd_mode(struct afu *afu)
	246	{
	247	return afu_is_cmd_mode(afu, SISL_INTVER_CAP_SQ_CMD_MODE);
	248	}
	249
	250	static inline bool afu_is_ioarrin_cmd_mode(struct afu *afu)
	251	{
	252	return afu_is_cmd_mode(afu, SISL_INTVER_CAP_IOARRIN_CMD_MODE);
	253	}
	254
c21e0bbf MO	255	static inline u64 lun_to_lunid(u64 lun)
c21e0bbf MO	256	{
1786f4a0	257	__be64 lun_id;
c21e0bbf MO	258
c21e0bbf MO	259	int_to_scsilun(lun, (struct scsi_lun *)&lun_id);
1786f4a0	260	return be64_to_cpu(lun_id);
c21e0bbf MO	261	}
c21e0bbf MO	262
a290b480 MO	263	static inline struct fc_port_bank __iomem *get_fc_port_bank(
a290b480 MO	264	struct cxlflash_cfg *cfg, int i)
c885d3fe MO	265	{
	266	struct afu *afu = cfg->afu;
	267
a290b480 MO	268	return &afu->afu_map->global.bank[CHAN2PORTBANK(i)];
	269	}
	270
	271	static inline __be64 __iomem get_fc_port_regs(struct cxlflash_cfg cfg, int i)
	272	{
	273	struct fc_port_bank __iomem *fcpb = get_fc_port_bank(cfg, i);
	274
	275	return &fcpb->fc_port_regs[CHAN2BANKPORT(i)][0];
c885d3fe MO	276	}
	277
	278	static inline __be64 __iomem get_fc_port_luns(struct cxlflash_cfg cfg, int i)
	279	{
a290b480	280	struct fc_port_bank __iomem *fcpb = get_fc_port_bank(cfg, i);
c885d3fe	281
a290b480	282	return &fcpb->fc_port_luns[CHAN2BANKPORT(i)][0];
c885d3fe MO	283	}
c885d3fe MO	284
39e9d618	285	int cxlflash_afu_sync(struct afu *afu, ctx_hndl_t c, res_hndl_t r, u8 mode);
65be2c79 MO	286	void cxlflash_list_init(void);
	287	void cxlflash_term_global_luns(void);
	288	void cxlflash_free_errpage(void);
39e9d618 MO	289	int cxlflash_ioctl(struct scsi_device sdev, int cmd, void __user arg);
	290	void cxlflash_stop_term_user_contexts(struct cxlflash_cfg *cfg);
	291	int cxlflash_mark_contexts_error(struct cxlflash_cfg *cfg);
	292	void cxlflash_term_local_luns(struct cxlflash_cfg *cfg);
	293	void cxlflash_restore_luntable(struct cxlflash_cfg *cfg);
65be2c79	294
c21e0bbf	295	#endif /* ifndef _CXLFLASH_COMMON_H */