KVM: arm64: vgic-v3: Add ICV_CTLR_EL1 handler

[mirror_ubuntu-zesty-kernel.git] / virt / kvm / arm / hyp / vgic-v3-sr.c

diff --git a/virt/kvm/arm/hyp/vgic-v3-sr.c b/virt/kvm/arm/hyp/vgic-v3-sr.c
index 36272a12c19d03afd8a549a6019ed73800ce64df..d8c5a09b1f5852ed9001ba750c7679c8e5d77bdf 100644 (file)
--- a/virt/kvm/arm/hyp/vgic-v3-sr.c
+++ b/virt/kvm/arm/hyp/vgic-v3-sr.c
@@ -701,6 +701,30 @@ static void __hyp_text __vgic_v3_bump_eoicount(void)
        write_gicreg(hcr, ICH_HCR_EL2);
 }
 
+static void __hyp_text __vgic_v3_write_dir(struct kvm_vcpu *vcpu,
+                                          u32 vmcr, int rt)
+{
+       u32 vid = vcpu_get_reg(vcpu, rt);
+       u64 lr_val;
+       int lr;
+
+       /* EOImode == 0, nothing to be done here */
+       if (!(vmcr & ICH_VMCR_EOIM_MASK))
+               return;
+
+       /* No deactivate to be performed on an LPI */
+       if (vid >= VGIC_MIN_LPI)
+               return;
+
+       lr = __vgic_v3_find_active_lr(vcpu, vid, &lr_val);
+       if (lr == -1) {
+               __vgic_v3_bump_eoicount();
+               return;
+       }
+
+       __vgic_v3_clear_active_lr(lr, lr_val);
+}
+
 static void __hyp_text __vgic_v3_write_eoir(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
 {
        u32 vid = vcpu_get_reg(vcpu, rt);
@@ -738,11 +762,28 @@ static void __hyp_text __vgic_v3_write_eoir(struct kvm_vcpu *vcpu, u32 vmcr, int
        __vgic_v3_clear_active_lr(lr, lr_val);
 }
 
+static void __hyp_text __vgic_v3_read_igrpen0(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
+{
+       vcpu_set_reg(vcpu, rt, !!(vmcr & ICH_VMCR_ENG0_MASK));
+}
+
 static void __hyp_text __vgic_v3_read_igrpen1(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
 {
        vcpu_set_reg(vcpu, rt, !!(vmcr & ICH_VMCR_ENG1_MASK));
 }
 
+static void __hyp_text __vgic_v3_write_igrpen0(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
+{
+       u64 val = vcpu_get_reg(vcpu, rt);
+
+       if (val & 1)
+               vmcr |= ICH_VMCR_ENG0_MASK;
+       else
+               vmcr &= ~ICH_VMCR_ENG0_MASK;
+
+       __vgic_v3_write_vmcr(vmcr);
+}
+
 static void __hyp_text __vgic_v3_write_igrpen1(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
 {
        u64 val = vcpu_get_reg(vcpu, rt);
@@ -755,11 +796,33 @@ static void __hyp_text __vgic_v3_write_igrpen1(struct kvm_vcpu *vcpu, u32 vmcr,
        __vgic_v3_write_vmcr(vmcr);
 }
 
+static void __hyp_text __vgic_v3_read_bpr0(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
+{
+       vcpu_set_reg(vcpu, rt, __vgic_v3_get_bpr0(vmcr));
+}
+
 static void __hyp_text __vgic_v3_read_bpr1(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
 {
        vcpu_set_reg(vcpu, rt, __vgic_v3_get_bpr1(vmcr));
 }
 
+static void __hyp_text __vgic_v3_write_bpr0(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
+{
+       u64 val = vcpu_get_reg(vcpu, rt);
+       u8 bpr_min = __vgic_v3_bpr_min() - 1;
+
+       /* Enforce BPR limiting */
+       if (val < bpr_min)
+               val = bpr_min;
+
+       val <<= ICH_VMCR_BPR0_SHIFT;
+       val &= ICH_VMCR_BPR0_MASK;
+       vmcr &= ~ICH_VMCR_BPR0_MASK;
+       vmcr |= val;
+
+       __vgic_v3_write_vmcr(vmcr);
+}
+
 static void __hyp_text __vgic_v3_write_bpr1(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
 {
        u64 val = vcpu_get_reg(vcpu, rt);
@@ -870,6 +933,53 @@ spurious:
        vcpu_set_reg(vcpu, rt, lr_val & ICH_LR_VIRTUAL_ID_MASK);
 }
 
+static void __hyp_text __vgic_v3_read_rpr(struct kvm_vcpu *vcpu,
+                                         u32 vmcr, int rt)
+{
+       u32 val = __vgic_v3_get_highest_active_priority();
+       vcpu_set_reg(vcpu, rt, val);
+}
+
+static void __hyp_text __vgic_v3_read_ctlr(struct kvm_vcpu *vcpu,
+                                          u32 vmcr, int rt)
+{
+       u32 vtr, val;
+
+       vtr = read_gicreg(ICH_VTR_EL2);
+       /* PRIbits */
+       val = ((vtr >> 29) & 7) << ICC_CTLR_EL1_PRI_BITS_SHIFT;
+       /* IDbits */
+       val |= ((vtr >> 23) & 7) << ICC_CTLR_EL1_ID_BITS_SHIFT;
+       /* SEIS */
+       val |= ((vtr >> 22) & 1) << ICC_CTLR_EL1_SEIS_SHIFT;
+       /* A3V */
+       val |= ((vtr >> 21) & 1) << ICC_CTLR_EL1_A3V_SHIFT;
+       /* EOImode */
+       val |= ((vmcr & ICH_VMCR_EOIM_MASK) >> ICH_VMCR_EOIM_SHIFT) << ICC_CTLR_EL1_EOImode_SHIFT;
+       /* CBPR */
+       val |= (vmcr & ICH_VMCR_CBPR_MASK) >> ICH_VMCR_CBPR_SHIFT;
+
+       vcpu_set_reg(vcpu, rt, val);
+}
+
+static void __hyp_text __vgic_v3_write_ctlr(struct kvm_vcpu *vcpu,
+                                           u32 vmcr, int rt)
+{
+       u32 val = vcpu_get_reg(vcpu, rt);
+
+       if (val & ICC_CTLR_EL1_CBPR_MASK)
+               vmcr |= ICH_VMCR_CBPR_MASK;
+       else
+               vmcr &= ~ICH_VMCR_CBPR_MASK;
+
+       if (val & ICC_CTLR_EL1_EOImode_MASK)
+               vmcr |= ICH_VMCR_EOIM_MASK;
+       else
+               vmcr &= ~ICH_VMCR_EOIM_MASK;
+
+       write_gicreg(vmcr, ICH_VMCR_EL2);
+}
+
 int __hyp_text __vgic_v3_perform_cpuif_access(struct kvm_vcpu *vcpu)
 {
        int rt;
@@ -892,9 +1002,11 @@ int __hyp_text __vgic_v3_perform_cpuif_access(struct kvm_vcpu *vcpu)
        is_read = (esr & ESR_ELx_SYS64_ISS_DIR_MASK) == ESR_ELx_SYS64_ISS_DIR_READ;
 
        switch (sysreg) {
+       case ICC_IAR0_EL1:
        case ICC_IAR1_EL1:
                fn = __vgic_v3_read_iar;
                break;
+       case ICC_EOIR0_EL1:
        case ICC_EOIR1_EL1:
                fn = __vgic_v3_write_eoir;
                break;
@@ -910,33 +1022,62 @@ int __hyp_text __vgic_v3_perform_cpuif_access(struct kvm_vcpu *vcpu)
                else
                        fn = __vgic_v3_write_bpr1;
                break;
+       case ICC_AP0Rn_EL1(0):
        case ICC_AP1Rn_EL1(0):
                if (is_read)
                        fn = __vgic_v3_read_apxr0;
                else
                        fn = __vgic_v3_write_apxr0;
                break;
+       case ICC_AP0Rn_EL1(1):
        case ICC_AP1Rn_EL1(1):
                if (is_read)
                        fn = __vgic_v3_read_apxr1;
                else
                        fn = __vgic_v3_write_apxr1;
                break;
+       case ICC_AP0Rn_EL1(2):
        case ICC_AP1Rn_EL1(2):
                if (is_read)
                        fn = __vgic_v3_read_apxr2;
                else
                        fn = __vgic_v3_write_apxr2;
                break;
+       case ICC_AP0Rn_EL1(3):
        case ICC_AP1Rn_EL1(3):
                if (is_read)
                        fn = __vgic_v3_read_apxr3;
                else
                        fn = __vgic_v3_write_apxr3;
                break;
+       case ICC_HPPIR0_EL1:
        case ICC_HPPIR1_EL1:
                fn = __vgic_v3_read_hppir;
                break;
+       case ICC_GRPEN0_EL1:
+               if (is_read)
+                       fn = __vgic_v3_read_igrpen0;
+               else
+                       fn = __vgic_v3_write_igrpen0;
+               break;
+       case ICC_BPR0_EL1:
+               if (is_read)
+                       fn = __vgic_v3_read_bpr0;
+               else
+                       fn = __vgic_v3_write_bpr0;
+               break;
+       case ICC_DIR_EL1:
+               fn = __vgic_v3_write_dir;
+               break;
+       case ICC_RPR_EL1:
+               fn = __vgic_v3_read_rpr;
+               break;
+       case ICC_CTLR_EL1:
+               if (is_read)
+                       fn = __vgic_v3_read_ctlr;
+               else
+                       fn = __vgic_v3_write_ctlr;
+               break;
        default:
                return 0;
        }