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irqchip/gic-v3-its: Specialise readq and writeq accesses
authorVladimir Murzin <vladimir.murzin@arm.com>
Wed, 2 Nov 2016 11:54:06 +0000 (11:54 +0000)
committerMarc Zyngier <marc.zyngier@arm.com>
Tue, 29 Nov 2016 09:14:48 +0000 (09:14 +0000)
commit0968a61918a9140d39959a318f796412354ec24d
treea1283ec6f25af67f03d48913cc9d3be99ce3ec65tree
parent328191c05ed72762c382bdb835607dd5bd56b0bccommit | diff
irqchip/gic-v3-its: Specialise readq and writeq accesses

readq and writeq type of assessors are not supported in AArch32, so we
need to specialise them and glue later with series of 32-bit accesses
on AArch32 side.

Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
arch/arm64/include/asm/arch_gicv3.h diff | blob | blame | history
drivers/irqchip/irq-gic-v3-its.c diff | blob | blame | history
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