[pve-kernel.git] / patches / kernel / 0009-KVM-x86-emulator-smm-add-structs-for-KVM-s-smram-lay.patch

From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Maxim Levitsky <mlevitsk@redhat.com>
Date: Wed, 3 Aug 2022 18:50:05 +0300
Subject: [PATCH] KVM: x86: emulator/smm: add structs for KVM's smram layout
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Those structs will be used to read/write the smram state image.

Also document the differences between KVM's SMRAM layout and SMRAM
layout that is used by real Intel/AMD cpus.

Signed-off-by: Maxim Levitsky <mlevitsk@redhat.com>
Signed-off-by: Thomas Lamprecht <t.lamprecht@proxmox.com>
Signed-off-by: Fabian Grünbichler <f.gruenbichler@proxmox.com>
---
 arch/x86/kvm/emulate.c     |   6 +
 arch/x86/kvm/kvm_emulate.h | 218 +++++++++++++++++++++++++++++++++++++
 arch/x86/kvm/x86.c         |   1 +
 3 files changed, 225 insertions(+)

diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c
index 4f7f5117ec7a..470dd4453b01 100644
--- a/arch/x86/kvm/emulate.c
+++ b/arch/x86/kvm/emulate.c
@@ -5856,3 +5856,9 @@ bool emulator_can_use_gpa(struct x86_emulate_ctxt *ctxt)
 
 	return true;
 }
+
+void  __init kvm_emulator_init(void)
+{
+	__check_smram32_offsets();
+	__check_smram64_offsets();
+}
diff --git a/arch/x86/kvm/kvm_emulate.h b/arch/x86/kvm/kvm_emulate.h
index 89246446d6aa..dd0ae61e44a1 100644
--- a/arch/x86/kvm/kvm_emulate.h
+++ b/arch/x86/kvm/kvm_emulate.h
@@ -13,6 +13,7 @@
 #define _ASM_X86_KVM_X86_EMULATE_H
 
 #include <asm/desc_defs.h>
+#include <linux/build_bug.h>
 #include "fpu.h"
 
 struct x86_emulate_ctxt;
@@ -503,6 +504,223 @@ enum x86_intercept {
 	nr_x86_intercepts
 };
 
+
+/* 32 bit KVM's emulated SMM layout. Loosely based on Intel's layout */
+
+struct kvm_smm_seg_state_32 {
+	u32 flags;
+	u32 limit;
+	u32 base;
+} __packed;
+
+struct kvm_smram_state_32 {
+	u32 reserved1[62];
+	u32 smbase;
+	u32 smm_revision;
+	u32 reserved2[5];
+	u32 cr4; /* CR4 is not present in Intel/AMD SMRAM image */
+	u32 reserved3[5];
+
+	/*
+	 * Segment state is not present/documented in the Intel/AMD SMRAM image
+	 * Instead this area on Intel/AMD contains IO/HLT restart flags.
+	 */
+	struct kvm_smm_seg_state_32 ds;
+	struct kvm_smm_seg_state_32 fs;
+	struct kvm_smm_seg_state_32 gs;
+	struct kvm_smm_seg_state_32 idtr; /* IDTR has only base and limit */
+	struct kvm_smm_seg_state_32 tr;
+	u32 reserved;
+	struct kvm_smm_seg_state_32 gdtr; /* GDTR has only base and limit */
+	struct kvm_smm_seg_state_32 ldtr;
+	struct kvm_smm_seg_state_32 es;
+	struct kvm_smm_seg_state_32 cs;
+	struct kvm_smm_seg_state_32 ss;
+
+	u32 es_sel;
+	u32 cs_sel;
+	u32 ss_sel;
+	u32 ds_sel;
+	u32 fs_sel;
+	u32 gs_sel;
+	u32 ldtr_sel;
+	u32 tr_sel;
+
+	u32 dr7;
+	u32 dr6;
+	u32 gprs[8]; /* GPRS in the "natural" X86 order (EAX/ECX/EDX.../EDI) */
+	u32 eip;
+	u32 eflags;
+	u32 cr3;
+	u32 cr0;
+} __packed;
+
+
+static inline void __check_smram32_offsets(void)
+{
+#define __CHECK_SMRAM32_OFFSET(field, offset) \
+	ASSERT_STRUCT_OFFSET(struct kvm_smram_state_32, field, offset - 0xFE00)
+
+	__CHECK_SMRAM32_OFFSET(reserved1,	0xFE00);
+	__CHECK_SMRAM32_OFFSET(smbase,		0xFEF8);
+	__CHECK_SMRAM32_OFFSET(smm_revision,	0xFEFC);
+	__CHECK_SMRAM32_OFFSET(reserved2,	0xFF00);
+	__CHECK_SMRAM32_OFFSET(cr4,		0xFF14);
+	__CHECK_SMRAM32_OFFSET(reserved3,	0xFF18);
+	__CHECK_SMRAM32_OFFSET(ds,		0xFF2C);
+	__CHECK_SMRAM32_OFFSET(fs,		0xFF38);
+	__CHECK_SMRAM32_OFFSET(gs,		0xFF44);
+	__CHECK_SMRAM32_OFFSET(idtr,		0xFF50);
+	__CHECK_SMRAM32_OFFSET(tr,		0xFF5C);
+	__CHECK_SMRAM32_OFFSET(gdtr,		0xFF6C);
+	__CHECK_SMRAM32_OFFSET(ldtr,		0xFF78);
+	__CHECK_SMRAM32_OFFSET(es,		0xFF84);
+	__CHECK_SMRAM32_OFFSET(cs,		0xFF90);
+	__CHECK_SMRAM32_OFFSET(ss,		0xFF9C);
+	__CHECK_SMRAM32_OFFSET(es_sel,		0xFFA8);
+	__CHECK_SMRAM32_OFFSET(cs_sel,		0xFFAC);
+	__CHECK_SMRAM32_OFFSET(ss_sel,		0xFFB0);
+	__CHECK_SMRAM32_OFFSET(ds_sel,		0xFFB4);
+	__CHECK_SMRAM32_OFFSET(fs_sel,		0xFFB8);
+	__CHECK_SMRAM32_OFFSET(gs_sel,		0xFFBC);
+	__CHECK_SMRAM32_OFFSET(ldtr_sel,	0xFFC0);
+	__CHECK_SMRAM32_OFFSET(tr_sel,		0xFFC4);
+	__CHECK_SMRAM32_OFFSET(dr7,		0xFFC8);
+	__CHECK_SMRAM32_OFFSET(dr6,		0xFFCC);
+	__CHECK_SMRAM32_OFFSET(gprs,		0xFFD0);
+	__CHECK_SMRAM32_OFFSET(eip,		0xFFF0);
+	__CHECK_SMRAM32_OFFSET(eflags,		0xFFF4);
+	__CHECK_SMRAM32_OFFSET(cr3,		0xFFF8);
+	__CHECK_SMRAM32_OFFSET(cr0,		0xFFFC);
+#undef __CHECK_SMRAM32_OFFSET
+}
+
+
+/* 64 bit KVM's emulated SMM layout. Based on AMD64 layout */
+
+struct kvm_smm_seg_state_64 {
+	u16 selector;
+	u16 attributes;
+	u32 limit;
+	u64 base;
+};
+
+struct kvm_smram_state_64 {
+
+	struct kvm_smm_seg_state_64 es;
+	struct kvm_smm_seg_state_64 cs;
+	struct kvm_smm_seg_state_64 ss;
+	struct kvm_smm_seg_state_64 ds;
+	struct kvm_smm_seg_state_64 fs;
+	struct kvm_smm_seg_state_64 gs;
+	struct kvm_smm_seg_state_64 gdtr; /* GDTR has only base and limit*/
+	struct kvm_smm_seg_state_64 ldtr;
+	struct kvm_smm_seg_state_64 idtr; /* IDTR has only base and limit*/
+	struct kvm_smm_seg_state_64 tr;
+
+	/* I/O restart and auto halt restart are not implemented by KVM */
+	u64 io_restart_rip;
+	u64 io_restart_rcx;
+	u64 io_restart_rsi;
+	u64 io_restart_rdi;
+	u32 io_restart_dword;
+	u32 reserved1;
+	u8 io_inst_restart;
+	u8 auto_hlt_restart;
+	u8 reserved2[6];
+
+	u64 efer;
+
+	/*
+	 * Two fields below are implemented on AMD only, to store
+	 * SVM guest vmcb address if the #SMI was received while in the guest mode.
+	 */
+	u64 svm_guest_flag;
+	u64 svm_guest_vmcb_gpa;
+	u64 svm_guest_virtual_int; /* unknown purpose, not implemented */
+
+	u32 reserved3[3];
+	u32 smm_revison;
+	u32 smbase;
+	u32 reserved4[5];
+
+	/* ssp and svm_* fields below are not implemented by KVM */
+	u64 ssp;
+	u64 svm_guest_pat;
+	u64 svm_host_efer;
+	u64 svm_host_cr4;
+	u64 svm_host_cr3;
+	u64 svm_host_cr0;
+
+	u64 cr4;
+	u64 cr3;
+	u64 cr0;
+	u64 dr7;
+	u64 dr6;
+	u64 rflags;
+	u64 rip;
+	u64 gprs[16]; /* GPRS in a reversed "natural" X86 order (R15/R14/../RCX/RAX.) */
+};
+
+
+static inline void __check_smram64_offsets(void)
+{
+#define __CHECK_SMRAM64_OFFSET(field, offset) \
+	ASSERT_STRUCT_OFFSET(struct kvm_smram_state_64, field, offset - 0xFE00)
+
+	__CHECK_SMRAM64_OFFSET(es,			0xFE00);
+	__CHECK_SMRAM64_OFFSET(cs,			0xFE10);
+	__CHECK_SMRAM64_OFFSET(ss,			0xFE20);
+	__CHECK_SMRAM64_OFFSET(ds,			0xFE30);
+	__CHECK_SMRAM64_OFFSET(fs,			0xFE40);
+	__CHECK_SMRAM64_OFFSET(gs,			0xFE50);
+	__CHECK_SMRAM64_OFFSET(gdtr,			0xFE60);
+	__CHECK_SMRAM64_OFFSET(ldtr,			0xFE70);
+	__CHECK_SMRAM64_OFFSET(idtr,			0xFE80);
+	__CHECK_SMRAM64_OFFSET(tr,			0xFE90);
+	__CHECK_SMRAM64_OFFSET(io_restart_rip,		0xFEA0);
+	__CHECK_SMRAM64_OFFSET(io_restart_rcx,		0xFEA8);
+	__CHECK_SMRAM64_OFFSET(io_restart_rsi,		0xFEB0);
+	__CHECK_SMRAM64_OFFSET(io_restart_rdi,		0xFEB8);
+	__CHECK_SMRAM64_OFFSET(io_restart_dword,	0xFEC0);
+	__CHECK_SMRAM64_OFFSET(reserved1,		0xFEC4);
+	__CHECK_SMRAM64_OFFSET(io_inst_restart,		0xFEC8);
+	__CHECK_SMRAM64_OFFSET(auto_hlt_restart,	0xFEC9);
+	__CHECK_SMRAM64_OFFSET(reserved2,		0xFECA);
+	__CHECK_SMRAM64_OFFSET(efer,			0xFED0);
+	__CHECK_SMRAM64_OFFSET(svm_guest_flag,		0xFED8);
+	__CHECK_SMRAM64_OFFSET(svm_guest_vmcb_gpa,	0xFEE0);
+	__CHECK_SMRAM64_OFFSET(svm_guest_virtual_int,	0xFEE8);
+	__CHECK_SMRAM64_OFFSET(reserved3,		0xFEF0);
+	__CHECK_SMRAM64_OFFSET(smm_revison,		0xFEFC);
+	__CHECK_SMRAM64_OFFSET(smbase,			0xFF00);
+	__CHECK_SMRAM64_OFFSET(reserved4,		0xFF04);
+	__CHECK_SMRAM64_OFFSET(ssp,			0xFF18);
+	__CHECK_SMRAM64_OFFSET(svm_guest_pat,		0xFF20);
+	__CHECK_SMRAM64_OFFSET(svm_host_efer,		0xFF28);
+	__CHECK_SMRAM64_OFFSET(svm_host_cr4,		0xFF30);
+	__CHECK_SMRAM64_OFFSET(svm_host_cr3,		0xFF38);
+	__CHECK_SMRAM64_OFFSET(svm_host_cr0,		0xFF40);
+	__CHECK_SMRAM64_OFFSET(cr4,			0xFF48);
+	__CHECK_SMRAM64_OFFSET(cr3,			0xFF50);
+	__CHECK_SMRAM64_OFFSET(cr0,			0xFF58);
+	__CHECK_SMRAM64_OFFSET(dr7,			0xFF60);
+	__CHECK_SMRAM64_OFFSET(dr6,			0xFF68);
+	__CHECK_SMRAM64_OFFSET(rflags,			0xFF70);
+	__CHECK_SMRAM64_OFFSET(rip,			0xFF78);
+	__CHECK_SMRAM64_OFFSET(gprs,			0xFF80);
+#undef __CHECK_SMRAM64_OFFSET
+}
+
+union kvm_smram {
+	struct kvm_smram_state_64 smram64;
+	struct kvm_smram_state_32 smram32;
+	u8 bytes[512];
+};
+
+void  __init kvm_emulator_init(void);
+
+
 /* Host execution mode. */
 #if defined(CONFIG_X86_32)
 #define X86EMUL_MODE_HOST X86EMUL_MODE_PROT32
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 393b1040f96e..8bdcba503f35 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -13751,6 +13751,7 @@ EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_exit);
 static int __init kvm_x86_init(void)
 {
 	kvm_mmu_x86_module_init();
+	kvm_emulator_init();
 	mitigate_smt_rsb &= boot_cpu_has_bug(X86_BUG_SMT_RSB) && cpu_smt_possible();
 	return 0;
 }
Commit	Line	Data
f6df304f TL	1	From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
f6df304f TL	2	From: Maxim Levitsky <mlevitsk@redhat.com>
83250735	3	Date: Wed, 3 Aug 2022 18:50:05 +0300
f6df304f	4	Subject: [PATCH] KVM: x86: emulator/smm: add structs for KVM's smram layout
826eb0ff FG	5	MIME-Version: 1.0
	6	Content-Type: text/plain; charset=UTF-8
	7	Content-Transfer-Encoding: 8bit
f6df304f TL	8
	9	Those structs will be used to read/write the smram state image.
	10
	11	Also document the differences between KVM's SMRAM layout and SMRAM
	12	layout that is used by real Intel/AMD cpus.
	13
	14	Signed-off-by: Maxim Levitsky <mlevitsk@redhat.com>
	15	Signed-off-by: Thomas Lamprecht <t.lamprecht@proxmox.com>
826eb0ff	16	Signed-off-by: Fabian Grünbichler <f.gruenbichler@proxmox.com>
f6df304f	17	---
83250735 TL	18	arch/x86/kvm/emulate.c \| 6 +
	19	arch/x86/kvm/kvm_emulate.h \| 218 +++++++++++++++++++++++++++++++++++++
	20	arch/x86/kvm/x86.c \| 1 +
	21	3 files changed, 225 insertions(+)
f6df304f	22
83250735	23	diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c
12247ad0	24	index 4f7f5117ec7a..470dd4453b01 100644
83250735 TL	25	--- a/arch/x86/kvm/emulate.c
83250735 TL	26	+++ b/arch/x86/kvm/emulate.c
12247ad0	27	@@ -5856,3 +5856,9 @@ bool emulator_can_use_gpa(struct x86_emulate_ctxt *ctxt)
83250735 TL	28
	29	return true;
	30	}
	31	+
	32	+void __init kvm_emulator_init(void)
	33	+{
	34	+ __check_smram32_offsets();
	35	+ __check_smram64_offsets();
	36	+}
f6df304f	37	diff --git a/arch/x86/kvm/kvm_emulate.h b/arch/x86/kvm/kvm_emulate.h
12247ad0	38	index 89246446d6aa..dd0ae61e44a1 100644
f6df304f TL	39	--- a/arch/x86/kvm/kvm_emulate.h
f6df304f TL	40	+++ b/arch/x86/kvm/kvm_emulate.h
83250735 TL	41	@@ -13,6 +13,7 @@
	42	#define _ASM_X86_KVM_X86_EMULATE_H
	43
	44	#include <asm/desc_defs.h>
	45	+#include <linux/build_bug.h>
	46	#include "fpu.h"
	47
	48	struct x86_emulate_ctxt;
12247ad0	49	@@ -503,6 +504,223 @@ enum x86_intercept {
f6df304f TL	50	nr_x86_intercepts
	51	};
	52
	53	+
83250735	54	+/* 32 bit KVM's emulated SMM layout. Loosely based on Intel's layout */
f6df304f TL	55	+
	56	+struct kvm_smm_seg_state_32 {
	57	+ u32 flags;
	58	+ u32 limit;
	59	+ u32 base;
	60	+} __packed;
	61	+
	62	+struct kvm_smram_state_32 {
83250735 TL	63	+ u32 reserved1[62];
	64	+ u32 smbase;
	65	+ u32 smm_revision;
	66	+ u32 reserved2[5];
	67	+ u32 cr4; /* CR4 is not present in Intel/AMD SMRAM image */
	68	+ u32 reserved3[5];
f6df304f TL	69	+
f6df304f TL	70	+ /*
83250735 TL	71	+ * Segment state is not present/documented in the Intel/AMD SMRAM image
83250735 TL	72	+ * Instead this area on Intel/AMD contains IO/HLT restart flags.
f6df304f	73	+ */
83250735 TL	74	+ struct kvm_smm_seg_state_32 ds;
	75	+ struct kvm_smm_seg_state_32 fs;
	76	+ struct kvm_smm_seg_state_32 gs;
	77	+ struct kvm_smm_seg_state_32 idtr; /* IDTR has only base and limit */
	78	+ struct kvm_smm_seg_state_32 tr;
	79	+ u32 reserved;
	80	+ struct kvm_smm_seg_state_32 gdtr; /* GDTR has only base and limit */
	81	+ struct kvm_smm_seg_state_32 ldtr;
	82	+ struct kvm_smm_seg_state_32 es;
	83	+ struct kvm_smm_seg_state_32 cs;
	84	+ struct kvm_smm_seg_state_32 ss;
	85	+
	86	+ u32 es_sel;
	87	+ u32 cs_sel;
	88	+ u32 ss_sel;
	89	+ u32 ds_sel;
	90	+ u32 fs_sel;
	91	+ u32 gs_sel;
	92	+ u32 ldtr_sel;
	93	+ u32 tr_sel;
	94	+
	95	+ u32 dr7;
	96	+ u32 dr6;
	97	+ u32 gprs[8]; /* GPRS in the "natural" X86 order (EAX/ECX/EDX.../EDI) */
	98	+ u32 eip;
	99	+ u32 eflags;
	100	+ u32 cr3;
	101	+ u32 cr0;
f6df304f TL	102	+} __packed;
f6df304f TL	103	+
83250735 TL	104	+
	105	+static inline void __check_smram32_offsets(void)
	106	+{
	107	+#define __CHECK_SMRAM32_OFFSET(field, offset) \
	108	+ ASSERT_STRUCT_OFFSET(struct kvm_smram_state_32, field, offset - 0xFE00)
	109	+
	110	+ __CHECK_SMRAM32_OFFSET(reserved1, 0xFE00);
	111	+ __CHECK_SMRAM32_OFFSET(smbase, 0xFEF8);
	112	+ __CHECK_SMRAM32_OFFSET(smm_revision, 0xFEFC);
	113	+ __CHECK_SMRAM32_OFFSET(reserved2, 0xFF00);
	114	+ __CHECK_SMRAM32_OFFSET(cr4, 0xFF14);
	115	+ __CHECK_SMRAM32_OFFSET(reserved3, 0xFF18);
	116	+ __CHECK_SMRAM32_OFFSET(ds, 0xFF2C);
	117	+ __CHECK_SMRAM32_OFFSET(fs, 0xFF38);
	118	+ __CHECK_SMRAM32_OFFSET(gs, 0xFF44);
	119	+ __CHECK_SMRAM32_OFFSET(idtr, 0xFF50);
	120	+ __CHECK_SMRAM32_OFFSET(tr, 0xFF5C);
	121	+ __CHECK_SMRAM32_OFFSET(gdtr, 0xFF6C);
	122	+ __CHECK_SMRAM32_OFFSET(ldtr, 0xFF78);
	123	+ __CHECK_SMRAM32_OFFSET(es, 0xFF84);
	124	+ __CHECK_SMRAM32_OFFSET(cs, 0xFF90);
	125	+ __CHECK_SMRAM32_OFFSET(ss, 0xFF9C);
	126	+ __CHECK_SMRAM32_OFFSET(es_sel, 0xFFA8);
	127	+ __CHECK_SMRAM32_OFFSET(cs_sel, 0xFFAC);
	128	+ __CHECK_SMRAM32_OFFSET(ss_sel, 0xFFB0);
	129	+ __CHECK_SMRAM32_OFFSET(ds_sel, 0xFFB4);
	130	+ __CHECK_SMRAM32_OFFSET(fs_sel, 0xFFB8);
	131	+ __CHECK_SMRAM32_OFFSET(gs_sel, 0xFFBC);
	132	+ __CHECK_SMRAM32_OFFSET(ldtr_sel, 0xFFC0);
	133	+ __CHECK_SMRAM32_OFFSET(tr_sel, 0xFFC4);
	134	+ __CHECK_SMRAM32_OFFSET(dr7, 0xFFC8);
	135	+ __CHECK_SMRAM32_OFFSET(dr6, 0xFFCC);
	136	+ __CHECK_SMRAM32_OFFSET(gprs, 0xFFD0);
	137	+ __CHECK_SMRAM32_OFFSET(eip, 0xFFF0);
	138	+ __CHECK_SMRAM32_OFFSET(eflags, 0xFFF4);
	139	+ __CHECK_SMRAM32_OFFSET(cr3, 0xFFF8);
	140	+ __CHECK_SMRAM32_OFFSET(cr0, 0xFFFC);
	141	+#undef __CHECK_SMRAM32_OFFSET
	142	+}
	143	+
	144	+
	145	+/* 64 bit KVM's emulated SMM layout. Based on AMD64 layout */
f6df304f TL	146	+
	147	+struct kvm_smm_seg_state_64 {
	148	+ u16 selector;
	149	+ u16 attributes;
	150	+ u32 limit;
	151	+ u64 base;
	152	+};
	153	+
	154	+struct kvm_smram_state_64 {
f6df304f	155	+
83250735 TL	156	+ struct kvm_smm_seg_state_64 es;
	157	+ struct kvm_smm_seg_state_64 cs;
	158	+ struct kvm_smm_seg_state_64 ss;
	159	+ struct kvm_smm_seg_state_64 ds;
	160	+ struct kvm_smm_seg_state_64 fs;
	161	+ struct kvm_smm_seg_state_64 gs;
	162	+ struct kvm_smm_seg_state_64 gdtr; /* GDTR has only base and limit*/
	163	+ struct kvm_smm_seg_state_64 ldtr;
	164	+ struct kvm_smm_seg_state_64 idtr; /* IDTR has only base and limit*/
	165	+ struct kvm_smm_seg_state_64 tr;
f6df304f TL	166	+
f6df304f TL	167	+ /* I/O restart and auto halt restart are not implemented by KVM */
83250735 TL	168	+ u64 io_restart_rip;
	169	+ u64 io_restart_rcx;
	170	+ u64 io_restart_rsi;
	171	+ u64 io_restart_rdi;
	172	+ u32 io_restart_dword;
	173	+ u32 reserved1;
	174	+ u8 io_inst_restart;
	175	+ u8 auto_hlt_restart;
	176	+ u8 reserved2[6];
	177	+
	178	+ u64 efer;
f6df304f TL	179	+
f6df304f TL	180	+ /*
83250735 TL	181	+ * Two fields below are implemented on AMD only, to store
83250735 TL	182	+ * SVM guest vmcb address if the #SMI was received while in the guest mode.
f6df304f	183	+ */
83250735 TL	184	+ u64 svm_guest_flag;
	185	+ u64 svm_guest_vmcb_gpa;
	186	+ u64 svm_guest_virtual_int; /* unknown purpose, not implemented */
f6df304f	187	+
83250735 TL	188	+ u32 reserved3[3];
	189	+ u32 smm_revison;
	190	+ u32 smbase;
	191	+ u32 reserved4[5];
f6df304f	192	+
83250735 TL	193	+ /* ssp and svm_* fields below are not implemented by KVM */
	194	+ u64 ssp;
	195	+ u64 svm_guest_pat;
	196	+ u64 svm_host_efer;
	197	+ u64 svm_host_cr4;
	198	+ u64 svm_host_cr3;
	199	+ u64 svm_host_cr0;
f6df304f	200	+
83250735 TL	201	+ u64 cr4;
	202	+ u64 cr3;
	203	+ u64 cr0;
	204	+ u64 dr7;
	205	+ u64 dr6;
	206	+ u64 rflags;
	207	+ u64 rip;
	208	+ u64 gprs[16]; /* GPRS in a reversed "natural" X86 order (R15/R14/../RCX/RAX.) */
	209	+};
f6df304f	210	+
f6df304f	211	+
83250735 TL	212	+static inline void __check_smram64_offsets(void)
	213	+{
	214	+#define __CHECK_SMRAM64_OFFSET(field, offset) \
	215	+ ASSERT_STRUCT_OFFSET(struct kvm_smram_state_64, field, offset - 0xFE00)
f6df304f	216	+
83250735 TL	217	+ __CHECK_SMRAM64_OFFSET(es, 0xFE00);
	218	+ __CHECK_SMRAM64_OFFSET(cs, 0xFE10);
	219	+ __CHECK_SMRAM64_OFFSET(ss, 0xFE20);
	220	+ __CHECK_SMRAM64_OFFSET(ds, 0xFE30);
	221	+ __CHECK_SMRAM64_OFFSET(fs, 0xFE40);
	222	+ __CHECK_SMRAM64_OFFSET(gs, 0xFE50);
	223	+ __CHECK_SMRAM64_OFFSET(gdtr, 0xFE60);
	224	+ __CHECK_SMRAM64_OFFSET(ldtr, 0xFE70);
	225	+ __CHECK_SMRAM64_OFFSET(idtr, 0xFE80);
	226	+ __CHECK_SMRAM64_OFFSET(tr, 0xFE90);
	227	+ __CHECK_SMRAM64_OFFSET(io_restart_rip, 0xFEA0);
	228	+ __CHECK_SMRAM64_OFFSET(io_restart_rcx, 0xFEA8);
	229	+ __CHECK_SMRAM64_OFFSET(io_restart_rsi, 0xFEB0);
	230	+ __CHECK_SMRAM64_OFFSET(io_restart_rdi, 0xFEB8);
	231	+ __CHECK_SMRAM64_OFFSET(io_restart_dword, 0xFEC0);
	232	+ __CHECK_SMRAM64_OFFSET(reserved1, 0xFEC4);
	233	+ __CHECK_SMRAM64_OFFSET(io_inst_restart, 0xFEC8);
	234	+ __CHECK_SMRAM64_OFFSET(auto_hlt_restart, 0xFEC9);
	235	+ __CHECK_SMRAM64_OFFSET(reserved2, 0xFECA);
	236	+ __CHECK_SMRAM64_OFFSET(efer, 0xFED0);
	237	+ __CHECK_SMRAM64_OFFSET(svm_guest_flag, 0xFED8);
	238	+ __CHECK_SMRAM64_OFFSET(svm_guest_vmcb_gpa, 0xFEE0);
	239	+ __CHECK_SMRAM64_OFFSET(svm_guest_virtual_int, 0xFEE8);
	240	+ __CHECK_SMRAM64_OFFSET(reserved3, 0xFEF0);
	241	+ __CHECK_SMRAM64_OFFSET(smm_revison, 0xFEFC);
	242	+ __CHECK_SMRAM64_OFFSET(smbase, 0xFF00);
	243	+ __CHECK_SMRAM64_OFFSET(reserved4, 0xFF04);
	244	+ __CHECK_SMRAM64_OFFSET(ssp, 0xFF18);
	245	+ __CHECK_SMRAM64_OFFSET(svm_guest_pat, 0xFF20);
	246	+ __CHECK_SMRAM64_OFFSET(svm_host_efer, 0xFF28);
	247	+ __CHECK_SMRAM64_OFFSET(svm_host_cr4, 0xFF30);
	248	+ __CHECK_SMRAM64_OFFSET(svm_host_cr3, 0xFF38);
	249	+ __CHECK_SMRAM64_OFFSET(svm_host_cr0, 0xFF40);
	250	+ __CHECK_SMRAM64_OFFSET(cr4, 0xFF48);
	251	+ __CHECK_SMRAM64_OFFSET(cr3, 0xFF50);
	252	+ __CHECK_SMRAM64_OFFSET(cr0, 0xFF58);
	253	+ __CHECK_SMRAM64_OFFSET(dr7, 0xFF60);
	254	+ __CHECK_SMRAM64_OFFSET(dr6, 0xFF68);
	255	+ __CHECK_SMRAM64_OFFSET(rflags, 0xFF70);
	256	+ __CHECK_SMRAM64_OFFSET(rip, 0xFF78);
	257	+ __CHECK_SMRAM64_OFFSET(gprs, 0xFF80);
	258	+#undef __CHECK_SMRAM64_OFFSET
	259	+}
f6df304f	260	+
83250735 TL	261	+union kvm_smram {
	262	+ struct kvm_smram_state_64 smram64;
	263	+ struct kvm_smram_state_32 smram32;
	264	+ u8 bytes[512];
f6df304f TL	265	+};
f6df304f TL	266	+
83250735 TL	267	+void __init kvm_emulator_init(void);
83250735 TL	268	+
f6df304f TL	269	+
	270	/* Host execution mode. */
	271	#if defined(CONFIG_X86_32)
	272	#define X86EMUL_MODE_HOST X86EMUL_MODE_PROT32
83250735	273	diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
fc2b61b1	274	index 393b1040f96e..8bdcba503f35 100644
83250735 TL	275	--- a/arch/x86/kvm/x86.c
83250735 TL	276	+++ b/arch/x86/kvm/x86.c
fc2b61b1	277	@@ -13751,6 +13751,7 @@ EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_exit);
83250735 TL	278	static int __init kvm_x86_init(void)
	279	{
	280	kvm_mmu_x86_module_init();
	281	+ kvm_emulator_init();
fc2b61b1	282	mitigate_smt_rsb &= boot_cpu_has_bug(X86_BUG_SMT_RSB) && cpu_smt_possible();
83250735 TL	283	return 0;
83250735 TL	284	}