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321d628a FG |
1 | From 4264307e3e9665cba9220e02ada91ad9b4742711 Mon Sep 17 00:00:00 2001 |
2 | From: Ingo Molnar <mingo@kernel.org> | |
3 | Date: Tue, 31 Oct 2017 13:17:23 +0100 | |
b378f209 | 4 | Subject: [PATCH 111/233] x86/cpufeatures: Fix various details in the feature |
321d628a FG |
5 | definitions |
6 | MIME-Version: 1.0 | |
7 | Content-Type: text/plain; charset=UTF-8 | |
8 | Content-Transfer-Encoding: 8bit | |
9 | ||
10 | CVE-2017-5754 | |
11 | ||
12 | Kept this commit separate from the re-tabulation changes, to make | |
13 | the changes easier to review: | |
14 | ||
15 | - add better explanation for entries with no explanation | |
16 | - fix/enhance the text of some of the entries | |
17 | - fix the vertical alignment of some of the feature number definitions | |
18 | - fix inconsistent capitalization | |
19 | - ... and lots of other small details | |
20 | ||
21 | i.e. make it all more of a coherent unit, instead of a patchwork of years of additions. | |
22 | ||
23 | Cc: Andrew Morton <akpm@linux-foundation.org> | |
24 | Cc: Andy Lutomirski <luto@amacapital.net> | |
25 | Cc: Andy Lutomirski <luto@kernel.org> | |
26 | Cc: Borislav Petkov <bp@alien8.de> | |
27 | Cc: Brian Gerst <brgerst@gmail.com> | |
28 | Cc: Denys Vlasenko <dvlasenk@redhat.com> | |
29 | Cc: Josh Poimboeuf <jpoimboe@redhat.com> | |
30 | Cc: Linus Torvalds <torvalds@linux-foundation.org> | |
31 | Cc: Peter Zijlstra <peterz@infradead.org> | |
32 | Cc: Thomas Gleixner <tglx@linutronix.de> | |
33 | Link: http://lkml.kernel.org/r/20171031121723.28524-4-mingo@kernel.org | |
34 | Signed-off-by: Ingo Molnar <mingo@kernel.org> | |
35 | (backported from commit f3a624e901c633593156f7b00ca743a6204a29bc) | |
36 | Signed-off-by: Andy Whitcroft <apw@canonical.com> | |
37 | Signed-off-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com> | |
38 | (cherry picked from commit 256c600cf0edb23ea5f2d70e7da091c909f5ace6) | |
39 | Signed-off-by: Fabian Grünbichler <f.gruenbichler@proxmox.com> | |
40 | --- | |
41 | arch/x86/include/asm/cpufeatures.h | 149 ++++++++++++++++++------------------- | |
42 | 1 file changed, 74 insertions(+), 75 deletions(-) | |
43 | ||
44 | diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h | |
45 | index a021b0756af6..6db782ed9cdb 100644 | |
46 | --- a/arch/x86/include/asm/cpufeatures.h | |
47 | +++ b/arch/x86/include/asm/cpufeatures.h | |
48 | @@ -19,14 +19,12 @@ | |
49 | * Note: If the comment begins with a quoted string, that string is used | |
50 | * in /proc/cpuinfo instead of the macro name. If the string is "", | |
51 | * this feature bit is not displayed in /proc/cpuinfo at all. | |
52 | - */ | |
53 | - | |
54 | -/* | |
55 | + * | |
56 | * When adding new features here that depend on other features, | |
57 | - * please update the table in kernel/cpu/cpuid-deps.c | |
58 | + * please update the table in kernel/cpu/cpuid-deps.c as well. | |
59 | */ | |
60 | ||
61 | -/* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */ | |
62 | +/* Intel-defined CPU features, CPUID level 0x00000001 (EDX), word 0 */ | |
63 | #define X86_FEATURE_FPU ( 0*32+ 0) /* Onboard FPU */ | |
64 | #define X86_FEATURE_VME ( 0*32+ 1) /* Virtual Mode Extensions */ | |
65 | #define X86_FEATURE_DE ( 0*32+ 2) /* Debugging Extensions */ | |
66 | @@ -41,8 +39,7 @@ | |
67 | #define X86_FEATURE_MTRR ( 0*32+12) /* Memory Type Range Registers */ | |
68 | #define X86_FEATURE_PGE ( 0*32+13) /* Page Global Enable */ | |
69 | #define X86_FEATURE_MCA ( 0*32+14) /* Machine Check Architecture */ | |
70 | -#define X86_FEATURE_CMOV ( 0*32+15) /* CMOV instructions */ | |
71 | - /* (plus FCMOVcc, FCOMI with FPU) */ | |
72 | +#define X86_FEATURE_CMOV ( 0*32+15) /* CMOV instructions (plus FCMOVcc, FCOMI with FPU) */ | |
73 | #define X86_FEATURE_PAT ( 0*32+16) /* Page Attribute Table */ | |
74 | #define X86_FEATURE_PSE36 ( 0*32+17) /* 36-bit PSEs */ | |
75 | #define X86_FEATURE_PN ( 0*32+18) /* Processor serial number */ | |
76 | @@ -62,15 +59,15 @@ | |
77 | /* AMD-defined CPU features, CPUID level 0x80000001, word 1 */ | |
78 | /* Don't duplicate feature flags which are redundant with Intel! */ | |
79 | #define X86_FEATURE_SYSCALL ( 1*32+11) /* SYSCALL/SYSRET */ | |
80 | -#define X86_FEATURE_MP ( 1*32+19) /* MP Capable. */ | |
81 | +#define X86_FEATURE_MP ( 1*32+19) /* MP Capable */ | |
82 | #define X86_FEATURE_NX ( 1*32+20) /* Execute Disable */ | |
83 | #define X86_FEATURE_MMXEXT ( 1*32+22) /* AMD MMX extensions */ | |
84 | #define X86_FEATURE_FXSR_OPT ( 1*32+25) /* FXSAVE/FXRSTOR optimizations */ | |
85 | #define X86_FEATURE_GBPAGES ( 1*32+26) /* "pdpe1gb" GB pages */ | |
86 | #define X86_FEATURE_RDTSCP ( 1*32+27) /* RDTSCP */ | |
87 | -#define X86_FEATURE_LM ( 1*32+29) /* Long Mode (x86-64) */ | |
88 | -#define X86_FEATURE_3DNOWEXT ( 1*32+30) /* AMD 3DNow! extensions */ | |
89 | -#define X86_FEATURE_3DNOW ( 1*32+31) /* 3DNow! */ | |
90 | +#define X86_FEATURE_LM ( 1*32+29) /* Long Mode (x86-64, 64-bit support) */ | |
91 | +#define X86_FEATURE_3DNOWEXT ( 1*32+30) /* AMD 3DNow extensions */ | |
92 | +#define X86_FEATURE_3DNOW ( 1*32+31) /* 3DNow */ | |
93 | ||
94 | /* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */ | |
95 | #define X86_FEATURE_RECOVERY ( 2*32+ 0) /* CPU in recovery mode */ | |
96 | @@ -83,66 +80,67 @@ | |
97 | #define X86_FEATURE_K6_MTRR ( 3*32+ 1) /* AMD K6 nonstandard MTRRs */ | |
98 | #define X86_FEATURE_CYRIX_ARR ( 3*32+ 2) /* Cyrix ARRs (= MTRRs) */ | |
99 | #define X86_FEATURE_CENTAUR_MCR ( 3*32+ 3) /* Centaur MCRs (= MTRRs) */ | |
100 | -/* cpu types for specific tunings: */ | |
101 | + | |
102 | +/* CPU types for specific tunings: */ | |
103 | #define X86_FEATURE_K8 ( 3*32+ 4) /* "" Opteron, Athlon64 */ | |
104 | #define X86_FEATURE_K7 ( 3*32+ 5) /* "" Athlon */ | |
105 | #define X86_FEATURE_P3 ( 3*32+ 6) /* "" P3 */ | |
106 | #define X86_FEATURE_P4 ( 3*32+ 7) /* "" P4 */ | |
107 | #define X86_FEATURE_CONSTANT_TSC ( 3*32+ 8) /* TSC ticks at a constant rate */ | |
108 | -#define X86_FEATURE_UP ( 3*32+ 9) /* smp kernel running on up */ | |
109 | -#define X86_FEATURE_ART ( 3*32+10) /* Platform has always running timer (ART) */ | |
110 | +#define X86_FEATURE_UP ( 3*32+ 9) /* SMP kernel running on UP */ | |
111 | +#define X86_FEATURE_ART ( 3*32+10) /* Always running timer (ART) */ | |
112 | #define X86_FEATURE_ARCH_PERFMON ( 3*32+11) /* Intel Architectural PerfMon */ | |
113 | #define X86_FEATURE_PEBS ( 3*32+12) /* Precise-Event Based Sampling */ | |
114 | #define X86_FEATURE_BTS ( 3*32+13) /* Branch Trace Store */ | |
115 | -#define X86_FEATURE_SYSCALL32 ( 3*32+14) /* "" syscall in ia32 userspace */ | |
116 | -#define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in ia32 userspace */ | |
117 | -#define X86_FEATURE_REP_GOOD ( 3*32+16) /* rep microcode works well */ | |
118 | -#define X86_FEATURE_MFENCE_RDTSC ( 3*32+17) /* "" Mfence synchronizes RDTSC */ | |
119 | -#define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" Lfence synchronizes RDTSC */ | |
120 | +#define X86_FEATURE_SYSCALL32 ( 3*32+14) /* "" syscall in IA32 userspace */ | |
121 | +#define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in IA32 userspace */ | |
122 | +#define X86_FEATURE_REP_GOOD ( 3*32+16) /* REP microcode works well */ | |
123 | +#define X86_FEATURE_MFENCE_RDTSC ( 3*32+17) /* "" MFENCE synchronizes RDTSC */ | |
124 | +#define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" LFENCE synchronizes RDTSC */ | |
125 | #define X86_FEATURE_ACC_POWER ( 3*32+19) /* AMD Accumulated Power Mechanism */ | |
126 | #define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */ | |
127 | #define X86_FEATURE_ALWAYS ( 3*32+21) /* "" Always-present feature */ | |
128 | -#define X86_FEATURE_XTOPOLOGY ( 3*32+22) /* cpu topology enum extensions */ | |
129 | +#define X86_FEATURE_XTOPOLOGY ( 3*32+22) /* CPU topology enum extensions */ | |
130 | #define X86_FEATURE_TSC_RELIABLE ( 3*32+23) /* TSC is known to be reliable */ | |
131 | #define X86_FEATURE_NONSTOP_TSC ( 3*32+24) /* TSC does not stop in C states */ | |
132 | #define X86_FEATURE_CPUID ( 3*32+25) /* CPU has CPUID instruction itself */ | |
133 | -#define X86_FEATURE_EXTD_APICID ( 3*32+26) /* has extended APICID (8 bits) */ | |
134 | -#define X86_FEATURE_AMD_DCM ( 3*32+27) /* multi-node processor */ | |
135 | -#define X86_FEATURE_APERFMPERF ( 3*32+28) /* APERFMPERF */ | |
136 | +#define X86_FEATURE_EXTD_APICID ( 3*32+26) /* Extended APICID (8 bits) */ | |
137 | +#define X86_FEATURE_AMD_DCM ( 3*32+27) /* AMD multi-node processor */ | |
138 | +#define X86_FEATURE_APERFMPERF ( 3*32+28) /* P-State hardware coordination feedback capability (APERF/MPERF MSRs) */ | |
139 | #define X86_FEATURE_NONSTOP_TSC_S3 ( 3*32+30) /* TSC doesn't stop in S3 state */ | |
140 | #define X86_FEATURE_TSC_KNOWN_FREQ ( 3*32+31) /* TSC has known frequency */ | |
141 | ||
142 | -/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ | |
143 | +/* Intel-defined CPU features, CPUID level 0x00000001 (ECX), word 4 */ | |
144 | #define X86_FEATURE_XMM3 ( 4*32+ 0) /* "pni" SSE-3 */ | |
145 | #define X86_FEATURE_PCLMULQDQ ( 4*32+ 1) /* PCLMULQDQ instruction */ | |
146 | #define X86_FEATURE_DTES64 ( 4*32+ 2) /* 64-bit Debug Store */ | |
147 | -#define X86_FEATURE_MWAIT ( 4*32+ 3) /* "monitor" Monitor/Mwait support */ | |
148 | -#define X86_FEATURE_DSCPL ( 4*32+ 4) /* "ds_cpl" CPL Qual. Debug Store */ | |
149 | +#define X86_FEATURE_MWAIT ( 4*32+ 3) /* "monitor" MONITOR/MWAIT support */ | |
150 | +#define X86_FEATURE_DSCPL ( 4*32+ 4) /* "ds_cpl" CPL-qualified (filtered) Debug Store */ | |
151 | #define X86_FEATURE_VMX ( 4*32+ 5) /* Hardware virtualization */ | |
152 | -#define X86_FEATURE_SMX ( 4*32+ 6) /* Safer mode */ | |
153 | +#define X86_FEATURE_SMX ( 4*32+ 6) /* Safer Mode eXtensions */ | |
154 | #define X86_FEATURE_EST ( 4*32+ 7) /* Enhanced SpeedStep */ | |
155 | #define X86_FEATURE_TM2 ( 4*32+ 8) /* Thermal Monitor 2 */ | |
156 | #define X86_FEATURE_SSSE3 ( 4*32+ 9) /* Supplemental SSE-3 */ | |
157 | #define X86_FEATURE_CID ( 4*32+10) /* Context ID */ | |
158 | #define X86_FEATURE_SDBG ( 4*32+11) /* Silicon Debug */ | |
159 | #define X86_FEATURE_FMA ( 4*32+12) /* Fused multiply-add */ | |
160 | -#define X86_FEATURE_CX16 ( 4*32+13) /* CMPXCHG16B */ | |
161 | +#define X86_FEATURE_CX16 ( 4*32+13) /* CMPXCHG16B instruction */ | |
162 | #define X86_FEATURE_XTPR ( 4*32+14) /* Send Task Priority Messages */ | |
163 | -#define X86_FEATURE_PDCM ( 4*32+15) /* Performance Capabilities */ | |
164 | +#define X86_FEATURE_PDCM ( 4*32+15) /* Perf/Debug Capabilities MSR */ | |
165 | #define X86_FEATURE_PCID ( 4*32+17) /* Process Context Identifiers */ | |
166 | #define X86_FEATURE_DCA ( 4*32+18) /* Direct Cache Access */ | |
167 | #define X86_FEATURE_XMM4_1 ( 4*32+19) /* "sse4_1" SSE-4.1 */ | |
168 | #define X86_FEATURE_XMM4_2 ( 4*32+20) /* "sse4_2" SSE-4.2 */ | |
169 | -#define X86_FEATURE_X2APIC ( 4*32+21) /* x2APIC */ | |
170 | +#define X86_FEATURE_X2APIC ( 4*32+21) /* X2APIC */ | |
171 | #define X86_FEATURE_MOVBE ( 4*32+22) /* MOVBE instruction */ | |
172 | #define X86_FEATURE_POPCNT ( 4*32+23) /* POPCNT instruction */ | |
173 | -#define X86_FEATURE_TSC_DEADLINE_TIMER ( 4*32+24) /* Tsc deadline timer */ | |
174 | +#define X86_FEATURE_TSC_DEADLINE_TIMER ( 4*32+24) /* TSC deadline timer */ | |
175 | #define X86_FEATURE_AES ( 4*32+25) /* AES instructions */ | |
176 | -#define X86_FEATURE_XSAVE ( 4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */ | |
177 | -#define X86_FEATURE_OSXSAVE ( 4*32+27) /* "" XSAVE enabled in the OS */ | |
178 | +#define X86_FEATURE_XSAVE ( 4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV instructions */ | |
179 | +#define X86_FEATURE_OSXSAVE ( 4*32+27) /* "" XSAVE instruction enabled in the OS */ | |
180 | #define X86_FEATURE_AVX ( 4*32+28) /* Advanced Vector Extensions */ | |
181 | -#define X86_FEATURE_F16C ( 4*32+29) /* 16-bit fp conversions */ | |
182 | -#define X86_FEATURE_RDRAND ( 4*32+30) /* The RDRAND instruction */ | |
183 | +#define X86_FEATURE_F16C ( 4*32+29) /* 16-bit FP conversions */ | |
184 | +#define X86_FEATURE_RDRAND ( 4*32+30) /* RDRAND instruction */ | |
185 | #define X86_FEATURE_HYPERVISOR ( 4*32+31) /* Running on a hypervisor */ | |
186 | ||
187 | /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */ | |
188 | @@ -157,10 +155,10 @@ | |
189 | #define X86_FEATURE_PMM ( 5*32+12) /* PadLock Montgomery Multiplier */ | |
190 | #define X86_FEATURE_PMM_EN ( 5*32+13) /* PMM enabled */ | |
191 | ||
192 | -/* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */ | |
193 | +/* More extended AMD flags: CPUID level 0x80000001, ECX, word 6 */ | |
194 | #define X86_FEATURE_LAHF_LM ( 6*32+ 0) /* LAHF/SAHF in long mode */ | |
195 | #define X86_FEATURE_CMP_LEGACY ( 6*32+ 1) /* If yes HyperThreading not valid */ | |
196 | -#define X86_FEATURE_SVM ( 6*32+ 2) /* Secure virtual machine */ | |
197 | +#define X86_FEATURE_SVM ( 6*32+ 2) /* Secure Virtual Machine */ | |
198 | #define X86_FEATURE_EXTAPIC ( 6*32+ 3) /* Extended APIC space */ | |
199 | #define X86_FEATURE_CR8_LEGACY ( 6*32+ 4) /* CR8 in 32-bit mode */ | |
200 | #define X86_FEATURE_ABM ( 6*32+ 5) /* Advanced bit manipulation */ | |
201 | @@ -174,16 +172,16 @@ | |
202 | #define X86_FEATURE_WDT ( 6*32+13) /* Watchdog timer */ | |
203 | #define X86_FEATURE_LWP ( 6*32+15) /* Light Weight Profiling */ | |
204 | #define X86_FEATURE_FMA4 ( 6*32+16) /* 4 operands MAC instructions */ | |
205 | -#define X86_FEATURE_TCE ( 6*32+17) /* translation cache extension */ | |
206 | +#define X86_FEATURE_TCE ( 6*32+17) /* Translation Cache Extension */ | |
207 | #define X86_FEATURE_NODEID_MSR ( 6*32+19) /* NodeId MSR */ | |
208 | -#define X86_FEATURE_TBM ( 6*32+21) /* trailing bit manipulations */ | |
209 | -#define X86_FEATURE_TOPOEXT ( 6*32+22) /* topology extensions CPUID leafs */ | |
210 | -#define X86_FEATURE_PERFCTR_CORE ( 6*32+23) /* core performance counter extensions */ | |
211 | +#define X86_FEATURE_TBM ( 6*32+21) /* Trailing Bit Manipulations */ | |
212 | +#define X86_FEATURE_TOPOEXT ( 6*32+22) /* Topology extensions CPUID leafs */ | |
213 | +#define X86_FEATURE_PERFCTR_CORE ( 6*32+23) /* Core performance counter extensions */ | |
214 | #define X86_FEATURE_PERFCTR_NB ( 6*32+24) /* NB performance counter extensions */ | |
215 | -#define X86_FEATURE_BPEXT (6*32+26) /* data breakpoint extension */ | |
216 | -#define X86_FEATURE_PTSC ( 6*32+27) /* performance time-stamp counter */ | |
217 | +#define X86_FEATURE_BPEXT ( 6*32+26) /* Data breakpoint extension */ | |
218 | +#define X86_FEATURE_PTSC ( 6*32+27) /* Performance time-stamp counter */ | |
219 | #define X86_FEATURE_PERFCTR_L2 ( 6*32+28) /* Last Level Cache performance counter extensions */ | |
220 | -#define X86_FEATURE_MWAITX ( 6*32+29) /* MWAIT extension (MONITORX/MWAITX) */ | |
221 | +#define X86_FEATURE_MWAITX ( 6*32+29) /* MWAIT extension (MONITORX/MWAITX instructions) */ | |
222 | ||
223 | /* | |
224 | * Auxiliary flags: Linux defined - For features scattered in various | |
225 | @@ -191,7 +189,7 @@ | |
226 | * | |
227 | * Reuse free bits when adding new feature flags! | |
228 | */ | |
229 | -#define X86_FEATURE_RING3MWAIT ( 7*32+ 0) /* Ring 3 MONITOR/MWAIT */ | |
230 | +#define X86_FEATURE_RING3MWAIT ( 7*32+ 0) /* Ring 3 MONITOR/MWAIT instructions */ | |
231 | #define X86_FEATURE_CPUID_FAULT ( 7*32+ 1) /* Intel CPUID faulting */ | |
232 | #define X86_FEATURE_CPB ( 7*32+ 2) /* AMD Core Performance Boost */ | |
233 | #define X86_FEATURE_EPB ( 7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */ | |
234 | @@ -205,8 +203,8 @@ | |
235 | ||
236 | #define X86_FEATURE_INTEL_PPIN ( 7*32+14) /* Intel Processor Inventory Number */ | |
237 | #define X86_FEATURE_INTEL_PT ( 7*32+15) /* Intel Processor Trace */ | |
238 | -#define X86_FEATURE_AVX512_4VNNIW (7*32+16) /* AVX-512 Neural Network Instructions */ | |
239 | -#define X86_FEATURE_AVX512_4FMAPS (7*32+17) /* AVX-512 Multiply Accumulation Single precision */ | |
240 | +#define X86_FEATURE_AVX512_4VNNIW ( 7*32+16) /* AVX-512 Neural Network Instructions */ | |
241 | +#define X86_FEATURE_AVX512_4FMAPS ( 7*32+17) /* AVX-512 Multiply Accumulation Single precision */ | |
242 | ||
243 | #define X86_FEATURE_MBA ( 7*32+18) /* Memory Bandwidth Allocation */ | |
244 | ||
245 | @@ -217,19 +215,19 @@ | |
246 | #define X86_FEATURE_EPT ( 8*32+ 3) /* Intel Extended Page Table */ | |
247 | #define X86_FEATURE_VPID ( 8*32+ 4) /* Intel Virtual Processor ID */ | |
248 | ||
249 | -#define X86_FEATURE_VMMCALL ( 8*32+15) /* Prefer vmmcall to vmcall */ | |
250 | +#define X86_FEATURE_VMMCALL ( 8*32+15) /* Prefer VMMCALL to VMCALL */ | |
251 | #define X86_FEATURE_XENPV ( 8*32+16) /* "" Xen paravirtual guest */ | |
252 | ||
253 | ||
254 | -/* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 9 */ | |
255 | -#define X86_FEATURE_FSGSBASE ( 9*32+ 0) /* {RD/WR}{FS/GS}BASE instructions*/ | |
256 | -#define X86_FEATURE_TSC_ADJUST ( 9*32+ 1) /* TSC adjustment MSR 0x3b */ | |
257 | +/* Intel-defined CPU features, CPUID level 0x00000007:0 (EBX), word 9 */ | |
258 | +#define X86_FEATURE_FSGSBASE ( 9*32+ 0) /* RDFSBASE, WRFSBASE, RDGSBASE, WRGSBASE instructions*/ | |
259 | +#define X86_FEATURE_TSC_ADJUST ( 9*32+ 1) /* TSC adjustment MSR 0x3B */ | |
260 | #define X86_FEATURE_BMI1 ( 9*32+ 3) /* 1st group bit manipulation extensions */ | |
261 | #define X86_FEATURE_HLE ( 9*32+ 4) /* Hardware Lock Elision */ | |
262 | #define X86_FEATURE_AVX2 ( 9*32+ 5) /* AVX2 instructions */ | |
263 | #define X86_FEATURE_SMEP ( 9*32+ 7) /* Supervisor Mode Execution Protection */ | |
264 | #define X86_FEATURE_BMI2 ( 9*32+ 8) /* 2nd group bit manipulation extensions */ | |
265 | -#define X86_FEATURE_ERMS ( 9*32+ 9) /* Enhanced REP MOVSB/STOSB */ | |
266 | +#define X86_FEATURE_ERMS ( 9*32+ 9) /* Enhanced REP MOVSB/STOSB instructions */ | |
267 | #define X86_FEATURE_INVPCID ( 9*32+10) /* Invalidate Processor Context ID */ | |
268 | #define X86_FEATURE_RTM ( 9*32+11) /* Restricted Transactional Memory */ | |
269 | #define X86_FEATURE_CQM ( 9*32+12) /* Cache QoS Monitoring */ | |
270 | @@ -237,8 +235,8 @@ | |
271 | #define X86_FEATURE_RDT_A ( 9*32+15) /* Resource Director Technology Allocation */ | |
272 | #define X86_FEATURE_AVX512F ( 9*32+16) /* AVX-512 Foundation */ | |
273 | #define X86_FEATURE_AVX512DQ ( 9*32+17) /* AVX-512 DQ (Double/Quad granular) Instructions */ | |
274 | -#define X86_FEATURE_RDSEED ( 9*32+18) /* The RDSEED instruction */ | |
275 | -#define X86_FEATURE_ADX ( 9*32+19) /* The ADCX and ADOX instructions */ | |
276 | +#define X86_FEATURE_RDSEED ( 9*32+18) /* RDSEED instruction */ | |
277 | +#define X86_FEATURE_ADX ( 9*32+19) /* ADCX and ADOX instructions */ | |
278 | #define X86_FEATURE_SMAP ( 9*32+20) /* Supervisor Mode Access Prevention */ | |
279 | #define X86_FEATURE_AVX512IFMA ( 9*32+21) /* AVX-512 Integer Fused Multiply-Add instructions */ | |
280 | #define X86_FEATURE_CLFLUSHOPT ( 9*32+23) /* CLFLUSHOPT instruction */ | |
281 | @@ -250,25 +248,25 @@ | |
282 | #define X86_FEATURE_AVX512BW ( 9*32+30) /* AVX-512 BW (Byte/Word granular) Instructions */ | |
283 | #define X86_FEATURE_AVX512VL ( 9*32+31) /* AVX-512 VL (128/256 Vector Length) Extensions */ | |
284 | ||
285 | -/* Extended state features, CPUID level 0x0000000d:1 (eax), word 10 */ | |
286 | -#define X86_FEATURE_XSAVEOPT (10*32+ 0) /* XSAVEOPT */ | |
287 | -#define X86_FEATURE_XSAVEC (10*32+ 1) /* XSAVEC */ | |
288 | -#define X86_FEATURE_XGETBV1 (10*32+ 2) /* XGETBV with ECX = 1 */ | |
289 | -#define X86_FEATURE_XSAVES (10*32+ 3) /* XSAVES/XRSTORS */ | |
290 | +/* Extended state features, CPUID level 0x0000000d:1 (EAX), word 10 */ | |
291 | +#define X86_FEATURE_XSAVEOPT (10*32+ 0) /* XSAVEOPT instruction */ | |
292 | +#define X86_FEATURE_XSAVEC (10*32+ 1) /* XSAVEC instruction */ | |
293 | +#define X86_FEATURE_XGETBV1 (10*32+ 2) /* XGETBV with ECX = 1 instruction */ | |
294 | +#define X86_FEATURE_XSAVES (10*32+ 3) /* XSAVES/XRSTORS instructions */ | |
295 | ||
296 | -/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:0 (edx), word 11 */ | |
297 | +/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:0 (EDX), word 11 */ | |
298 | #define X86_FEATURE_CQM_LLC (11*32+ 1) /* LLC QoS if 1 */ | |
299 | ||
300 | -/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:1 (edx), word 12 */ | |
301 | -#define X86_FEATURE_CQM_OCCUP_LLC (12*32+ 0) /* LLC occupancy monitoring if 1 */ | |
302 | +/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:1 (EDX), word 12 */ | |
303 | +#define X86_FEATURE_CQM_OCCUP_LLC (12*32+ 0) /* LLC occupancy monitoring */ | |
304 | #define X86_FEATURE_CQM_MBM_TOTAL (12*32+ 1) /* LLC Total MBM monitoring */ | |
305 | #define X86_FEATURE_CQM_MBM_LOCAL (12*32+ 2) /* LLC Local MBM monitoring */ | |
306 | ||
307 | -/* AMD-defined CPU features, CPUID level 0x80000008 (ebx), word 13 */ | |
308 | -#define X86_FEATURE_CLZERO (13*32+0) /* CLZERO instruction */ | |
309 | -#define X86_FEATURE_IRPERF (13*32+1) /* Instructions Retired Count */ | |
310 | +/* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */ | |
311 | +#define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */ | |
312 | +#define X86_FEATURE_IRPERF (13*32+ 1) /* Instructions Retired Count */ | |
313 | ||
314 | -/* Thermal and Power Management Leaf, CPUID level 0x00000006 (eax), word 14 */ | |
315 | +/* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */ | |
316 | #define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */ | |
317 | #define X86_FEATURE_IDA (14*32+ 1) /* Intel Dynamic Acceleration */ | |
318 | #define X86_FEATURE_ARAT (14*32+ 2) /* Always Running APIC Timer */ | |
319 | @@ -280,7 +278,7 @@ | |
320 | #define X86_FEATURE_HWP_EPP (14*32+10) /* HWP Energy Perf. Preference */ | |
321 | #define X86_FEATURE_HWP_PKG_REQ (14*32+11) /* HWP Package Level Request */ | |
322 | ||
323 | -/* AMD SVM Feature Identification, CPUID level 0x8000000a (edx), word 15 */ | |
324 | +/* AMD SVM Feature Identification, CPUID level 0x8000000a (EDX), word 15 */ | |
325 | #define X86_FEATURE_NPT (15*32+ 0) /* Nested Page Table support */ | |
326 | #define X86_FEATURE_LBRV (15*32+ 1) /* LBR Virtualization support */ | |
327 | #define X86_FEATURE_SVML (15*32+ 2) /* "svm_lock" SVM locking MSR */ | |
328 | @@ -295,24 +293,24 @@ | |
329 | #define X86_FEATURE_V_VMSAVE_VMLOAD (15*32+15) /* Virtual VMSAVE VMLOAD */ | |
330 | #define X86_FEATURE_VGIF (15*32+16) /* Virtual GIF */ | |
331 | ||
332 | -/* Intel-defined CPU features, CPUID level 0x00000007:0 (ecx), word 16 */ | |
333 | +/* Intel-defined CPU features, CPUID level 0x00000007:0 (ECX), word 16 */ | |
334 | #define X86_FEATURE_AVX512VBMI (16*32+ 1) /* AVX512 Vector Bit Manipulation instructions*/ | |
335 | #define X86_FEATURE_PKU (16*32+ 3) /* Protection Keys for Userspace */ | |
336 | #define X86_FEATURE_OSPKE (16*32+ 4) /* OS Protection Keys Enable */ | |
337 | #define X86_FEATURE_AVX512_VBMI2 (16*32+ 6) /* Additional AVX512 Vector Bit Manipulation Instructions */ | |
338 | #define X86_FEATURE_GFNI (16*32+ 8) /* Galois Field New Instructions */ | |
339 | #define X86_FEATURE_VAES (16*32+ 9) /* Vector AES */ | |
340 | -#define X86_FEATURE_VPCLMULQDQ (16*32+ 10) /* Carry-Less Multiplication Double Quadword */ | |
341 | -#define X86_FEATURE_AVX512_VNNI (16*32+ 11) /* Vector Neural Network Instructions */ | |
342 | -#define X86_FEATURE_AVX512_BITALG (16*32+12) /* Support for VPOPCNT[B,W] and VPSHUF-BITQMB */ | |
343 | +#define X86_FEATURE_VPCLMULQDQ (16*32+10) /* Carry-Less Multiplication Double Quadword */ | |
344 | +#define X86_FEATURE_AVX512_VNNI (16*32+11) /* Vector Neural Network Instructions */ | |
345 | +#define X86_FEATURE_AVX512_BITALG (16*32+12) /* Support for VPOPCNT[B,W] and VPSHUF-BITQMB instructions */ | |
346 | #define X86_FEATURE_AVX512_VPOPCNTDQ (16*32+14) /* POPCNT for vectors of DW/QW */ | |
347 | #define X86_FEATURE_LA57 (16*32+16) /* 5-level page tables */ | |
348 | #define X86_FEATURE_RDPID (16*32+22) /* RDPID instruction */ | |
349 | ||
350 | -/* AMD-defined CPU features, CPUID level 0x80000007 (ebx), word 17 */ | |
351 | -#define X86_FEATURE_OVERFLOW_RECOV (17*32+0) /* MCA overflow recovery support */ | |
352 | -#define X86_FEATURE_SUCCOR (17*32+1) /* Uncorrectable error containment and recovery */ | |
353 | -#define X86_FEATURE_SMCA (17*32+3) /* Scalable MCA */ | |
354 | +/* AMD-defined CPU features, CPUID level 0x80000007 (EBX), word 17 */ | |
355 | +#define X86_FEATURE_OVERFLOW_RECOV (17*32+ 0) /* MCA overflow recovery support */ | |
356 | +#define X86_FEATURE_SUCCOR (17*32+ 1) /* Uncorrectable error containment and recovery */ | |
357 | +#define X86_FEATURE_SMCA (17*32+ 3) /* Scalable MCA */ | |
358 | ||
359 | /* | |
360 | * BUG word(s) | |
361 | @@ -339,4 +337,5 @@ | |
362 | #define X86_BUG_SWAPGS_FENCE X86_BUG(11) /* SWAPGS without input dep on GS */ | |
363 | #define X86_BUG_MONITOR X86_BUG(12) /* IPI required to wake up remote CPU */ | |
364 | #define X86_BUG_AMD_E400 X86_BUG(13) /* CPU is among the affected by Erratum 400 */ | |
365 | + | |
366 | #endif /* _ASM_X86_CPUFEATURES_H */ | |
367 | -- | |
368 | 2.14.2 | |
369 |