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Commit | Line | Data |
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1c771352 WB |
1 | From c6048f849c7e3f009786df76206e895a69de032c Mon Sep 17 00:00:00 2001 |
2 | From: Shmulik Ladkani <shmulik.ladkani@ravellosystems.com> | |
3 | Date: Mon, 21 Sep 2015 17:09:02 +0300 | |
4 | Subject: [PATCH] vmxnet3: Support reading IMR registers on bar0 | |
5 | ||
6 | Instead of asserting, return the actual IMR register value. | |
7 | This is aligned with what's returned on ESXi. | |
8 | ||
9 | Signed-off-by: Shmulik Ladkani <shmulik.ladkani@ravellosystems.com> | |
10 | Tested-by: Dana Rubin <dana.rubin@ravellosystems.com> | |
11 | Signed-off-by: Jason Wang <jasowang@redhat.com> | |
12 | --- | |
13 | hw/net/vmxnet3.c | 6 +++++- | |
14 | 1 file changed, 5 insertions(+), 1 deletion(-) | |
15 | ||
16 | diff --git a/hw/net/vmxnet3.c b/hw/net/vmxnet3.c | |
17 | index 48ced71..057f0dc 100644 | |
18 | --- a/hw/net/vmxnet3.c | |
19 | +++ b/hw/net/vmxnet3.c | |
20 | @@ -1163,9 +1163,13 @@ vmxnet3_io_bar0_write(void *opaque, hwaddr addr, | |
21 | static uint64_t | |
22 | vmxnet3_io_bar0_read(void *opaque, hwaddr addr, unsigned size) | |
23 | { | |
24 | + VMXNET3State *s = opaque; | |
25 | + | |
26 | if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_IMR, | |
27 | VMXNET3_MAX_INTRS, VMXNET3_REG_ALIGN)) { | |
28 | - g_assert_not_reached(); | |
29 | + int l = VMW_MULTIREG_IDX_BY_ADDR(addr, VMXNET3_REG_IMR, | |
30 | + VMXNET3_REG_ALIGN); | |
31 | + return s->interrupt_states[l].is_masked; | |
32 | } | |
33 | ||
34 | VMW_CBPRN("BAR0 unknown read [%" PRIx64 "], size %d", addr, size); | |
35 | -- | |
36 | 2.1.4 | |
37 |