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(parent: b8095f2) | patch
target-arm: Mark 1136r1 as a v6K core
authorPeter Maydell <peter.maydell@linaro.org>
Wed, 20 Jul 2011 10:32:55 +0000 (10:32 +0000)
committerPeter Maydell <peter.maydell@linaro.org>
Tue, 26 Jul 2011 14:58:43 +0000 (14:58 +0000)
commite961d129e1712b64e561ea16fe124933115ee477
treee75b8a66d63f996bb11180f7d2f8577ef66bb1f3tree
parentb8095f24f24e50a7d4be33d8a79474aff3324295commit | diff
target-arm: Mark 1136r1 as a v6K core

The 1136r1 is actually a v6K core (unlike the 1136r0); mark it as such,
thus enabling the TLS registers, NOP hints, CLREX, half and byte wide
exclusive load/stores, etc.

The VA-to-PA translation registers are not present on 1136r1, so
introduce a new feature flag for them, which is enabled on
11MPCore and all v7 cores.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm/cpu.h diff | blob | blame | history
target-arm/helper.c diff | blob | blame | history
Qemu copy for testing