linux-user: Fix MIPS ISA transitions during signal handling
Processors supporting the MIPS16 or microMIPS ISAs set bit 0 in target
addresses to indicate that the target is written using a compressed ISA.
During signal handling, when jumping to or returning from a signal
handler, bit 0 of the destination PC is inspected and MIPS_HFLAG_M16 in
hflags cleared or set accordingly. Bit 0 of the PC is then cleared.