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8bbf0f09 A |
1 | #/** @file\r |
2 | # ARM processor package.\r | |
3 | #\r | |
d6ebcab7 | 4 | # Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>\r |
8bbf0f09 | 5 | #\r |
d6ebcab7 | 6 | # This program and the accompanying materials\r |
8bbf0f09 A |
7 | # are licensed and made available under the terms and conditions of the BSD License\r |
8 | # which accompanies this distribution. The full text of the license may be found at\r | |
9 | # http://opensource.org/licenses/bsd-license.php\r | |
10 | #\r | |
11 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | #\r | |
14 | #**/\r | |
15 | \r | |
2ef2b01e A |
16 | [Defines]\r |
17 | DEC_SPECIFICATION = 0x00010005\r | |
18 | PACKAGE_NAME = ArmPkg\r | |
19 | PACKAGE_GUID = 5CFBD99E-3C43-4E7F-8054-9CDEAFF7710F\r | |
20 | PACKAGE_VERSION = 0.1\r | |
21 | \r | |
22 | ################################################################################\r | |
23 | #\r | |
24 | # Include Section - list of Include Paths that are provided by this package.\r | |
25 | # Comments are used for Keywords and Module Types.\r | |
26 | #\r | |
27 | # Supported Module Types:\r | |
28 | # BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION\r | |
29 | #\r | |
30 | ################################################################################\r | |
31 | [Includes.common]\r | |
32 | Include # Root include for the package\r | |
33 | \r | |
34 | [LibraryClasses.common]\r | |
8bbf0f09 | 35 | ArmLib|Include/Library/ArmLib.h\r |
2ef2b01e | 36 | SemihostLib|Include/Library/Semihosting.h\r |
8bbf0f09 | 37 | UncachedMemoryAllocationLib|Include/Library/UncachedMemoryAllocationLib.h\r |
6f72e28d | 38 | DefaultExceptioHandlerLib|Include/Library/DefaultExceptioHandlerLib.h\r |
097bd461 | 39 | ArmDisassemblerLib|Include/Library/ArmDisassemblerLib.h\r |
40 | \r | |
2ef2b01e A |
41 | [Guids.common]\r |
42 | gArmTokenSpaceGuid = { 0xBB11ECFE, 0x820F, 0x4968, { 0xBB, 0xA6, 0xF7, 0x6A, 0xFE, 0x30, 0x25, 0x96 } }\r | |
43 | \r | |
44 | [Protocols.common]\r | |
8bbf0f09 | 45 | gVirtualUncachedPagesProtocolGuid = { 0xAD651C7D, 0x3C22, 0x4DBF, { 0x92, 0xe8, 0x38, 0xa7, 0xcd, 0xae, 0x87, 0xb2 } }\r |
2ef2b01e A |
46 | \r |
47 | [PcdsFeatureFlag.common]\r | |
48 | gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE|BOOLEAN|0x00000001\r | |
49 | \r | |
1bfda055 | 50 | # On ARM Architecture with the Security Extension, the address for the\r |
51 | # Vector Table can be mapped anywhere in the memory map. It means we can\r | |
52 | # point the Exception Vector Table to its location in CpuDxe.\r | |
53 | # By default we copy the Vector Table at PcdGet32(PcdCpuVectorBaseAddress)\r | |
54 | gArmTokenSpaceGuid.PcdRelocateVectorTable|TRUE|BOOLEAN|0x00000022\r | |
eeec69c5 | 55 | # Set this PCD to TRUE if the Exception Vector is changed to add debugger support before\r |
56 | # it has been configured by the CPU DXE\r | |
57 | gArmTokenSpaceGuid.PcdDebuggerExceptionSupport|FALSE|BOOLEAN|0x00000032\r | |
1bfda055 | 58 | \r |
59 | gArmTokenSpaceGuid.PcdEfiUncachedMemoryToStronglyOrdered|FALSE|BOOLEAN|0x00000025\r | |
60 | gArmTokenSpaceGuid.PcdSkipPeiCore|FALSE|BOOLEAN|0x00000026\r | |
61 | \r | |
2ef2b01e | 62 | [PcdsFixedAtBuild.common]\r |
1bfda055 | 63 | # This PCD should be a FeaturePcd. But we used this PCD as an '#if' in an ASM file.\r |
64 | # Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.\r | |
65 | gArmTokenSpaceGuid.PcdVFPEnabled|0|UINT32|0x00000024\r | |
66 | \r | |
2ef2b01e A |
67 | gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000080000000|UINT64|0x00000002\r |
68 | gArmTokenSpaceGuid.PcdArmCacheOperationThreshold|1024|UINT32|0x00000003\r | |
5a4b8c6a | 69 | gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xffff0000|UINT32|0x00000004\r |
2ef2b01e | 70 | gArmTokenSpaceGuid.PcdCpuResetAddress|0x00000000|UINT32|0x00000005\r |
1bfda055 | 71 | \r |
72 | #\r | |
73 | # ARM PL180 MCI\r | |
74 | #\r | |
75 | gArmTokenSpaceGuid.PcdPL180SysMciRegAddress|0x00000000|UINT32|0x00000006\r | |
76 | gArmTokenSpaceGuid.PcdPL180MciBaseAddress|0x00000000|UINT32|0x00000007\r | |
77 | \r | |
78 | #\r | |
79 | # ARM PL390 General Interrupt Controller\r | |
80 | #\r | |
81 | gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT32|0x0000000C\r | |
82 | gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT32|0x0000000D\r | |
83 | gArmTokenSpaceGuid.PcdGicNumInterrupts|96|UINT32|0x00000023\r | |
84 | \r | |
85 | #\r | |
262a9b04 | 86 | # ARM Secure Firmware PCDs\r |
1bfda055 | 87 | #\r |
88 | gArmTokenSpaceGuid.PcdSecureFdBaseAddress|0|UINT32|0x00000015\r | |
89 | gArmTokenSpaceGuid.PcdSecureFdSize|0|UINT32|0x00000016\r | |
1ad14bc8 | 90 | gArmTokenSpaceGuid.PcdSecureFvBaseAddress|0x0|UINT32|0x0000002F\r |
91 | gArmTokenSpaceGuid.PcdSecureFvSize|0x0|UINT32|0x00000030\r | |
1bfda055 | 92 | \r |
262a9b04 | 93 | #\r |
94 | # ARM Normal (or Non Secure) Firmware PCDs\r | |
95 | #\r | |
96 | gArmTokenSpaceGuid.PcdNormalFdBaseAddress|0|UINT32|0x0000002B\r | |
97 | gArmTokenSpaceGuid.PcdNormalFdSize|0|UINT32|0x0000002C\r | |
1ad14bc8 | 98 | gArmTokenSpaceGuid.PcdNormalFvBaseAddress|0|UINT32|0x0000002D\r |
99 | gArmTokenSpaceGuid.PcdNormalFvSize|0|UINT32|0x0000002E\r | |
262a9b04 | 100 | \r |
964680c1 | 101 | # System Memory (DRAM): These PCDs define the region of in-built system memory\r |
102 | # Some platforms can get DRAM extensions, these additional regions will be declared\r | |
103 | # to UEFI by ArmPLatformPlib \r | |
104 | gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT32|0x00000029\r | |
105 | gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT32|0x0000002A\r | |
106 | \r | |
1bfda055 | 107 | #\r |
108 | # ARM MPCore MailBox PCDs\r | |
109 | #\r | |
110 | # Address to Set/Get to Mailbox in Multicore system\r | |
111 | gArmTokenSpaceGuid.PcdMPCoreMailboxSetAddress|0|UINT32|0x00000017\r | |
112 | gArmTokenSpaceGuid.PcdMPCoreMailboxGetAddress|0|UINT32|0x00000018\r | |
113 | # Address/Value to clear Mailbox in Multicore system\r | |
114 | gArmTokenSpaceGuid.PcdMPCoreMailboxClearAddress|0|UINT32|0x00000019\r | |
115 | gArmTokenSpaceGuid.PcdMPCoreMailboxClearValue|0|UINT32|0x0000001A\r | |
116 | \r | |
117 | #\r | |
118 | # ARM L2x0 PCDs\r | |
119 | #\r | |
120 | gArmTokenSpaceGuid.PcdL2x0ControllerBase|0|UINT32|0x0000001B\r | |
121 | \r | |
122 | #\r | |
123 | # ARM PL390 General Interrupt Controller\r | |
124 | #\r | |
125 | gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT32|0x0000001C\r | |
126 | gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT32|0x0000001D\r | |
127 | \r | |
128 | # \r | |
129 | # BdsLib\r | |
130 | #\r | |
131 | gArmTokenSpaceGuid.PcdArmMachineType|0|UINT32|0x0000001E\r | |
a355a365 | 132 | # The compressed Linux kernel is expected to be under 128MB from the beginning of the System Memory\r |
133 | gArmTokenSpaceGuid.PcdArmLinuxKernelMaxOffset|0x08000000|UINT32|0x0000001F\r | |
134 | # The Linux ATAGs are expected to be under 0x4000 (16KB) from the beginning of the System Memory\r | |
135 | gArmTokenSpaceGuid.PcdArmLinuxAtagMaxOffset|0x4000|UINT32|0x00000020\r | |
1bfda055 | 136 | \r |