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793ca69f OM |
1 | /** @file\r |
2 | *\r | |
3 | * Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r | |
4 | *\r | |
4059386c | 5 | * SPDX-License-Identifier: BSD-2-Clause-Patent\r |
793ca69f OM |
6 | *\r |
7 | **/\r | |
8 | \r | |
9 | #include <Uefi.h>\r | |
10 | #include <Library/IoLib.h>\r | |
11 | #include <Library/ArmGicLib.h>\r | |
12 | \r | |
793ca69f OM |
13 | VOID\r |
14 | EFIAPI\r | |
15 | ArmGicV2EnableInterruptInterface (\r | |
429309e0 | 16 | IN INTN GicInterruptInterfaceBase\r |
793ca69f OM |
17 | )\r |
18 | {\r | |
19 | /*\r | |
20 | * Enable the CPU interface in Non-Secure world\r | |
21 | * Note: The ICCICR register is banked when Security extensions are implemented\r | |
22 | */\r | |
23 | MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, 0x1);\r | |
24 | }\r | |
25 | \r | |
26 | VOID\r | |
27 | EFIAPI\r | |
28 | ArmGicV2DisableInterruptInterface (\r | |
429309e0 | 29 | IN INTN GicInterruptInterfaceBase\r |
793ca69f OM |
30 | )\r |
31 | {\r | |
32 | // Disable Gic Interface\r | |
33 | MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, 0x0);\r | |
34 | MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x0);\r | |
35 | }\r |