ArmPkg/ArmGicDxe: Fix double GIC EIOR write per interrupt

[mirror_edk2.git] / ArmPkg / Drivers / ArmGic / GicV2 / ArmGicV2SecLib.c

/** @file\r
*\r
*  Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
*\r
*  This program and the accompanying materials\r
*  are licensed and made available under the terms and conditions of the BSD License\r
*  which accompanies this distribution.  The full text of the license may be found at\r
*  http://opensource.org/licenses/bsd-license.php\r
*\r
*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
*\r
**/\r
\r
#include <Base.h>\r
#include <Library/ArmLib.h>\r
#include <Library/ArmPlatformLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/ArmGicLib.h>\r
\r
/*\r
 * This function configures the all interrupts to be Non-secure.\r
 *\r
 */\r
VOID\r
EFIAPI\r
ArmGicV2SetupNonSecure (\r
  IN  UINTN         MpId,\r
  IN  INTN          GicDistributorBase,\r
  IN  INTN          GicInterruptInterfaceBase\r
  )\r
{\r
  UINTN InterruptId;\r
  UINTN CachedPriorityMask;\r
  UINTN Index;\r
  UINTN MaxInterrupts;\r
\r
  CachedPriorityMask = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR);\r
\r
  // Set priority Mask so that no interrupts get through to CPU\r
  MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0);\r
\r
  InterruptId   = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);\r
  MaxInterrupts = ArmGicGetMaxNumInterrupts (GicDistributorBase);\r
\r
  // Only try to clear valid interrupts. Ignore spurious interrupts.\r
  while ((InterruptId & 0x3FF) < MaxInterrupts) {\r
    // Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal\r
    ArmGicEndOfInterrupt (GicInterruptInterfaceBase, InterruptId);\r
\r
    // Next\r
    InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);\r
  }\r
\r
  // Only the primary core should set the Non Secure bit to the SPIs (Shared Peripheral Interrupt).\r
  if (ArmPlatformIsPrimaryCore (MpId)) {\r
    // Ensure all GIC interrupts are Non-Secure\r
    for (Index = 0; Index < (MaxInterrupts / 32); Index++) {\r
      MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), 0xffffffff);\r
    }\r
  } else {\r
    // The secondary cores only set the Non Secure bit to their banked PPIs\r
    MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR, 0xffffffff);\r
  }\r
\r
  // Ensure all interrupts can get through the priority mask\r
  MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, CachedPriorityMask);\r
}\r
\r
VOID\r
EFIAPI\r
ArmGicV2EnableInterruptInterface (\r
  IN  INTN          GicInterruptInterfaceBase\r
  )\r
{\r
  // Set Priority Mask to allow interrupts\r
  MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x000000FF);\r
\r
  // Enable CPU interface in Secure world\r
  // Enable CPU interface in Non-secure World\r
  // Signal Secure Interrupts to CPU using FIQ line *\r
  MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR,\r
      ARM_GIC_ICCICR_ENABLE_SECURE |\r
      ARM_GIC_ICCICR_ENABLE_NS |\r
      ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ);\r
}\r
\r
VOID\r
EFIAPI\r
ArmGicV2DisableInterruptInterface (\r
  IN  INTN          GicInterruptInterfaceBase\r
  )\r
{\r
  UINT32    ControlValue;\r
\r
  // Disable CPU interface in Secure world and Non-secure World\r
  ControlValue = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR);\r
  MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, ControlValue & ~(ARM_GIC_ICCICR_ENABLE_SECURE | ARM_GIC_ICCICR_ENABLE_NS));\r
}\r