projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| d7133859 OM |
1 | #\r |
| 2 | # Copyright (c) 2014, ARM Limited. All rights reserved.\r | |
| 3 | #\r | |
| 4 | # This program and the accompanying materials are licensed and made available\r | |
| 5 | # under the terms and conditions of the BSD License which accompanies this\r | |
| 6 | # distribution. The full text of the license may be found at\r | |
| 7 | # http://opensource.org/licenses/bsd-license.php\r | |
| 8 | #\r | |
| 9 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 10 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 11 | #\r | |
| 12 | #\r | |
| 13 | \r | |
| 14 | #include <AsmMacroIoLib.h>\r | |
| 15 | #include <Library/ArmLib.h>\r | |
| 16 | \r | |
| 17 | // For the moment we assume this will run in SVC mode on ARMv7\r | |
| 18 | \r | |
| 19 | .text\r | |
| 20 | .align 2\r | |
| 21 | \r | |
| 5f81082e OM |
22 | GCC_ASM_EXPORT(ArmGicV3GetControlSystemRegisterEnable)\r |
| 23 | GCC_ASM_EXPORT(ArmGicV3SetControlSystemRegisterEnable)\r | |
| d7133859 OM |
24 | GCC_ASM_EXPORT(ArmGicV3EnableInterruptInterface)\r |
| 25 | GCC_ASM_EXPORT(ArmGicV3DisableInterruptInterface)\r | |
| 26 | GCC_ASM_EXPORT(ArmGicV3EndOfInterrupt)\r | |
| 27 | GCC_ASM_EXPORT(ArmGicV3AcknowledgeInterrupt)\r | |
| 28 | GCC_ASM_EXPORT(ArmGicV3SetPriorityMask)\r | |
| 29 | GCC_ASM_EXPORT(ArmGicV3SetBinaryPointer)\r | |
| 30 | \r | |
| 31 | //UINT32\r | |
| 32 | //EFIAPI\r | |
| 33 | //ArmGicGetControlSystemRegisterEnable (\r | |
| 34 | // VOID\r | |
| 35 | // );\r | |
| 5f81082e | 36 | ASM_PFX(ArmGicV3GetControlSystemRegisterEnable):\r |
| d7133859 OM |
37 | mrc p15, 0, r0, c12, c12, 5 // ICC_SRE\r |
| 38 | bx lr\r | |
| 39 | \r | |
| 40 | //VOID\r | |
| 41 | //EFIAPI\r | |
| 42 | //ArmGicSetControlSystemRegisterEnable (\r | |
| 43 | // IN UINT32 ControlSystemRegisterEnable\r | |
| 44 | // );\r | |
| 5f81082e | 45 | ASM_PFX(ArmGicV3SetControlSystemRegisterEnable):\r |
| d7133859 OM |
46 | mcr p15, 0, r0, c12, c12, 5 // ICC_SRE\r |
| 47 | isb\r | |
| 48 | bx lr\r | |
| 49 | \r | |
| 50 | //VOID\r | |
| 51 | //ArmGicV3EnableInterruptInterface (\r | |
| 52 | // VOID\r | |
| 53 | // );\r | |
| 54 | ASM_PFX(ArmGicV3EnableInterruptInterface):\r | |
| 55 | mov r0, #1\r | |
| 56 | mcr p15, 0, r0, c12, c12, 7 // ICC_IGRPEN1\r | |
| 57 | bx lr\r | |
| 58 | \r | |
| 59 | //VOID\r | |
| 60 | //ArmGicV3DisableInterruptInterface (\r | |
| 61 | // VOID\r | |
| 62 | // );\r | |
| 63 | ASM_PFX(ArmGicV3DisableInterruptInterface):\r | |
| 64 | mov r0, #0\r | |
| 65 | mcr p15, 0, r0, c12, c12, 7 // ICC_IGRPEN1\r | |
| 66 | bx lr\r | |
| 67 | \r | |
| 68 | //VOID\r | |
| 69 | //ArmGicV3EndOfInterrupt (\r | |
| 70 | // IN UINTN InterruptId\r | |
| 71 | // );\r | |
| 72 | ASM_PFX(ArmGicV3EndOfInterrupt):\r | |
| 73 | mcr p15, 0, r0, c12, c12, 1 //ICC_EOIR1\r | |
| 74 | bx lr\r | |
| 75 | \r | |
| 76 | //UINTN\r | |
| 77 | //ArmGicV3AcknowledgeInterrupt (\r | |
| 78 | // VOID\r | |
| 79 | // );\r | |
| 80 | ASM_PFX(ArmGicV3AcknowledgeInterrupt):\r | |
| 81 | mrc p15, 0, r0, c12, c8, 0 //ICC_IAR1\r | |
| 82 | bx lr\r | |
| 83 | \r | |
| 84 | //VOID\r | |
| 85 | //ArmGicV3SetPriorityMask (\r | |
| 86 | // IN UINTN Priority\r | |
| 87 | // );\r | |
| 88 | ASM_PFX(ArmGicV3SetPriorityMask):\r | |
| 89 | mcr p15, 0, r0, c4, c6, 0 //ICC_PMR\r | |
| 90 | bx lr\r | |
| 91 | \r | |
| 92 | //VOID\r | |
| 93 | //ArmGicV3SetBinaryPointer (\r | |
| 94 | // IN UINTN BinaryPoint\r | |
| 95 | // );\r | |
| 96 | ASM_PFX(ArmGicV3SetBinaryPointer):\r | |
| 97 | mcr p15, 0, r0, c12, c12, 3 //ICC_BPR1\r | |
| 98 | bx lr\r |