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5f81082e OM |
1 | /** @file\r |
2 | *\r | |
919697ae | 3 | * Copyright (c) 2011-2015, ARM Limited. All rights reserved.\r |
5f81082e OM |
4 | *\r |
5 | * This program and the accompanying materials\r | |
6 | * are licensed and made available under the terms and conditions of the BSD License\r | |
7 | * which accompanies this distribution. The full text of the license may be found at\r | |
8 | * http://opensource.org/licenses/bsd-license.php\r | |
9 | *\r | |
10 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | *\r | |
13 | **/\r | |
14 | \r | |
bce29e30 AB |
15 | #include <Library/ArmGicLib.h>\r |
16 | \r | |
5f81082e | 17 | #include "ArmGicDxe.h"\r |
5f81082e OM |
18 | \r |
19 | #define ARM_GIC_DEFAULT_PRIORITY 0x80\r | |
20 | \r | |
21 | extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV3Protocol;\r | |
22 | \r | |
23 | STATIC UINTN mGicDistributorBase;\r | |
919697ae | 24 | STATIC UINTN mGicRedistributorsBase;\r |
5f81082e OM |
25 | \r |
26 | /**\r | |
27 | Enable interrupt source Source.\r | |
28 | \r | |
29 | @param This Instance pointer for this protocol\r | |
30 | @param Source Hardware source of the interrupt\r | |
31 | \r | |
32 | @retval EFI_SUCCESS Source interrupt enabled.\r | |
33 | @retval EFI_DEVICE_ERROR Hardware could not be programmed.\r | |
34 | \r | |
35 | **/\r | |
36 | EFI_STATUS\r | |
37 | EFIAPI\r | |
38 | GicV3EnableInterruptSource (\r | |
39 | IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,\r | |
40 | IN HARDWARE_INTERRUPT_SOURCE Source\r | |
41 | )\r | |
42 | {\r | |
43 | if (Source > mGicNumInterrupts) {\r | |
44 | ASSERT(FALSE);\r | |
45 | return EFI_UNSUPPORTED;\r | |
46 | }\r | |
47 | \r | |
41fb5d46 | 48 | ArmGicEnableInterrupt (mGicDistributorBase, mGicRedistributorsBase, Source);\r |
5f81082e OM |
49 | \r |
50 | return EFI_SUCCESS;\r | |
51 | }\r | |
52 | \r | |
53 | /**\r | |
54 | Disable interrupt source Source.\r | |
55 | \r | |
56 | @param This Instance pointer for this protocol\r | |
57 | @param Source Hardware source of the interrupt\r | |
58 | \r | |
59 | @retval EFI_SUCCESS Source interrupt disabled.\r | |
60 | @retval EFI_DEVICE_ERROR Hardware could not be programmed.\r | |
61 | \r | |
62 | **/\r | |
63 | EFI_STATUS\r | |
64 | EFIAPI\r | |
65 | GicV3DisableInterruptSource (\r | |
66 | IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,\r | |
67 | IN HARDWARE_INTERRUPT_SOURCE Source\r | |
68 | )\r | |
69 | {\r | |
70 | if (Source > mGicNumInterrupts) {\r | |
71 | ASSERT(FALSE);\r | |
72 | return EFI_UNSUPPORTED;\r | |
73 | }\r | |
74 | \r | |
41fb5d46 | 75 | ArmGicDisableInterrupt (mGicDistributorBase, mGicRedistributorsBase, Source);\r |
5f81082e OM |
76 | \r |
77 | return EFI_SUCCESS;\r | |
78 | }\r | |
79 | \r | |
80 | /**\r | |
81 | Return current state of interrupt source Source.\r | |
82 | \r | |
83 | @param This Instance pointer for this protocol\r | |
84 | @param Source Hardware source of the interrupt\r | |
85 | @param InterruptState TRUE: source enabled, FALSE: source disabled.\r | |
86 | \r | |
87 | @retval EFI_SUCCESS InterruptState is valid\r | |
88 | @retval EFI_DEVICE_ERROR InterruptState is not valid\r | |
89 | \r | |
90 | **/\r | |
91 | EFI_STATUS\r | |
92 | EFIAPI\r | |
93 | GicV3GetInterruptSourceState (\r | |
94 | IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,\r | |
95 | IN HARDWARE_INTERRUPT_SOURCE Source,\r | |
96 | IN BOOLEAN *InterruptState\r | |
97 | )\r | |
98 | {\r | |
99 | if (Source > mGicNumInterrupts) {\r | |
100 | ASSERT(FALSE);\r | |
101 | return EFI_UNSUPPORTED;\r | |
102 | }\r | |
103 | \r | |
41fb5d46 | 104 | *InterruptState = ArmGicIsInterruptEnabled (mGicDistributorBase, mGicRedistributorsBase, Source);\r |
5f81082e OM |
105 | \r |
106 | return EFI_SUCCESS;\r | |
107 | }\r | |
108 | \r | |
109 | /**\r | |
110 | Signal to the hardware that the End Of Interrupt state\r | |
111 | has been reached.\r | |
112 | \r | |
113 | @param This Instance pointer for this protocol\r | |
114 | @param Source Hardware source of the interrupt\r | |
115 | \r | |
116 | @retval EFI_SUCCESS Source interrupt EOI'ed.\r | |
117 | @retval EFI_DEVICE_ERROR Hardware could not be programmed.\r | |
118 | \r | |
119 | **/\r | |
120 | EFI_STATUS\r | |
121 | EFIAPI\r | |
122 | GicV3EndOfInterrupt (\r | |
123 | IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,\r | |
124 | IN HARDWARE_INTERRUPT_SOURCE Source\r | |
125 | )\r | |
126 | {\r | |
127 | if (Source > mGicNumInterrupts) {\r | |
128 | ASSERT(FALSE);\r | |
129 | return EFI_UNSUPPORTED;\r | |
130 | }\r | |
131 | \r | |
132 | ArmGicV3EndOfInterrupt (Source);\r | |
133 | return EFI_SUCCESS;\r | |
134 | }\r | |
135 | \r | |
136 | /**\r | |
137 | EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs.\r | |
138 | \r | |
139 | @param InterruptType Defines the type of interrupt or exception that\r | |
140 | occurred on the processor.This parameter is processor architecture specific.\r | |
141 | @param SystemContext A pointer to the processor context when\r | |
142 | the interrupt occurred on the processor.\r | |
143 | \r | |
144 | @return None\r | |
145 | \r | |
146 | **/\r | |
147 | VOID\r | |
148 | EFIAPI\r | |
149 | GicV3IrqInterruptHandler (\r | |
150 | IN EFI_EXCEPTION_TYPE InterruptType,\r | |
151 | IN EFI_SYSTEM_CONTEXT SystemContext\r | |
152 | )\r | |
153 | {\r | |
154 | UINT32 GicInterrupt;\r | |
155 | HARDWARE_INTERRUPT_HANDLER InterruptHandler;\r | |
156 | \r | |
157 | GicInterrupt = ArmGicV3AcknowledgeInterrupt ();\r | |
158 | \r | |
159 | // Special Interrupts (ID1020-ID1023) have an Interrupt ID greater than the\r | |
160 | // number of interrupt (ie: Spurious interrupt).\r | |
161 | if ((GicInterrupt & ARM_GIC_ICCIAR_ACKINTID) >= mGicNumInterrupts) {\r | |
162 | // The special interrupt do not need to be acknowledge\r | |
163 | return;\r | |
164 | }\r | |
165 | \r | |
166 | InterruptHandler = gRegisteredInterruptHandlers[GicInterrupt];\r | |
167 | if (InterruptHandler != NULL) {\r | |
168 | // Call the registered interrupt handler.\r | |
169 | InterruptHandler (GicInterrupt, SystemContext);\r | |
170 | } else {\r | |
171 | DEBUG ((EFI_D_ERROR, "Spurious GIC interrupt: 0x%x\n", GicInterrupt));\r | |
172 | }\r | |
173 | \r | |
174 | GicV3EndOfInterrupt (&gHardwareInterruptV3Protocol, GicInterrupt);\r | |
175 | }\r | |
176 | \r | |
177 | //\r | |
178 | // The protocol instance produced by this driver\r | |
179 | //\r | |
180 | EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV3Protocol = {\r | |
181 | RegisterInterruptSource,\r | |
182 | GicV3EnableInterruptSource,\r | |
183 | GicV3DisableInterruptSource,\r | |
184 | GicV3GetInterruptSourceState,\r | |
185 | GicV3EndOfInterrupt\r | |
186 | };\r | |
187 | \r | |
188 | /**\r | |
189 | Shutdown our hardware\r | |
190 | \r | |
191 | DXE Core will disable interrupts and turn off the timer and disable interrupts\r | |
192 | after all the event handlers have run.\r | |
193 | \r | |
194 | @param[in] Event The Event that is being processed\r | |
195 | @param[in] Context Event Context\r | |
196 | **/\r | |
197 | VOID\r | |
198 | EFIAPI\r | |
199 | GicV3ExitBootServicesEvent (\r | |
200 | IN EFI_EVENT Event,\r | |
201 | IN VOID *Context\r | |
202 | )\r | |
203 | {\r | |
204 | UINTN Index;\r | |
205 | \r | |
206 | // Acknowledge all pending interrupts\r | |
207 | for (Index = 0; Index < mGicNumInterrupts; Index++) {\r | |
208 | GicV3DisableInterruptSource (&gHardwareInterruptV3Protocol, Index);\r | |
209 | }\r | |
210 | \r | |
211 | for (Index = 0; Index < mGicNumInterrupts; Index++) {\r | |
212 | GicV3EndOfInterrupt (&gHardwareInterruptV3Protocol, Index);\r | |
213 | }\r | |
214 | \r | |
215 | // Disable Gic Interface\r | |
216 | ArmGicV3DisableInterruptInterface ();\r | |
217 | \r | |
218 | // Disable Gic Distributor\r | |
219 | ArmGicDisableDistributor (mGicDistributorBase);\r | |
220 | }\r | |
221 | \r | |
222 | /**\r | |
223 | Initialize the state information for the CPU Architectural Protocol\r | |
224 | \r | |
225 | @param ImageHandle of the loaded driver\r | |
226 | @param SystemTable Pointer to the System Table\r | |
227 | \r | |
228 | @retval EFI_SUCCESS Protocol registered\r | |
229 | @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure\r | |
230 | @retval EFI_DEVICE_ERROR Hardware problems\r | |
231 | \r | |
232 | **/\r | |
233 | EFI_STATUS\r | |
234 | GicV3DxeInitialize (\r | |
235 | IN EFI_HANDLE ImageHandle,\r | |
236 | IN EFI_SYSTEM_TABLE *SystemTable\r | |
237 | )\r | |
238 | {\r | |
239 | EFI_STATUS Status;\r | |
240 | UINTN Index;\r | |
241 | UINT32 RegOffset;\r | |
242 | UINTN RegShift;\r | |
41fb5d46 OM |
243 | UINT64 CpuTarget;\r |
244 | UINT64 MpId;\r | |
5f81082e OM |
245 | \r |
246 | // Make sure the Interrupt Controller Protocol is not already installed in the system.\r | |
247 | ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid);\r | |
248 | \r | |
919697ae OM |
249 | mGicDistributorBase = PcdGet32 (PcdGicDistributorBase);\r |
250 | mGicRedistributorsBase = PcdGet32 (PcdGicRedistributorsBase);\r | |
251 | mGicNumInterrupts = ArmGicGetMaxNumInterrupts (mGicDistributorBase);\r | |
5f81082e | 252 | \r |
f6d46e29 AB |
253 | //\r |
254 | // We will be driving this GIC in native v3 mode, i.e., with Affinity\r | |
255 | // Routing enabled. So ensure that the ARE bit is set.\r | |
256 | //\r | |
257 | if (!FeaturePcdGet (PcdArmGicV3WithV2Legacy)) {\r | |
258 | MmioOr32 (mGicDistributorBase + ARM_GIC_ICDDCR, ARM_GIC_ICDDCR_ARE);\r | |
259 | }\r | |
260 | \r | |
5f81082e OM |
261 | for (Index = 0; Index < mGicNumInterrupts; Index++) {\r |
262 | GicV3DisableInterruptSource (&gHardwareInterruptV3Protocol, Index);\r | |
263 | \r | |
264 | // Set Priority\r | |
265 | RegOffset = Index / 4;\r | |
266 | RegShift = (Index % 4) * 8;\r | |
267 | MmioAndThenOr32 (\r | |
268 | mGicDistributorBase + ARM_GIC_ICDIPR + (4 * RegOffset),\r | |
269 | ~(0xff << RegShift),\r | |
270 | ARM_GIC_DEFAULT_PRIORITY << RegShift\r | |
271 | );\r | |
272 | }\r | |
273 | \r | |
274 | //\r | |
275 | // Targets the interrupts to the Primary Cpu\r | |
276 | //\r | |
277 | \r | |
152ac489 OM |
278 | if (FeaturePcdGet (PcdArmGicV3WithV2Legacy)) {\r |
279 | // Only Primary CPU will run this code. We can identify our GIC CPU ID by reading\r | |
280 | // the GIC Distributor Target register. The 8 first GICD_ITARGETSRn are banked to each\r | |
281 | // connected CPU. These 8 registers hold the CPU targets fields for interrupts 0-31.\r | |
282 | // More Info in the GIC Specification about "Interrupt Processor Targets Registers"\r | |
283 | //\r | |
284 | // Read the first Interrupt Processor Targets Register (that corresponds to the 4\r | |
285 | // first SGIs)\r | |
286 | CpuTarget = MmioRead32 (mGicDistributorBase + ARM_GIC_ICDIPTR);\r | |
287 | \r | |
288 | // The CPU target is a bit field mapping each CPU to a GIC CPU Interface. This value\r | |
289 | // is 0 when we run on a uniprocessor platform.\r | |
290 | if (CpuTarget != 0) {\r | |
291 | // The 8 first Interrupt Processor Targets Registers are read-only\r | |
292 | for (Index = 8; Index < (mGicNumInterrupts / 4); Index++) {\r | |
293 | MmioWrite32 (mGicDistributorBase + ARM_GIC_ICDIPTR + (Index * 4), CpuTarget);\r | |
294 | }\r | |
295 | }\r | |
296 | } else {\r | |
297 | MpId = ArmReadMpidr ();\r | |
298 | CpuTarget = MpId & (ARM_CORE_AFF0 | ARM_CORE_AFF1 | ARM_CORE_AFF2 | ARM_CORE_AFF3);\r | |
41fb5d46 | 299 | \r |
152ac489 OM |
300 | // Route the SPIs to the primary CPU. SPIs start at the INTID 32\r |
301 | for (Index = 0; Index < (mGicNumInterrupts - 32); Index++) {\r | |
302 | MmioWrite32 (mGicDistributorBase + ARM_GICD_IROUTER + (Index * 8), CpuTarget | ARM_GICD_IROUTER_IRM);\r | |
303 | }\r | |
5f81082e OM |
304 | }\r |
305 | \r | |
5f81082e OM |
306 | // Set binary point reg to 0x7 (no preemption)\r |
307 | ArmGicV3SetBinaryPointer (0x7);\r | |
308 | \r | |
309 | // Set priority mask reg to 0xff to allow all priorities through\r | |
310 | ArmGicV3SetPriorityMask (0xff);\r | |
311 | \r | |
312 | // Enable gic cpu interface\r | |
313 | ArmGicV3EnableInterruptInterface ();\r | |
314 | \r | |
315 | // Enable gic distributor\r | |
316 | ArmGicEnableDistributor (mGicDistributorBase);\r | |
317 | \r | |
318 | Status = InstallAndRegisterInterruptService (\r | |
319 | &gHardwareInterruptV3Protocol, GicV3IrqInterruptHandler, GicV3ExitBootServicesEvent);\r | |
320 | \r | |
321 | return Status;\r | |
322 | }\r |