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1 | /** @file\r |
2 | *\r | |
7c609a14 | 3 | * Copyright (c) 2013-2017, ARM Limited. All rights reserved.\r |
9f38945f | 4 | *\r |
4059386c | 5 | * SPDX-License-Identifier: BSD-2-Clause-Patent\r |
9f38945f OM |
6 | *\r |
7 | **/\r | |
8 | #ifndef __GENERIC_WATCHDOG_H__\r | |
9 | #define __GENERIC_WATCHDOG_H__\r | |
10 | \r | |
11 | // Refresh Frame:\r | |
7c609a14 | 12 | #define GENERIC_WDOG_REFRESH_REG ((UINTN)FixedPcdGet64 (PcdGenericWatchdogRefreshBase) + 0x000)\r |
9f38945f OM |
13 | \r |
14 | // Control Frame:\r | |
7c609a14 A |
15 | #define GENERIC_WDOG_CONTROL_STATUS_REG ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x000)\r |
16 | #define GENERIC_WDOG_OFFSET_REG ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x008)\r | |
dd4cae4d MW |
17 | #define GENERIC_WDOG_COMPARE_VALUE_REG_LOW ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x010)\r |
18 | #define GENERIC_WDOG_COMPARE_VALUE_REG_HIGH ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x014)\r | |
9f38945f OM |
19 | \r |
20 | // Values of bit 0 of the Control/Status Register\r | |
21 | #define GENERIC_WDOG_ENABLED 1\r | |
22 | #define GENERIC_WDOG_DISABLED 0\r | |
23 | \r | |
24 | #endif // __GENERIC_WATCHDOG_H__\r |