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1 | /** @file\r |
2 | \r | |
47d183db | 3 | Copyright (c) 2012-2014, ARM Limited. All rights reserved.\r |
25402f5d HL |
4 | \r |
5 | This program and the accompanying materials\r | |
6 | are licensed and made available under the terms and conditions of the BSD License\r | |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | **/\r | |
14 | \r | |
15 | #ifndef __ARM_CORTEX_A5x_H__\r | |
16 | #define __ARM_CORTEX_A5x_H__\r | |
17 | \r | |
18 | //\r | |
19 | // Cortex A5x feature bit definitions\r | |
20 | //\r | |
21 | #define A5X_FEATURE_SMP (1 << 6)\r | |
22 | \r | |
47d183db OM |
23 | //\r |
24 | // Helper functions to access CPU Extended Control Register\r | |
25 | //\r | |
26 | UINT64\r | |
27 | EFIAPI\r | |
28 | ArmReadCpuExCr (\r | |
29 | VOID\r | |
30 | );\r | |
31 | \r | |
32 | VOID\r | |
33 | EFIAPI\r | |
34 | ArmWriteCpuExCr (\r | |
35 | IN UINT64 Val\r | |
36 | );\r | |
37 | \r | |
38 | VOID\r | |
39 | EFIAPI\r | |
40 | ArmSetCpuExCrBit (\r | |
41 | IN UINT64 Bits\r | |
42 | );\r | |
43 | \r | |
44 | VOID\r | |
45 | EFIAPI\r | |
46 | ArmUnsetCpuExCrBit (\r | |
47 | IN UINT64 Bits\r | |
48 | );\r | |
49 | \r | |
25402f5d | 50 | #endif\r |