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1 | /** @file |
2 | ||
3 | Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR> | |
4 | ||
5 | All rights reserved. This program and the accompanying materials | |
6 | are licensed and made available under the terms and conditions of the BSD License | |
7 | which accompanies this distribution. The full text of the license may be found at | |
8 | http://opensource.org/licenses/bsd-license.php | |
9 | ||
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. | |
12 | ||
13 | **/ | |
14 | ||
15 | #ifndef __ARM_LIB__ | |
16 | #define __ARM_LIB__ | |
17 | ||
18 | typedef enum { | |
19 | ARM_CACHE_TYPE_WRITE_BACK, | |
20 | ARM_CACHE_TYPE_UNKNOWN | |
21 | } ARM_CACHE_TYPE; | |
22 | ||
23 | typedef enum { | |
24 | ARM_CACHE_ARCHITECTURE_UNIFIED, | |
25 | ARM_CACHE_ARCHITECTURE_SEPARATE, | |
26 | ARM_CACHE_ARCHITECTURE_UNKNOWN | |
27 | } ARM_CACHE_ARCHITECTURE; | |
28 | ||
29 | typedef struct { | |
30 | ARM_CACHE_TYPE Type; | |
31 | ARM_CACHE_ARCHITECTURE Architecture; | |
32 | BOOLEAN DataCachePresent; | |
33 | UINTN DataCacheSize; | |
34 | UINTN DataCacheAssociativity; | |
35 | UINTN DataCacheLineLength; | |
36 | BOOLEAN InstructionCachePresent; | |
37 | UINTN InstructionCacheSize; | |
38 | UINTN InstructionCacheAssociativity; | |
39 | UINTN InstructionCacheLineLength; | |
40 | } ARM_CACHE_INFO; | |
41 | ||
42 | typedef enum { | |
43 | ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED, | |
44 | ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK, | |
45 | ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH, | |
46 | ARM_MEMORY_REGION_ATTRIBUTE_DEVICE | |
47 | } ARM_MEMORY_REGION_ATTRIBUTES; | |
48 | ||
49 | typedef struct { | |
50 | UINT32 PhysicalBase; | |
51 | UINT32 VirtualBase; | |
52 | UINT32 Length; | |
53 | ARM_MEMORY_REGION_ATTRIBUTES Attributes; | |
54 | } ARM_MEMORY_REGION_DESCRIPTOR; | |
55 | ||
56 | typedef VOID (*CACHE_OPERATION)(VOID); | |
57 | typedef VOID (*LINE_OPERATION)(UINTN); | |
58 | ||
59 | typedef enum { | |
60 | ARM_PROCESSOR_MODE_USER = 0x10, | |
61 | ARM_PROCESSOR_MODE_FIQ = 0x11, | |
62 | ARM_PROCESSOR_MODE_IRQ = 0x12, | |
63 | ARM_PROCESSOR_MODE_SUPERVISOR = 0x13, | |
64 | ARM_PROCESSOR_MODE_ABORT = 0x17, | |
65 | ARM_PROCESSOR_MODE_UNDEFINED = 0x1B, | |
66 | ARM_PROCESSOR_MODE_SYSTEM = 0x1F, | |
67 | ARM_PROCESSOR_MODE_MASK = 0x1F | |
68 | } ARM_PROCESSOR_MODE; | |
69 | ||
70 | ARM_CACHE_TYPE | |
71 | EFIAPI | |
72 | ArmCacheType ( | |
73 | VOID | |
74 | ); | |
75 | ||
76 | ARM_CACHE_ARCHITECTURE | |
77 | EFIAPI | |
78 | ArmCacheArchitecture ( | |
79 | VOID | |
80 | ); | |
81 | ||
82 | VOID | |
83 | EFIAPI | |
84 | ArmCacheInformation ( | |
85 | OUT ARM_CACHE_INFO *CacheInfo | |
86 | ); | |
87 | ||
88 | BOOLEAN | |
89 | EFIAPI | |
90 | ArmDataCachePresent ( | |
91 | VOID | |
92 | ); | |
93 | ||
94 | UINTN | |
95 | EFIAPI | |
96 | ArmDataCacheSize ( | |
97 | VOID | |
98 | ); | |
99 | ||
100 | UINTN | |
101 | EFIAPI | |
102 | ArmDataCacheAssociativity ( | |
103 | VOID | |
104 | ); | |
105 | ||
106 | UINTN | |
107 | EFIAPI | |
108 | ArmDataCacheLineLength ( | |
109 | VOID | |
110 | ); | |
111 | ||
112 | BOOLEAN | |
113 | EFIAPI | |
114 | ArmInstructionCachePresent ( | |
115 | VOID | |
116 | ); | |
117 | ||
118 | UINTN | |
119 | EFIAPI | |
120 | ArmInstructionCacheSize ( | |
121 | VOID | |
122 | ); | |
123 | ||
124 | UINTN | |
125 | EFIAPI | |
126 | ArmInstructionCacheAssociativity ( | |
127 | VOID | |
128 | ); | |
129 | ||
130 | UINTN | |
131 | EFIAPI | |
132 | ArmInstructionCacheLineLength ( | |
133 | VOID | |
134 | ); | |
135 | ||
136 | UINT32 | |
137 | EFIAPI | |
138 | Cp15IdCode ( | |
139 | VOID | |
140 | ); | |
141 | ||
142 | UINT32 | |
143 | EFIAPI | |
144 | Cp15CacheInfo ( | |
145 | VOID | |
146 | ); | |
147 | ||
148 | VOID | |
149 | EFIAPI | |
150 | ArmInvalidateDataCache ( | |
151 | VOID | |
152 | ); | |
153 | ||
f45ce9d9 | 154 | |
2ef2b01e A |
155 | VOID |
156 | EFIAPI | |
157 | ArmCleanInvalidateDataCache ( | |
158 | VOID | |
159 | ); | |
160 | ||
161 | VOID | |
162 | EFIAPI | |
163 | ArmCleanDataCache ( | |
164 | VOID | |
165 | ); | |
166 | ||
167 | VOID | |
168 | EFIAPI | |
169 | ArmInvalidateInstructionCache ( | |
170 | VOID | |
171 | ); | |
172 | ||
173 | VOID | |
174 | EFIAPI | |
175 | ArmInvalidateDataCacheEntryByMVA ( | |
176 | IN UINTN Address | |
177 | ); | |
178 | ||
179 | VOID | |
180 | EFIAPI | |
181 | ArmCleanDataCacheEntryByMVA ( | |
182 | IN UINTN Address | |
183 | ); | |
184 | ||
185 | VOID | |
186 | EFIAPI | |
187 | ArmCleanInvalidateDataCacheEntryByMVA ( | |
188 | IN UINTN Address | |
189 | ); | |
190 | ||
191 | VOID | |
192 | EFIAPI | |
193 | ArmEnableDataCache ( | |
194 | VOID | |
195 | ); | |
196 | ||
197 | VOID | |
198 | EFIAPI | |
199 | ArmDisableDataCache ( | |
200 | VOID | |
201 | ); | |
202 | ||
203 | VOID | |
204 | EFIAPI | |
205 | ArmEnableInstructionCache ( | |
206 | VOID | |
207 | ); | |
208 | ||
209 | VOID | |
210 | EFIAPI | |
211 | ArmDisableInstructionCache ( | |
212 | VOID | |
213 | ); | |
214 | ||
215 | VOID | |
216 | EFIAPI | |
217 | ArmEnableMmu ( | |
218 | VOID | |
219 | ); | |
220 | ||
221 | VOID | |
222 | EFIAPI | |
223 | ArmDisableMmu ( | |
224 | VOID | |
225 | ); | |
226 | ||
227 | VOID | |
228 | EFIAPI | |
229 | ArmEnableInterrupts ( | |
230 | VOID | |
231 | ); | |
232 | ||
233 | UINTN | |
234 | EFIAPI | |
235 | ArmDisableInterrupts ( | |
236 | VOID | |
237 | ); | |
238 | ||
239 | BOOLEAN | |
240 | EFIAPI | |
241 | ArmGetInterruptState ( | |
242 | VOID | |
243 | ); | |
0416278c | 244 | VOID |
245 | EFIAPI | |
246 | ArmEnableFiq ( | |
247 | VOID | |
248 | ); | |
249 | ||
250 | UINTN | |
251 | EFIAPI | |
252 | ArmDisableFiq ( | |
253 | VOID | |
254 | ); | |
255 | ||
256 | BOOLEAN | |
257 | EFIAPI | |
258 | ArmGetFiqState ( | |
259 | VOID | |
260 | ); | |
2ef2b01e A |
261 | |
262 | VOID | |
263 | EFIAPI | |
264 | ArmInvalidateTlb ( | |
265 | VOID | |
266 | ); | |
267 | ||
6f72e28d | 268 | VOID |
269 | EFIAPI | |
270 | ArmUpdateTranslationTableEntry ( | |
271 | IN UINTN Mva | |
272 | ); | |
273 | ||
2ef2b01e A |
274 | VOID |
275 | EFIAPI | |
276 | ArmSetDomainAccessControl ( | |
277 | IN UINT32 Domain | |
278 | ); | |
279 | ||
280 | VOID | |
281 | EFIAPI | |
282 | ArmSetTranslationTableBaseAddress ( | |
283 | IN VOID *TranslationTableBase | |
284 | ); | |
285 | ||
f45ce9d9 A |
286 | VOID * |
287 | EFIAPI | |
288 | ArmGetTranslationTableBaseAddress ( | |
f659880b | 289 | VOID |
f45ce9d9 A |
290 | ); |
291 | ||
2ef2b01e A |
292 | VOID |
293 | EFIAPI | |
294 | ArmConfigureMmu ( | |
295 | IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable, | |
296 | OUT VOID **TranslationTableBase OPTIONAL, | |
297 | OUT UINTN *TranslationTableSize OPTIONAL | |
298 | ); | |
299 | ||
f45ce9d9 A |
300 | BOOLEAN |
301 | EFIAPI | |
302 | ArmMmuEnabled ( | |
303 | VOID | |
304 | ); | |
305 | ||
2ef2b01e A |
306 | VOID |
307 | EFIAPI | |
308 | ArmSwitchProcessorMode ( | |
309 | IN ARM_PROCESSOR_MODE Mode | |
310 | ); | |
311 | ||
312 | ARM_PROCESSOR_MODE | |
313 | EFIAPI | |
314 | ArmProcessorMode ( | |
315 | VOID | |
316 | ); | |
317 | ||
318 | VOID | |
319 | EFIAPI | |
320 | ArmEnableBranchPrediction ( | |
321 | VOID | |
322 | ); | |
323 | ||
324 | VOID | |
325 | EFIAPI | |
326 | ArmDisableBranchPrediction ( | |
327 | VOID | |
328 | ); | |
026c3d34 | 329 | |
330 | VOID | |
331 | EFIAPI | |
332 | ArmDataMemoryBarrier ( | |
333 | VOID | |
334 | ); | |
335 | ||
336 | VOID | |
337 | EFIAPI | |
338 | ArmDataSyncronizationBarrier ( | |
339 | VOID | |
340 | ); | |
341 | ||
342 | VOID | |
343 | EFIAPI | |
344 | ArmInstructionSynchronizationBarrier ( | |
345 | VOID | |
346 | ); | |
347 | ||
2ef2b01e | 348 | #endif // __ARM_LIB__ |