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2ef2b01e A |
1 | /** @file |
2 | ||
d6ebcab7 | 3 | Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> |
2ef2b01e | 4 | |
d6ebcab7 | 5 | This program and the accompanying materials |
2ef2b01e A |
6 | are licensed and made available under the terms and conditions of the BSD License |
7 | which accompanies this distribution. The full text of the license may be found at | |
8 | http://opensource.org/licenses/bsd-license.php | |
9 | ||
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. | |
12 | ||
13 | **/ | |
14 | ||
15 | #ifndef __ARM_LIB__ | |
16 | #define __ARM_LIB__ | |
17 | ||
916666c0 | 18 | #include <Uefi/UefiBaseType.h> |
19 | ||
bd6b9799 | 20 | #ifdef ARM_CPU_ARMv6 |
21 | #include <Chipset/ARM1176JZ-S.h> | |
22 | #else | |
23 | #include <Chipset/ArmV7.h> | |
24 | #endif | |
25 | ||
2ef2b01e A |
26 | typedef enum { |
27 | ARM_CACHE_TYPE_WRITE_BACK, | |
28 | ARM_CACHE_TYPE_UNKNOWN | |
29 | } ARM_CACHE_TYPE; | |
30 | ||
31 | typedef enum { | |
32 | ARM_CACHE_ARCHITECTURE_UNIFIED, | |
33 | ARM_CACHE_ARCHITECTURE_SEPARATE, | |
34 | ARM_CACHE_ARCHITECTURE_UNKNOWN | |
35 | } ARM_CACHE_ARCHITECTURE; | |
36 | ||
37 | typedef struct { | |
38 | ARM_CACHE_TYPE Type; | |
39 | ARM_CACHE_ARCHITECTURE Architecture; | |
40 | BOOLEAN DataCachePresent; | |
41 | UINTN DataCacheSize; | |
42 | UINTN DataCacheAssociativity; | |
43 | UINTN DataCacheLineLength; | |
44 | BOOLEAN InstructionCachePresent; | |
45 | UINTN InstructionCacheSize; | |
46 | UINTN InstructionCacheAssociativity; | |
47 | UINTN InstructionCacheLineLength; | |
48 | } ARM_CACHE_INFO; | |
49 | ||
50 | typedef enum { | |
1e6a5cfc | 51 | ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0, |
1bfda055 | 52 | ARM_MEMORY_REGION_ATTRIBUTE_SECURE_UNCACHED_UNBUFFERED, |
1e6a5cfc | 53 | ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK, |
1bfda055 | 54 | ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_BACK, |
1e6a5cfc | 55 | ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH, |
1bfda055 | 56 | ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_THROUGH, |
1e6a5cfc | 57 | ARM_MEMORY_REGION_ATTRIBUTE_DEVICE, |
1bfda055 | 58 | ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE |
2ef2b01e A |
59 | } ARM_MEMORY_REGION_ATTRIBUTES; |
60 | ||
1e6a5cfc | 61 | #define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1) |
62 | ||
2ef2b01e | 63 | typedef struct { |
916666c0 | 64 | EFI_PHYSICAL_ADDRESS PhysicalBase; |
65 | EFI_VIRTUAL_ADDRESS VirtualBase; | |
3b73c91b | 66 | UINTN Length; |
2ef2b01e A |
67 | ARM_MEMORY_REGION_ATTRIBUTES Attributes; |
68 | } ARM_MEMORY_REGION_DESCRIPTOR; | |
69 | ||
70 | typedef VOID (*CACHE_OPERATION)(VOID); | |
71 | typedef VOID (*LINE_OPERATION)(UINTN); | |
72 | ||
73 | typedef enum { | |
74 | ARM_PROCESSOR_MODE_USER = 0x10, | |
75 | ARM_PROCESSOR_MODE_FIQ = 0x11, | |
76 | ARM_PROCESSOR_MODE_IRQ = 0x12, | |
77 | ARM_PROCESSOR_MODE_SUPERVISOR = 0x13, | |
78 | ARM_PROCESSOR_MODE_ABORT = 0x17, | |
0e9674e5 | 79 | ARM_PROCESSOR_MODE_HYP = 0x1A, |
2ef2b01e A |
80 | ARM_PROCESSOR_MODE_UNDEFINED = 0x1B, |
81 | ARM_PROCESSOR_MODE_SYSTEM = 0x1F, | |
82 | ARM_PROCESSOR_MODE_MASK = 0x1F | |
83 | } ARM_PROCESSOR_MODE; | |
84 | ||
0787bc61 | 85 | #define IS_PRIMARY_CORE(MpId) (((MpId) & PcdGet32(PcdArmPrimaryCoreMask)) == PcdGet32(PcdArmPrimaryCore)) |
69f60552 | 86 | #define GET_CORE_ID(MpId) ((MpId) & 0xFF) |
87 | #define GET_CLUSTER_ID(MpId) (((MpId) >> 8) & 0xFF) | |
0787bc61 | 88 | // Get the position of the core for the Stack Offset (4 Core per Cluster) |
89 | // Position = (ClusterId * 4) + CoreId | |
69f60552 | 90 | #define GET_CORE_POS(MpId) ((((MpId) >> 6) & 0xFF) + ((MpId) & 0xFF)) |
91 | #define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & 0xFF) | |
0787bc61 | 92 | |
2ef2b01e A |
93 | ARM_CACHE_TYPE |
94 | EFIAPI | |
95 | ArmCacheType ( | |
96 | VOID | |
97 | ); | |
98 | ||
99 | ARM_CACHE_ARCHITECTURE | |
100 | EFIAPI | |
101 | ArmCacheArchitecture ( | |
102 | VOID | |
103 | ); | |
104 | ||
105 | VOID | |
106 | EFIAPI | |
107 | ArmCacheInformation ( | |
108 | OUT ARM_CACHE_INFO *CacheInfo | |
109 | ); | |
110 | ||
111 | BOOLEAN | |
112 | EFIAPI | |
113 | ArmDataCachePresent ( | |
114 | VOID | |
115 | ); | |
116 | ||
117 | UINTN | |
118 | EFIAPI | |
119 | ArmDataCacheSize ( | |
120 | VOID | |
121 | ); | |
122 | ||
123 | UINTN | |
124 | EFIAPI | |
125 | ArmDataCacheAssociativity ( | |
126 | VOID | |
127 | ); | |
128 | ||
129 | UINTN | |
130 | EFIAPI | |
131 | ArmDataCacheLineLength ( | |
132 | VOID | |
133 | ); | |
134 | ||
135 | BOOLEAN | |
136 | EFIAPI | |
137 | ArmInstructionCachePresent ( | |
138 | VOID | |
139 | ); | |
140 | ||
141 | UINTN | |
142 | EFIAPI | |
143 | ArmInstructionCacheSize ( | |
144 | VOID | |
145 | ); | |
146 | ||
147 | UINTN | |
148 | EFIAPI | |
149 | ArmInstructionCacheAssociativity ( | |
150 | VOID | |
151 | ); | |
152 | ||
153 | UINTN | |
154 | EFIAPI | |
155 | ArmInstructionCacheLineLength ( | |
156 | VOID | |
157 | ); | |
158 | ||
159 | UINT32 | |
160 | EFIAPI | |
161 | Cp15IdCode ( | |
162 | VOID | |
163 | ); | |
164 | ||
165 | UINT32 | |
166 | EFIAPI | |
167 | Cp15CacheInfo ( | |
168 | VOID | |
169 | ); | |
170 | ||
1bfda055 | 171 | BOOLEAN |
172 | EFIAPI | |
da9675a2 | 173 | ArmIsMpCore ( |
1bfda055 | 174 | VOID |
175 | ); | |
176 | ||
2ef2b01e A |
177 | VOID |
178 | EFIAPI | |
179 | ArmInvalidateDataCache ( | |
180 | VOID | |
181 | ); | |
182 | ||
f45ce9d9 | 183 | |
2ef2b01e A |
184 | VOID |
185 | EFIAPI | |
186 | ArmCleanInvalidateDataCache ( | |
187 | VOID | |
188 | ); | |
189 | ||
190 | VOID | |
191 | EFIAPI | |
192 | ArmCleanDataCache ( | |
193 | VOID | |
194 | ); | |
195 | ||
d60f6af4 | 196 | VOID |
197 | EFIAPI | |
198 | ArmCleanDataCacheToPoU ( | |
199 | VOID | |
200 | ); | |
201 | ||
2ef2b01e A |
202 | VOID |
203 | EFIAPI | |
204 | ArmInvalidateInstructionCache ( | |
205 | VOID | |
206 | ); | |
207 | ||
208 | VOID | |
209 | EFIAPI | |
210 | ArmInvalidateDataCacheEntryByMVA ( | |
211 | IN UINTN Address | |
212 | ); | |
213 | ||
214 | VOID | |
215 | EFIAPI | |
216 | ArmCleanDataCacheEntryByMVA ( | |
217 | IN UINTN Address | |
218 | ); | |
219 | ||
220 | VOID | |
221 | EFIAPI | |
222 | ArmCleanInvalidateDataCacheEntryByMVA ( | |
223 | IN UINTN Address | |
224 | ); | |
225 | ||
226 | VOID | |
227 | EFIAPI | |
228 | ArmEnableDataCache ( | |
229 | VOID | |
230 | ); | |
231 | ||
232 | VOID | |
233 | EFIAPI | |
234 | ArmDisableDataCache ( | |
235 | VOID | |
236 | ); | |
237 | ||
238 | VOID | |
239 | EFIAPI | |
240 | ArmEnableInstructionCache ( | |
241 | VOID | |
242 | ); | |
243 | ||
244 | VOID | |
245 | EFIAPI | |
246 | ArmDisableInstructionCache ( | |
247 | VOID | |
248 | ); | |
249 | ||
250 | VOID | |
251 | EFIAPI | |
252 | ArmEnableMmu ( | |
253 | VOID | |
254 | ); | |
255 | ||
256 | VOID | |
257 | EFIAPI | |
258 | ArmDisableMmu ( | |
259 | VOID | |
260 | ); | |
261 | ||
1bfda055 | 262 | VOID |
263 | EFIAPI | |
264 | ArmDisableCachesAndMmu ( | |
265 | VOID | |
266 | ); | |
267 | ||
bd6b9799 | 268 | VOID |
269 | EFIAPI | |
270 | ArmInvalidateInstructionAndDataTlb ( | |
271 | VOID | |
272 | ); | |
273 | ||
2ef2b01e A |
274 | VOID |
275 | EFIAPI | |
276 | ArmEnableInterrupts ( | |
277 | VOID | |
278 | ); | |
279 | ||
280 | UINTN | |
281 | EFIAPI | |
282 | ArmDisableInterrupts ( | |
283 | VOID | |
284 | ); | |
285 | ||
286 | BOOLEAN | |
287 | EFIAPI | |
288 | ArmGetInterruptState ( | |
289 | VOID | |
290 | ); | |
1bfda055 | 291 | |
0416278c | 292 | VOID |
293 | EFIAPI | |
294 | ArmEnableFiq ( | |
295 | VOID | |
296 | ); | |
297 | ||
298 | UINTN | |
299 | EFIAPI | |
300 | ArmDisableFiq ( | |
301 | VOID | |
302 | ); | |
303 | ||
304 | BOOLEAN | |
305 | EFIAPI | |
306 | ArmGetFiqState ( | |
307 | VOID | |
308 | ); | |
2ef2b01e A |
309 | |
310 | VOID | |
311 | EFIAPI | |
312 | ArmInvalidateTlb ( | |
313 | VOID | |
314 | ); | |
315 | ||
6f72e28d | 316 | VOID |
317 | EFIAPI | |
318 | ArmUpdateTranslationTableEntry ( | |
bb02cb80 | 319 | IN VOID *TranslationTableEntry, |
320 | IN VOID *Mva | |
6f72e28d | 321 | ); |
322 | ||
2ef2b01e A |
323 | VOID |
324 | EFIAPI | |
325 | ArmSetDomainAccessControl ( | |
326 | IN UINT32 Domain | |
327 | ); | |
328 | ||
329 | VOID | |
330 | EFIAPI | |
1bfda055 | 331 | ArmSetTTBR0 ( |
2ef2b01e A |
332 | IN VOID *TranslationTableBase |
333 | ); | |
334 | ||
f45ce9d9 A |
335 | VOID * |
336 | EFIAPI | |
1bfda055 | 337 | ArmGetTTBR0BaseAddress ( |
f659880b | 338 | VOID |
f45ce9d9 A |
339 | ); |
340 | ||
2ef2b01e A |
341 | VOID |
342 | EFIAPI | |
343 | ArmConfigureMmu ( | |
344 | IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable, | |
345 | OUT VOID **TranslationTableBase OPTIONAL, | |
346 | OUT UINTN *TranslationTableSize OPTIONAL | |
347 | ); | |
348 | ||
f45ce9d9 A |
349 | BOOLEAN |
350 | EFIAPI | |
351 | ArmMmuEnabled ( | |
352 | VOID | |
353 | ); | |
354 | ||
2ef2b01e A |
355 | VOID |
356 | EFIAPI | |
357 | ArmSwitchProcessorMode ( | |
358 | IN ARM_PROCESSOR_MODE Mode | |
359 | ); | |
360 | ||
361 | ARM_PROCESSOR_MODE | |
362 | EFIAPI | |
363 | ArmProcessorMode ( | |
364 | VOID | |
365 | ); | |
366 | ||
367 | VOID | |
368 | EFIAPI | |
369 | ArmEnableBranchPrediction ( | |
370 | VOID | |
371 | ); | |
372 | ||
373 | VOID | |
374 | EFIAPI | |
375 | ArmDisableBranchPrediction ( | |
376 | VOID | |
377 | ); | |
f0fef790 | 378 | |
379 | VOID | |
380 | EFIAPI | |
381 | ArmSetLowVectors ( | |
382 | VOID | |
383 | ); | |
384 | ||
385 | VOID | |
386 | EFIAPI | |
387 | ArmSetHighVectors ( | |
388 | VOID | |
389 | ); | |
390 | ||
026c3d34 | 391 | VOID |
392 | EFIAPI | |
393 | ArmDataMemoryBarrier ( | |
394 | VOID | |
395 | ); | |
396 | ||
397 | VOID | |
398 | EFIAPI | |
399 | ArmDataSyncronizationBarrier ( | |
400 | VOID | |
401 | ); | |
402 | ||
403 | VOID | |
404 | EFIAPI | |
405 | ArmInstructionSynchronizationBarrier ( | |
406 | VOID | |
407 | ); | |
bd6b9799 | 408 | |
409 | VOID | |
410 | EFIAPI | |
411 | ArmWriteVBar ( | |
412 | IN UINT32 VectorBase | |
413 | ); | |
414 | ||
415 | UINT32 | |
416 | EFIAPI | |
417 | ArmReadVBar ( | |
418 | VOID | |
419 | ); | |
420 | ||
421 | VOID | |
422 | EFIAPI | |
423 | ArmWriteAuxCr ( | |
424 | IN UINT32 Bit | |
425 | ); | |
426 | ||
427 | UINT32 | |
428 | EFIAPI | |
429 | ArmReadAuxCr ( | |
430 | VOID | |
431 | ); | |
432 | ||
433 | VOID | |
434 | EFIAPI | |
435 | ArmSetAuxCrBit ( | |
436 | IN UINT32 Bits | |
437 | ); | |
438 | ||
439 | VOID | |
440 | EFIAPI | |
441 | ArmCallWFI ( | |
442 | VOID | |
443 | ); | |
444 | ||
445 | UINTN | |
446 | EFIAPI | |
447 | ArmReadMpidr ( | |
448 | VOID | |
449 | ); | |
450 | ||
451 | VOID | |
452 | EFIAPI | |
453 | ArmWriteCPACR ( | |
454 | IN UINT32 Access | |
455 | ); | |
456 | ||
457 | VOID | |
458 | EFIAPI | |
459 | ArmEnableVFP ( | |
460 | VOID | |
461 | ); | |
462 | ||
463 | VOID | |
464 | EFIAPI | |
465 | ArmWriteNsacr ( | |
466 | IN UINT32 SetWayFormat | |
467 | ); | |
468 | ||
469 | VOID | |
470 | EFIAPI | |
471 | ArmWriteScr ( | |
472 | IN UINT32 SetWayFormat | |
473 | ); | |
474 | ||
475 | VOID | |
476 | EFIAPI | |
477 | ArmWriteVMBar ( | |
478 | IN UINT32 VectorMonitorBase | |
479 | ); | |
bb02cb80 | 480 | |
2ef2b01e | 481 | #endif // __ARM_LIB__ |