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1bfda055 | 1 | /** @file\r |
2 | *\r | |
3 | * Copyright (c) 2011, ARM Limited. All rights reserved.\r | |
4 | *\r | |
5 | * This program and the accompanying materials\r | |
6 | * are licensed and made available under the terms and conditions of the BSD License\r | |
7 | * which accompanies this distribution. The full text of the license may be found at\r | |
8 | * http://opensource.org/licenses/bsd-license.php\r | |
9 | *\r | |
10 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | *\r | |
13 | **/\r | |
14 | \r | |
15 | #ifndef L2CACHELIB_H_\r | |
16 | #define L2CACHELIB_H_\r | |
17 | \r | |
18 | #define L2_LATENCY 7\r | |
19 | \r | |
20 | #define L2_TAG_ACCESS_LATENCY L2_LATENCY\r | |
21 | #define L2_TAG_SETUP_LATENCY L2_LATENCY\r | |
22 | #define L2_DATA_ACCESS_LATENCY L2_LATENCY\r | |
23 | #define L2_DATA_SETUP_LATENCY L2_LATENCY\r | |
24 | \r | |
25 | \r | |
26 | #define L2X0_CACHEID 0x000\r | |
27 | #define L2X0_CTRL 0x100\r | |
28 | #define L2X0_AUXCTRL 0x104\r | |
29 | #define L230_TAG_LATENCY 0x108\r | |
30 | #define L230_DATA_LATENCY 0x10C\r | |
31 | #define L2X0_INTCLEAR 0x220\r | |
32 | #define L2X0_CACHE_SYNC 0x730\r | |
33 | #define L2X0_INVWAY 0x77C\r | |
34 | #define L2X0_CLEAN_WAY 0x7BC\r | |
35 | #define L2X0_PFCTRL 0xF60\r | |
36 | #define L2X0_PWRCTRL 0xF80\r | |
37 | \r | |
38 | #define L2X0_CACHEID_IMPLEMENTER_ARM 0x41\r | |
39 | #define L2X0_CACHEID_PARTNUM_PL310 0x03\r | |
40 | \r | |
41 | #define L2X0_CTRL_ENABLED 0x1\r | |
42 | #define L2X0_CTRL_DISABLED 0x0\r | |
43 | \r | |
44 | #define L2X0_AUXCTRL_EXCLUSIVE (1<<12)\r | |
45 | #define L2X0_AUXCTRL_WAYSIZE_16KB (0x001 << 17)\r | |
46 | #define L2X0_AUXCTRL_WAYSIZE_32KB (0x010 << 17)\r | |
47 | #define L2X0_AUXCTRL_WAYSIZE_64KB (0x011 << 17)\r | |
48 | #define L2X0_AUXCTRL_WAYSIZE_128KB (0x100 << 17)\r | |
49 | #define L2X0_AUXCTRL_WAYSIZE_256KB (0x101 << 17)\r | |
50 | #define L2X0_AUXCTRL_WAYSIZE_512KB (0x110 << 17)\r | |
51 | #define L2X0_AUXCTRL_EM (1 << 20)\r | |
52 | #define L2x0_AUXCTRL_AW_AWCACHE (0x00 << 23)\r | |
53 | #define L2x0_AUXCTRL_AW_NOALLOC (0x01 << 23)\r | |
54 | #define L2x0_AUXCTRL_AW_OVERRIDE (0x10 << 23)\r | |
55 | #define L2X0_AUXCTRL_SBO (1 << 25)\r | |
56 | #define L2X0_AUXCTRL_NSAC (1 << 27)\r | |
57 | #define L2x0_AUXCTRL_DPREFETCH (1 << 28)\r | |
58 | #define L2x0_AUXCTRL_IPREFETCH (1 << 29)\r | |
59 | \r | |
60 | VOID L2x0CacheInit(UINTN L2x0Base, BOOLEAN CacheEnabled);\r | |
61 | \r | |
62 | #endif /* L2CACHELIB_H_ */\r |