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da9675a2 | 1 | /** @file\r |
2 | Generic ARM implementation of TimerLib.h\r | |
3 | \r | |
27331bff OM |
4 | Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r |
5 | \r | |
da9675a2 | 6 | This program and the accompanying materials\r |
7 | are licensed and made available under the terms and conditions of the BSD License\r | |
8 | which accompanies this distribution. The full text of the license may be found at\r | |
9 | http://opensource.org/licenses/bsd-license.php\r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | \r | |
14 | **/\r | |
15 | \r | |
16 | \r | |
17 | #include <Base.h>\r | |
168d7245 | 18 | #include <Library/ArmLib.h>\r |
da9675a2 | 19 | #include <Library/BaseLib.h>\r |
20 | #include <Library/TimerLib.h>\r | |
21 | #include <Library/DebugLib.h>\r | |
22 | #include <Library/PcdLib.h>\r | |
25402f5d | 23 | #include <Library/ArmArchTimerLib.h>\r |
da9675a2 | 24 | \r |
25 | #define TICKS_PER_MICRO_SEC (PcdGet32 (PcdArmArchTimerFreqInHz)/1000000U)\r | |
26 | \r | |
27 | RETURN_STATUS\r | |
28 | EFIAPI\r | |
31d196c1 | 29 | TimerConstructor (\r |
da9675a2 | 30 | VOID\r |
31 | )\r | |
32 | {\r | |
33 | // Check if the ARM Generic Timer Extension is implemented\r | |
34 | if (ArmIsArchTimerImplemented ()) {\r | |
35 | \r | |
36 | UINTN TimerFreq;\r | |
37 | \r | |
38 | // Check if Architectural Timer frequency is valid number (should not be 0)\r | |
39 | ASSERT (PcdGet32 (PcdArmArchTimerFreqInHz));\r | |
40 | \r | |
41 | // Check if ticks/uS is not 0. The Architectural timer runs at constant\r | |
42 | // frequency irrespective of CPU frequency. According to General Timer Ref\r | |
43 | // manual lower bound of the frequency is in the range of 1-10MHz\r | |
44 | ASSERT (TICKS_PER_MICRO_SEC);\r | |
45 | \r | |
25402f5d HL |
46 | #ifdef MDE_CPU_ARM\r |
47 | // Only set the frequency for ARMv7. We expect the secure firmware to have already do it\r | |
da9675a2 | 48 | // If the security extensions are not implemented set Timer Frequency\r |
27331bff | 49 | if ((ArmReadIdPfr1 () & ARM_PFR1_SEC) == 0x0) {\r |
da9675a2 | 50 | ArmArchTimerSetTimerFreq (PcdGet32 (PcdArmArchTimerFreqInHz));\r |
51 | }\r | |
25402f5d | 52 | #endif\r |
da9675a2 | 53 | \r |
54 | // Architectural Timer Frequency must be set in the Secure privileged(if secure extensions are supported) mode.\r | |
55 | // If the reset value (0) is returned just ASSERT.\r | |
56 | TimerFreq = ArmArchTimerGetTimerFreq ();\r | |
25402f5d | 57 | ASSERT (TimerFreq != 0);\r |
da9675a2 | 58 | \r |
59 | } else {\r | |
ce88684e | 60 | DEBUG ((EFI_D_ERROR, "ARM Architectural Timer is not available in the CPU, hence this library can not be used.\n"));\r |
da9675a2 | 61 | ASSERT (0);\r |
62 | }\r | |
63 | \r | |
64 | return RETURN_SUCCESS;\r | |
65 | }\r | |
66 | \r | |
67 | \r | |
68 | /**\r | |
69 | Stalls the CPU for the number of microseconds specified by MicroSeconds.\r | |
70 | \r | |
71 | @param MicroSeconds The minimum number of microseconds to delay.\r | |
72 | \r | |
73 | @return The value of MicroSeconds inputted.\r | |
74 | \r | |
75 | **/\r | |
76 | UINTN\r | |
77 | EFIAPI\r | |
78 | MicroSecondDelay (\r | |
79 | IN UINTN MicroSeconds\r | |
80 | )\r | |
81 | {\r | |
82 | UINT64 TimerTicks64;\r | |
83 | UINT64 SystemCounterVal;\r | |
84 | \r | |
33292af5 OM |
85 | // Calculate counter ticks that can represent requested delay:\r |
86 | // = MicroSeconds x TICKS_PER_MICRO_SEC\r | |
87 | // = MicroSeconds x Frequency.10^-6\r | |
88 | TimerTicks64 = (MicroSeconds * PcdGet32 (PcdArmArchTimerFreqInHz)) / 1000000U;\r | |
da9675a2 | 89 | \r |
90 | // Read System Counter value\r | |
91 | SystemCounterVal = ArmArchTimerGetSystemCount ();\r | |
92 | \r | |
93 | TimerTicks64 += SystemCounterVal;\r | |
94 | \r | |
95 | // Wait until delay count is expired.\r | |
96 | while (SystemCounterVal < TimerTicks64) {\r | |
97 | SystemCounterVal = ArmArchTimerGetSystemCount ();\r | |
98 | }\r | |
99 | \r | |
100 | return MicroSeconds;\r | |
101 | }\r | |
102 | \r | |
103 | \r | |
104 | /**\r | |
105 | Stalls the CPU for at least the given number of nanoseconds.\r | |
106 | \r | |
107 | Stalls the CPU for the number of nanoseconds specified by NanoSeconds.\r | |
108 | \r | |
109 | When the timer frequency is 1MHz, each tick corresponds to 1 microsecond.\r | |
110 | Therefore, the nanosecond delay will be rounded up to the nearest 1 microsecond.\r | |
111 | \r | |
112 | @param NanoSeconds The minimum number of nanoseconds to delay.\r | |
113 | \r | |
ce88684e | 114 | @return The value of NanoSeconds inputed.\r |
da9675a2 | 115 | \r |
116 | **/\r | |
117 | UINTN\r | |
118 | EFIAPI\r | |
119 | NanoSecondDelay (\r | |
120 | IN UINTN NanoSeconds\r | |
121 | )\r | |
122 | {\r | |
123 | UINTN MicroSeconds;\r | |
124 | \r | |
125 | // Round up to 1us Tick Number\r | |
126 | MicroSeconds = NanoSeconds / 1000;\r | |
127 | MicroSeconds += ((NanoSeconds % 1000) == 0) ? 0 : 1;\r | |
128 | \r | |
129 | MicroSecondDelay (MicroSeconds);\r | |
130 | \r | |
131 | return NanoSeconds;\r | |
132 | }\r | |
133 | \r | |
134 | /**\r | |
135 | Retrieves the current value of a 64-bit free running performance counter.\r | |
136 | \r | |
137 | The counter can either count up by 1 or count down by 1. If the physical\r | |
138 | performance counter counts by a larger increment, then the counter values\r | |
139 | must be translated. The properties of the counter can be retrieved from\r | |
140 | GetPerformanceCounterProperties().\r | |
141 | \r | |
142 | @return The current value of the free running performance counter.\r | |
143 | \r | |
144 | **/\r | |
145 | UINT64\r | |
146 | EFIAPI\r | |
147 | GetPerformanceCounter (\r | |
148 | VOID\r | |
149 | )\r | |
150 | {\r | |
151 | // Just return the value of system count\r | |
152 | return ArmArchTimerGetSystemCount ();\r | |
153 | }\r | |
154 | \r | |
155 | /**\r | |
156 | Retrieves the 64-bit frequency in Hz and the range of performance counter\r | |
157 | values.\r | |
158 | \r | |
159 | If StartValue is not NULL, then the value that the performance counter starts\r | |
160 | with immediately after is it rolls over is returned in StartValue. If\r | |
161 | EndValue is not NULL, then the value that the performance counter end with\r | |
162 | immediately before it rolls over is returned in EndValue. The 64-bit\r | |
163 | frequency of the performance counter in Hz is always returned. If StartValue\r | |
164 | is less than EndValue, then the performance counter counts up. If StartValue\r | |
165 | is greater than EndValue, then the performance counter counts down. For\r | |
166 | example, a 64-bit free running counter that counts up would have a StartValue\r | |
167 | of 0 and an EndValue of 0xFFFFFFFFFFFFFFFF. A 24-bit free running counter\r | |
168 | that counts down would have a StartValue of 0xFFFFFF and an EndValue of 0.\r | |
169 | \r | |
170 | @param StartValue The value the performance counter starts with when it\r | |
171 | rolls over.\r | |
172 | @param EndValue The value that the performance counter ends with before\r | |
173 | it rolls over.\r | |
174 | \r | |
175 | @return The frequency in Hz.\r | |
176 | \r | |
177 | **/\r | |
178 | UINT64\r | |
179 | EFIAPI\r | |
180 | GetPerformanceCounterProperties (\r | |
181 | OUT UINT64 *StartValue, OPTIONAL\r | |
182 | OUT UINT64 *EndValue OPTIONAL\r | |
183 | )\r | |
184 | {\r | |
185 | if (StartValue != NULL) {\r | |
186 | // Timer starts with the reload value\r | |
187 | *StartValue = (UINT64)0ULL ;\r | |
188 | }\r | |
189 | \r | |
190 | if (EndValue != NULL) {\r | |
191 | // Timer counts down to 0x0\r | |
89bbce11 | 192 | *EndValue = 0xFFFFFFFFFFFFFFFFUL;\r |
da9675a2 | 193 | }\r |
194 | \r | |
195 | return (UINT64)ArmArchTimerGetTimerFreq ();\r | |
196 | }\r |