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1 | /** @file\r |
2 | \r | |
3 | Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r | |
01674afd | 4 | Portions copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>\r |
25402f5d HL |
5 | \r |
6 | This program and the accompanying materials\r | |
7 | are licensed and made available under the terms and conditions of the BSD License\r | |
8 | which accompanies this distribution. The full text of the license may be found at\r | |
9 | http://opensource.org/licenses/bsd-license.php\r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | \r | |
14 | **/\r | |
15 | \r | |
16 | #include <Uefi.h>\r | |
17 | #include <Chipset/AArch64.h>\r | |
18 | #include <Library/ArmLib.h>\r | |
19 | #include <Library/BaseLib.h>\r | |
20 | #include <Library/IoLib.h>\r | |
21 | #include "AArch64Lib.h"\r | |
22 | #include "ArmLibPrivate.h"\r | |
23 | \r | |
24 | ARM_CACHE_TYPE\r | |
25 | EFIAPI\r | |
26 | ArmCacheType (\r | |
27 | VOID\r | |
28 | )\r | |
29 | {\r | |
30 | return ARM_CACHE_TYPE_WRITE_BACK;\r | |
31 | }\r | |
32 | \r | |
33 | ARM_CACHE_ARCHITECTURE\r | |
34 | EFIAPI\r | |
35 | ArmCacheArchitecture (\r | |
36 | VOID\r | |
37 | )\r | |
38 | {\r | |
39 | UINT32 CLIDR = ReadCLIDR ();\r | |
40 | \r | |
41 | return (ARM_CACHE_ARCHITECTURE)CLIDR; // BugBug Fix Me\r | |
42 | }\r | |
43 | \r | |
44 | BOOLEAN\r | |
45 | EFIAPI\r | |
46 | ArmDataCachePresent (\r | |
47 | VOID\r | |
48 | )\r | |
49 | {\r | |
50 | UINT32 CLIDR = ReadCLIDR ();\r | |
51 | \r | |
52 | if ((CLIDR & 0x2) == 0x2) {\r | |
53 | // Instruction cache exists\r | |
54 | return TRUE;\r | |
55 | }\r | |
56 | if ((CLIDR & 0x7) == 0x4) {\r | |
57 | // Unified cache\r | |
58 | return TRUE;\r | |
59 | }\r | |
60 | \r | |
61 | return FALSE;\r | |
62 | }\r | |
63 | \r | |
64 | UINTN\r | |
65 | EFIAPI\r | |
66 | ArmDataCacheSize (\r | |
67 | VOID\r | |
68 | )\r | |
69 | {\r | |
70 | UINT32 NumSets;\r | |
71 | UINT32 Associativity;\r | |
72 | UINT32 LineSize;\r | |
73 | UINT32 CCSIDR = ReadCCSIDR (0);\r | |
74 | \r | |
75 | LineSize = (1 << ((CCSIDR & 0x7) + 2));\r | |
76 | Associativity = ((CCSIDR >> 3) & 0x3ff) + 1;\r | |
77 | NumSets = ((CCSIDR >> 13) & 0x7fff) + 1;\r | |
78 | \r | |
79 | // LineSize is in words (4 byte chunks)\r | |
80 | return NumSets * Associativity * LineSize * 4;\r | |
81 | }\r | |
82 | \r | |
83 | UINTN\r | |
84 | EFIAPI\r | |
85 | ArmDataCacheAssociativity (\r | |
86 | VOID\r | |
87 | )\r | |
88 | {\r | |
89 | UINT32 CCSIDR = ReadCCSIDR (0);\r | |
90 | \r | |
91 | return ((CCSIDR >> 3) & 0x3ff) + 1;\r | |
92 | }\r | |
93 | \r | |
94 | UINTN\r | |
95 | ArmDataCacheSets (\r | |
96 | VOID\r | |
97 | )\r | |
98 | {\r | |
99 | UINT32 CCSIDR = ReadCCSIDR (0);\r | |
100 | \r | |
101 | return ((CCSIDR >> 13) & 0x7fff) + 1;\r | |
102 | }\r | |
103 | \r | |
104 | UINTN\r | |
105 | EFIAPI\r | |
106 | ArmDataCacheLineLength (\r | |
107 | VOID\r | |
108 | )\r | |
109 | {\r | |
110 | UINT32 CCSIDR = ReadCCSIDR (0) & 7;\r | |
111 | \r | |
112 | // * 4 converts to bytes\r | |
113 | return (1 << (CCSIDR + 2)) * 4;\r | |
114 | }\r | |
115 | \r | |
116 | BOOLEAN\r | |
117 | EFIAPI\r | |
118 | ArmInstructionCachePresent (\r | |
119 | VOID\r | |
120 | )\r | |
121 | {\r | |
122 | UINT32 CLIDR = ReadCLIDR ();\r | |
123 | \r | |
124 | if ((CLIDR & 1) == 1) {\r | |
125 | // Instruction cache exists\r | |
126 | return TRUE;\r | |
127 | }\r | |
128 | if ((CLIDR & 0x7) == 0x4) {\r | |
129 | // Unified cache\r | |
130 | return TRUE;\r | |
131 | }\r | |
132 | \r | |
133 | return FALSE;\r | |
134 | }\r | |
135 | \r | |
136 | UINTN\r | |
137 | EFIAPI\r | |
138 | ArmInstructionCacheSize (\r | |
139 | VOID\r | |
140 | )\r | |
141 | {\r | |
142 | UINT32 NumSets;\r | |
143 | UINT32 Associativity;\r | |
144 | UINT32 LineSize;\r | |
145 | UINT32 CCSIDR = ReadCCSIDR (1);\r | |
146 | \r | |
147 | LineSize = (1 << ((CCSIDR & 0x7) + 2));\r | |
148 | Associativity = ((CCSIDR >> 3) & 0x3ff) + 1;\r | |
149 | NumSets = ((CCSIDR >> 13) & 0x7fff) + 1;\r | |
150 | \r | |
151 | // LineSize is in words (4 byte chunks)\r | |
152 | return NumSets * Associativity * LineSize * 4;\r | |
153 | }\r | |
154 | \r | |
155 | UINTN\r | |
156 | EFIAPI\r | |
157 | ArmInstructionCacheAssociativity (\r | |
158 | VOID\r | |
159 | )\r | |
160 | {\r | |
161 | UINT32 CCSIDR = ReadCCSIDR (1);\r | |
162 | \r | |
163 | return ((CCSIDR >> 3) & 0x3ff) + 1;\r | |
164 | }\r | |
165 | \r | |
166 | UINTN\r | |
167 | EFIAPI\r | |
168 | ArmInstructionCacheSets (\r | |
169 | VOID\r | |
170 | )\r | |
171 | {\r | |
172 | UINT32 CCSIDR = ReadCCSIDR (1);\r | |
173 | \r | |
174 | return ((CCSIDR >> 13) & 0x7fff) + 1;\r | |
175 | }\r | |
176 | \r | |
177 | UINTN\r | |
178 | EFIAPI\r | |
179 | ArmInstructionCacheLineLength (\r | |
180 | VOID\r | |
181 | )\r | |
182 | {\r | |
183 | UINT32 CCSIDR = ReadCCSIDR (1) & 7;\r | |
184 | \r | |
185 | // * 4 converts to bytes\r | |
186 | return (1 << (CCSIDR + 2)) * 4;\r | |
187 | }\r | |
188 | \r | |
189 | \r | |
190 | VOID\r | |
191 | AArch64DataCacheOperation (\r | |
192 | IN AARCH64_CACHE_OPERATION DataCacheOperation\r | |
193 | )\r | |
194 | {\r | |
195 | UINTN SavedInterruptState;\r | |
196 | \r | |
197 | SavedInterruptState = ArmGetInterruptState ();\r | |
198 | ArmDisableInterrupts();\r | |
199 | \r | |
200 | AArch64AllDataCachesOperation (DataCacheOperation);\r | |
201 | \r | |
202 | ArmDrainWriteBuffer ();\r | |
203 | \r | |
204 | if (SavedInterruptState) {\r | |
205 | ArmEnableInterrupts ();\r | |
206 | }\r | |
207 | }\r | |
208 | \r | |
209 | \r | |
210 | VOID\r | |
211 | AArch64PoUDataCacheOperation (\r | |
212 | IN AARCH64_CACHE_OPERATION DataCacheOperation\r | |
213 | )\r | |
214 | {\r | |
215 | UINTN SavedInterruptState;\r | |
216 | \r | |
217 | SavedInterruptState = ArmGetInterruptState ();\r | |
218 | ArmDisableInterrupts ();\r | |
219 | \r | |
220 | AArch64PerformPoUDataCacheOperation (DataCacheOperation);\r | |
221 | \r | |
222 | ArmDrainWriteBuffer ();\r | |
223 | \r | |
224 | if (SavedInterruptState) {\r | |
225 | ArmEnableInterrupts ();\r | |
226 | }\r | |
227 | }\r | |
228 | \r | |
229 | VOID\r | |
230 | EFIAPI\r | |
231 | ArmInvalidateDataCache (\r | |
232 | VOID\r | |
233 | )\r | |
234 | {\r | |
01674afd | 235 | ArmDrainWriteBuffer ();\r |
25402f5d HL |
236 | AArch64DataCacheOperation (ArmInvalidateDataCacheEntryBySetWay);\r |
237 | }\r | |
238 | \r | |
239 | VOID\r | |
240 | EFIAPI\r | |
241 | ArmCleanInvalidateDataCache (\r | |
242 | VOID\r | |
243 | )\r | |
244 | {\r | |
01674afd | 245 | ArmDrainWriteBuffer ();\r |
25402f5d HL |
246 | AArch64DataCacheOperation (ArmCleanInvalidateDataCacheEntryBySetWay);\r |
247 | }\r | |
248 | \r | |
249 | VOID\r | |
250 | EFIAPI\r | |
251 | ArmCleanDataCache (\r | |
252 | VOID\r | |
253 | )\r | |
254 | {\r | |
01674afd | 255 | ArmDrainWriteBuffer ();\r |
25402f5d HL |
256 | AArch64DataCacheOperation (ArmCleanDataCacheEntryBySetWay);\r |
257 | }\r | |
258 | \r | |
259 | VOID\r | |
260 | EFIAPI\r | |
261 | ArmCleanDataCacheToPoU (\r | |
262 | VOID\r | |
263 | )\r | |
264 | {\r | |
01674afd | 265 | ArmDrainWriteBuffer ();\r |
25402f5d HL |
266 | AArch64PoUDataCacheOperation (ArmCleanDataCacheEntryBySetWay);\r |
267 | }\r |