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1 | /** @file\r |
2 | * File managing the MMU for ARMv8 architecture\r | |
3 | *\r | |
19dc108b | 4 | * Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r |
25402f5d HL |
5 | *\r |
6 | * This program and the accompanying materials\r | |
7 | * are licensed and made available under the terms and conditions of the BSD License\r | |
8 | * which accompanies this distribution. The full text of the license may be found at\r | |
9 | * http://opensource.org/licenses/bsd-license.php\r | |
10 | *\r | |
11 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | *\r | |
14 | **/\r | |
15 | \r | |
16 | #include <Uefi.h>\r | |
17 | #include <Chipset/AArch64.h>\r | |
18 | #include <Library/BaseMemoryLib.h>\r | |
19 | #include <Library/MemoryAllocationLib.h>\r | |
20 | #include <Library/ArmLib.h>\r | |
21 | #include <Library/BaseLib.h>\r | |
22 | #include <Library/DebugLib.h>\r | |
23 | #include "AArch64Lib.h"\r | |
24 | #include "ArmLibPrivate.h"\r | |
25 | \r | |
26 | // We use this index definition to define an invalid block entry\r | |
27 | #define TT_ATTR_INDX_INVALID ((UINT32)~0)\r | |
28 | \r | |
29 | STATIC\r | |
30 | UINT64\r | |
31 | ArmMemoryAttributeToPageAttribute (\r | |
32 | IN ARM_MEMORY_REGION_ATTRIBUTES Attributes\r | |
33 | )\r | |
34 | {\r | |
35 | switch (Attributes) {\r | |
36 | case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:\r | |
37 | return TT_ATTR_INDX_MEMORY_WRITE_BACK;\r | |
38 | case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:\r | |
39 | return TT_ATTR_INDX_MEMORY_WRITE_THROUGH;\r | |
40 | case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE:\r | |
41 | return TT_ATTR_INDX_DEVICE_MEMORY;\r | |
42 | case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:\r | |
43 | return TT_ATTR_INDX_MEMORY_NON_CACHEABLE;\r | |
44 | case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:\r | |
45 | return TT_ATTR_INDX_MEMORY_WRITE_BACK;\r | |
46 | case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:\r | |
47 | return TT_ATTR_INDX_MEMORY_WRITE_THROUGH;\r | |
48 | case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE:\r | |
49 | return TT_ATTR_INDX_DEVICE_MEMORY;\r | |
50 | case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:\r | |
51 | return TT_ATTR_INDX_MEMORY_NON_CACHEABLE;\r | |
52 | default:\r | |
53 | ASSERT(0);\r | |
54 | return TT_ATTR_INDX_DEVICE_MEMORY;\r | |
55 | }\r | |
56 | }\r | |
57 | \r | |
58 | UINT64\r | |
59 | PageAttributeToGcdAttribute (\r | |
60 | IN UINT64 PageAttributes\r | |
61 | )\r | |
62 | {\r | |
63 | UINT64 GcdAttributes;\r | |
64 | \r | |
65 | switch (PageAttributes & TT_ATTR_INDX_MASK) {\r | |
66 | case TT_ATTR_INDX_DEVICE_MEMORY:\r | |
67 | GcdAttributes = EFI_MEMORY_UC;\r | |
68 | break;\r | |
69 | case TT_ATTR_INDX_MEMORY_NON_CACHEABLE:\r | |
70 | GcdAttributes = EFI_MEMORY_WC;\r | |
71 | break;\r | |
72 | case TT_ATTR_INDX_MEMORY_WRITE_THROUGH:\r | |
73 | GcdAttributes = EFI_MEMORY_WT;\r | |
74 | break;\r | |
75 | case TT_ATTR_INDX_MEMORY_WRITE_BACK:\r | |
76 | GcdAttributes = EFI_MEMORY_WB;\r | |
77 | break;\r | |
78 | default:\r | |
79 | DEBUG ((EFI_D_ERROR, "PageAttributeToGcdAttribute: PageAttributes:0x%lX not supported.\n", PageAttributes));\r | |
80 | ASSERT (0);\r | |
81 | // The Global Coherency Domain (GCD) value is defined as a bit set.\r | |
82 | // Returning 0 means no attribute has been set.\r | |
83 | GcdAttributes = 0;\r | |
84 | }\r | |
85 | \r | |
86 | // Determine protection attributes\r | |
87 | if (((PageAttributes & TT_AP_MASK) == TT_AP_NO_RO) || ((PageAttributes & TT_AP_MASK) == TT_AP_RO_RO)) {\r | |
88 | // Read only cases map to write-protect\r | |
89 | GcdAttributes |= EFI_MEMORY_WP;\r | |
90 | }\r | |
91 | \r | |
92 | // Process eXecute Never attribute\r | |
93 | if ((PageAttributes & (TT_PXN_MASK | TT_UXN_MASK)) != 0 ) {\r | |
94 | GcdAttributes |= EFI_MEMORY_XP;\r | |
95 | }\r | |
96 | \r | |
97 | return GcdAttributes;\r | |
98 | }\r | |
99 | \r | |
100 | UINT64\r | |
101 | GcdAttributeToPageAttribute (\r | |
102 | IN UINT64 GcdAttributes\r | |
103 | )\r | |
104 | {\r | |
105 | UINT64 PageAttributes;\r | |
106 | \r | |
107 | switch (GcdAttributes & 0xFF) {\r | |
108 | case EFI_MEMORY_UC:\r | |
109 | PageAttributes = TT_ATTR_INDX_DEVICE_MEMORY;\r | |
110 | break;\r | |
111 | case EFI_MEMORY_WC:\r | |
112 | PageAttributes = TT_ATTR_INDX_MEMORY_NON_CACHEABLE;\r | |
113 | break;\r | |
114 | case EFI_MEMORY_WT:\r | |
115 | PageAttributes = TT_ATTR_INDX_MEMORY_WRITE_THROUGH;\r | |
116 | break;\r | |
117 | case EFI_MEMORY_WB:\r | |
118 | PageAttributes = TT_ATTR_INDX_MEMORY_WRITE_BACK;\r | |
119 | break;\r | |
120 | default:\r | |
121 | DEBUG ((EFI_D_ERROR, "GcdAttributeToPageAttribute: 0x%X attributes is not supported.\n", GcdAttributes));\r | |
122 | ASSERT (0);\r | |
123 | // If no match has been found then we mark the memory as device memory.\r | |
124 | // The only side effect of using device memory should be a slow down in the performance.\r | |
125 | PageAttributes = TT_ATTR_INDX_DEVICE_MEMORY;\r | |
126 | }\r | |
127 | \r | |
128 | // Determine protection attributes\r | |
129 | if (GcdAttributes & EFI_MEMORY_WP) {\r | |
130 | // Read only cases map to write-protect\r | |
131 | PageAttributes |= TT_AP_RO_RO;\r | |
132 | }\r | |
133 | \r | |
134 | // Process eXecute Never attribute\r | |
135 | if (GcdAttributes & EFI_MEMORY_XP) {\r | |
136 | PageAttributes |= (TT_PXN_MASK | TT_UXN_MASK);\r | |
137 | }\r | |
138 | \r | |
139 | return PageAttributes;\r | |
140 | }\r | |
141 | \r | |
142 | ARM_MEMORY_REGION_ATTRIBUTES\r | |
143 | GcdAttributeToArmAttribute (\r | |
144 | IN UINT64 GcdAttributes\r | |
145 | )\r | |
146 | {\r | |
147 | switch (GcdAttributes & 0xFF) {\r | |
148 | case EFI_MEMORY_UC:\r | |
149 | return ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r | |
150 | case EFI_MEMORY_WC:\r | |
151 | return ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;\r | |
152 | case EFI_MEMORY_WT:\r | |
153 | return ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH;\r | |
154 | case EFI_MEMORY_WB:\r | |
155 | return ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;\r | |
156 | default:\r | |
157 | DEBUG ((EFI_D_ERROR, "GcdAttributeToArmAttribute: 0x%lX attributes is not supported.\n", GcdAttributes));\r | |
158 | ASSERT (0);\r | |
159 | return ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r | |
160 | }\r | |
161 | }\r | |
162 | \r | |
163 | // Describe the T0SZ values for each translation table level\r | |
164 | typedef struct {\r | |
165 | UINTN MinT0SZ;\r | |
166 | UINTN MaxT0SZ;\r | |
167 | UINTN LargestT0SZ; // Generally (MaxT0SZ == LargestT0SZ) but at the Level3 Table\r | |
168 | // the MaxT0SZ is not at the boundary of the table\r | |
169 | } T0SZ_DESCRIPTION_PER_LEVEL;\r | |
170 | \r | |
171 | // Map table for the corresponding Level of Table\r | |
172 | STATIC CONST T0SZ_DESCRIPTION_PER_LEVEL T0SZPerTableLevel[] = {\r | |
173 | { 16, 24, 24 }, // Table Level 0\r | |
174 | { 25, 33, 33 }, // Table Level 1\r | |
175 | { 34, 39, 42 } // Table Level 2\r | |
176 | };\r | |
177 | \r | |
178 | VOID\r | |
179 | GetRootTranslationTableInfo (\r | |
180 | IN UINTN T0SZ,\r | |
181 | OUT UINTN *TableLevel,\r | |
182 | OUT UINTN *TableEntryCount\r | |
183 | )\r | |
184 | {\r | |
185 | UINTN Index;\r | |
186 | \r | |
187 | // Identify the level of the root table from the given T0SZ\r | |
188 | for (Index = 0; Index < sizeof (T0SZPerTableLevel) / sizeof (T0SZ_DESCRIPTION_PER_LEVEL); Index++) {\r | |
189 | if (T0SZ <= T0SZPerTableLevel[Index].MaxT0SZ) {\r | |
190 | break;\r | |
191 | }\r | |
192 | }\r | |
193 | \r | |
194 | // If we have not found the corresponding maximum T0SZ then we use the last one\r | |
195 | if (Index == sizeof (T0SZPerTableLevel) / sizeof (T0SZ_DESCRIPTION_PER_LEVEL)) {\r | |
196 | Index--;\r | |
197 | }\r | |
198 | \r | |
199 | // Get the level of the root table\r | |
200 | if (TableLevel) {\r | |
201 | *TableLevel = Index;\r | |
202 | }\r | |
203 | \r | |
204 | // The Size of the Table is 2^(T0SZ-LargestT0SZ)\r | |
205 | if (TableEntryCount) {\r | |
206 | *TableEntryCount = 1 << (T0SZPerTableLevel[Index].LargestT0SZ - T0SZ + 1);\r | |
207 | }\r | |
208 | }\r | |
209 | \r | |
210 | STATIC\r | |
211 | VOID\r | |
212 | LookupAddresstoRootTable (\r | |
213 | IN UINT64 MaxAddress,\r | |
214 | OUT UINTN *T0SZ,\r | |
215 | OUT UINTN *TableEntryCount\r | |
216 | )\r | |
217 | {\r | |
218 | UINTN TopBit;\r | |
219 | \r | |
220 | // Check the parameters are not NULL\r | |
221 | ASSERT ((T0SZ != NULL) && (TableEntryCount != NULL));\r | |
222 | \r | |
223 | // Look for the highest bit set in MaxAddress\r | |
224 | for (TopBit = 63; TopBit != 0; TopBit--) {\r | |
225 | if ((1ULL << TopBit) & MaxAddress) {\r | |
226 | // MaxAddress top bit is found\r | |
227 | TopBit = TopBit + 1;\r | |
228 | break;\r | |
229 | }\r | |
230 | }\r | |
231 | ASSERT (TopBit != 0);\r | |
232 | \r | |
233 | // Calculate T0SZ from the top bit of the MaxAddress\r | |
234 | *T0SZ = 64 - TopBit;\r | |
235 | \r | |
236 | // Get the Table info from T0SZ\r | |
237 | GetRootTranslationTableInfo (*T0SZ, NULL, TableEntryCount);\r | |
238 | }\r | |
239 | \r | |
240 | STATIC\r | |
241 | UINT64*\r | |
242 | GetBlockEntryListFromAddress (\r | |
243 | IN UINT64 *RootTable,\r | |
244 | IN UINT64 RegionStart,\r | |
245 | OUT UINTN *TableLevel,\r | |
246 | IN OUT UINT64 *BlockEntrySize,\r | |
edff645f | 247 | OUT UINT64 **LastBlockEntry\r |
25402f5d HL |
248 | )\r |
249 | {\r | |
250 | UINTN RootTableLevel;\r | |
251 | UINTN RootTableEntryCount;\r | |
252 | UINT64 *TranslationTable;\r | |
253 | UINT64 *BlockEntry;\r | |
ebb92353 | 254 | UINT64 *SubTableBlockEntry;\r |
25402f5d HL |
255 | UINT64 BlockEntryAddress;\r |
256 | UINTN BaseAddressAlignment;\r | |
257 | UINTN PageLevel;\r | |
258 | UINTN Index;\r | |
259 | UINTN IndexLevel;\r | |
260 | UINTN T0SZ;\r | |
261 | UINT64 Attributes;\r | |
262 | UINT64 TableAttributes;\r | |
263 | \r | |
264 | // Initialize variable\r | |
265 | BlockEntry = NULL;\r | |
266 | \r | |
267 | // Ensure the parameters are valid\r | |
19dc108b OM |
268 | if (!(TableLevel && BlockEntrySize && LastBlockEntry)) {\r |
269 | ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER);\r | |
270 | return NULL;\r | |
271 | }\r | |
25402f5d HL |
272 | \r |
273 | // Ensure the Region is aligned on 4KB boundary\r | |
19dc108b OM |
274 | if ((RegionStart & (SIZE_4KB - 1)) != 0) {\r |
275 | ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER);\r | |
276 | return NULL;\r | |
277 | }\r | |
25402f5d | 278 | \r |
41f89016 HG |
279 | // Ensure the required size is aligned on 4KB boundary and not 0\r |
280 | if ((*BlockEntrySize & (SIZE_4KB - 1)) != 0 || *BlockEntrySize == 0) {\r | |
19dc108b OM |
281 | ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER);\r |
282 | return NULL;\r | |
283 | }\r | |
25402f5d | 284 | \r |
25402f5d HL |
285 | T0SZ = ArmGetTCR () & TCR_T0SZ_MASK;\r |
286 | // Get the Table info from T0SZ\r | |
287 | GetRootTranslationTableInfo (T0SZ, &RootTableLevel, &RootTableEntryCount);\r | |
25402f5d HL |
288 | \r |
289 | // If the start address is 0x0 then we use the size of the region to identify the alignment\r | |
290 | if (RegionStart == 0) {\r | |
291 | // Identify the highest possible alignment for the Region Size\r | |
41f89016 | 292 | BaseAddressAlignment = LowBitSet64 (*BlockEntrySize);\r |
25402f5d HL |
293 | } else {\r |
294 | // Identify the highest possible alignment for the Base Address\r | |
41f89016 | 295 | BaseAddressAlignment = LowBitSet64 (RegionStart);\r |
25402f5d HL |
296 | }\r |
297 | \r | |
298 | // Identify the Page Level the RegionStart must belongs to\r | |
299 | PageLevel = 3 - ((BaseAddressAlignment - 12) / 9);\r | |
300 | \r | |
6ea162c2 OM |
301 | // If the required size is smaller than the current block size then we need to go to the page below.\r |
302 | // The PageLevel was calculated on the Base Address alignment but did not take in account the alignment\r | |
303 | // of the allocation size\r | |
946067bf | 304 | while (*BlockEntrySize < TT_BLOCK_ENTRY_SIZE_AT_LEVEL (PageLevel)) {\r |
25402f5d HL |
305 | // It does not fit so we need to go a page level above\r |
306 | PageLevel++;\r | |
307 | }\r | |
308 | \r | |
25402f5d HL |
309 | //\r |
310 | // Get the Table Descriptor for the corresponding PageLevel. We need to decompose RegionStart to get appropriate entries\r | |
311 | //\r | |
312 | \r | |
313 | TranslationTable = RootTable;\r | |
314 | for (IndexLevel = RootTableLevel; IndexLevel <= PageLevel; IndexLevel++) {\r | |
315 | BlockEntry = (UINT64*)TT_GET_ENTRY_FOR_ADDRESS (TranslationTable, IndexLevel, RegionStart);\r | |
316 | \r | |
317 | if ((IndexLevel != 3) && ((*BlockEntry & TT_TYPE_MASK) == TT_TYPE_TABLE_ENTRY)) {\r | |
318 | // Go to the next table\r | |
319 | TranslationTable = (UINT64*)(*BlockEntry & TT_ADDRESS_MASK_DESCRIPTION_TABLE);\r | |
320 | \r | |
edff645f | 321 | // If we are at the last level then update the last level to next level\r |
25402f5d | 322 | if (IndexLevel == PageLevel) {\r |
edff645f HG |
323 | // Enter the next level\r |
324 | PageLevel++;\r | |
25402f5d HL |
325 | }\r |
326 | } else if ((*BlockEntry & TT_TYPE_MASK) == TT_TYPE_BLOCK_ENTRY) {\r | |
327 | // If we are not at the last level then we need to split this BlockEntry\r | |
328 | if (IndexLevel != PageLevel) {\r | |
329 | // Retrieve the attributes from the block entry\r | |
330 | Attributes = *BlockEntry & TT_ATTRIBUTES_MASK;\r | |
331 | \r | |
332 | // Convert the block entry attributes into Table descriptor attributes\r | |
333 | TableAttributes = TT_TABLE_AP_NO_PERMISSION;\r | |
334 | if (Attributes & TT_PXN_MASK) {\r | |
335 | TableAttributes = TT_TABLE_PXN;\r | |
336 | }\r | |
337 | if (Attributes & TT_UXN_MASK) {\r | |
338 | TableAttributes = TT_TABLE_XN;\r | |
339 | }\r | |
340 | if (Attributes & TT_NS) {\r | |
341 | TableAttributes = TT_TABLE_NS;\r | |
342 | }\r | |
343 | \r | |
344 | // Get the address corresponding at this entry\r | |
345 | BlockEntryAddress = RegionStart;\r | |
346 | BlockEntryAddress = BlockEntryAddress >> TT_ADDRESS_OFFSET_AT_LEVEL(IndexLevel);\r | |
347 | // Shift back to right to set zero before the effective address\r | |
348 | BlockEntryAddress = BlockEntryAddress << TT_ADDRESS_OFFSET_AT_LEVEL(IndexLevel);\r | |
349 | \r | |
6ea162c2 OM |
350 | // Set the correct entry type for the next page level\r |
351 | if ((IndexLevel + 1) == 3) {\r | |
25402f5d HL |
352 | Attributes |= TT_TYPE_BLOCK_ENTRY_LEVEL3;\r |
353 | } else {\r | |
354 | Attributes |= TT_TYPE_BLOCK_ENTRY;\r | |
355 | }\r | |
356 | \r | |
357 | // Create a new translation table\r | |
7d189f99 | 358 | TranslationTable = (UINT64*)AllocateAlignedPages (EFI_SIZE_TO_PAGES(TT_ENTRY_COUNT * sizeof(UINT64)), TT_ALIGNMENT_DESCRIPTION_TABLE);\r |
25402f5d HL |
359 | if (TranslationTable == NULL) {\r |
360 | return NULL;\r | |
361 | }\r | |
25402f5d | 362 | \r |
ebb92353 OM |
363 | // Populate the newly created lower level table\r |
364 | SubTableBlockEntry = TranslationTable;\r | |
365 | for (Index = 0; Index < TT_ENTRY_COUNT; Index++) {\r | |
366 | *SubTableBlockEntry = Attributes | (BlockEntryAddress + (Index << TT_ADDRESS_OFFSET_AT_LEVEL(IndexLevel + 1)));\r | |
367 | SubTableBlockEntry++;\r | |
368 | }\r | |
369 | \r | |
6ea162c2 | 370 | // Fill the BlockEntry with the new TranslationTable\r |
25402f5d | 371 | *BlockEntry = ((UINTN)TranslationTable & TT_ADDRESS_MASK_DESCRIPTION_TABLE) | TableAttributes | TT_TYPE_TABLE_ENTRY;\r |
25402f5d HL |
372 | }\r |
373 | } else {\r | |
25402f5d | 374 | if (IndexLevel != PageLevel) {\r |
8bb7f03a OM |
375 | //\r |
376 | // Case when we have an Invalid Entry and we are at a page level above of the one targetted.\r | |
377 | //\r | |
378 | \r | |
25402f5d | 379 | // Create a new translation table\r |
7d189f99 | 380 | TranslationTable = (UINT64*)AllocateAlignedPages (EFI_SIZE_TO_PAGES(TT_ENTRY_COUNT * sizeof(UINT64)), TT_ALIGNMENT_DESCRIPTION_TABLE);\r |
25402f5d HL |
381 | if (TranslationTable == NULL) {\r |
382 | return NULL;\r | |
383 | }\r | |
25402f5d HL |
384 | \r |
385 | ZeroMem (TranslationTable, TT_ENTRY_COUNT * sizeof(UINT64));\r | |
386 | \r | |
387 | // Fill the new BlockEntry with the TranslationTable\r | |
388 | *BlockEntry = ((UINTN)TranslationTable & TT_ADDRESS_MASK_DESCRIPTION_TABLE) | TT_TYPE_TABLE_ENTRY;\r | |
389 | }\r | |
390 | }\r | |
391 | }\r | |
392 | \r | |
edff645f HG |
393 | // Expose the found PageLevel to the caller\r |
394 | *TableLevel = PageLevel;\r | |
395 | \r | |
396 | // Now, we have the Table Level we can get the Block Size associated to this table\r | |
397 | *BlockEntrySize = TT_BLOCK_ENTRY_SIZE_AT_LEVEL (PageLevel);\r | |
398 | \r | |
399 | // The last block of the root table depends on the number of entry in this table,\r | |
400 | // otherwise it is always the (TT_ENTRY_COUNT - 1)th entry in the table.\r | |
401 | *LastBlockEntry = TT_LAST_BLOCK_ADDRESS(TranslationTable,\r | |
402 | (PageLevel == RootTableLevel) ? RootTableEntryCount : TT_ENTRY_COUNT);\r | |
403 | \r | |
25402f5d HL |
404 | return BlockEntry;\r |
405 | }\r | |
406 | \r | |
407 | STATIC\r | |
408 | RETURN_STATUS\r | |
409 | FillTranslationTable (\r | |
410 | IN UINT64 *RootTable,\r | |
411 | IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryRegion\r | |
412 | )\r | |
413 | {\r | |
414 | UINT64 Attributes;\r | |
415 | UINT32 Type;\r | |
416 | UINT64 RegionStart;\r | |
417 | UINT64 RemainingRegionLength;\r | |
418 | UINT64 *BlockEntry;\r | |
419 | UINT64 *LastBlockEntry;\r | |
420 | UINT64 BlockEntrySize;\r | |
421 | UINTN TableLevel;\r | |
422 | \r | |
423 | // Ensure the Length is aligned on 4KB boundary\r | |
19dc108b OM |
424 | if ((MemoryRegion->Length == 0) || ((MemoryRegion->Length & (SIZE_4KB - 1)) != 0)) {\r |
425 | ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER);\r | |
426 | return RETURN_INVALID_PARAMETER;\r | |
427 | }\r | |
25402f5d HL |
428 | \r |
429 | // Variable initialization\r | |
430 | Attributes = ArmMemoryAttributeToPageAttribute (MemoryRegion->Attributes) | TT_AF;\r | |
431 | RemainingRegionLength = MemoryRegion->Length;\r | |
432 | RegionStart = MemoryRegion->VirtualBase;\r | |
433 | \r | |
434 | do {\r | |
435 | // Get the first Block Entry that matches the Virtual Address and also the information on the Table Descriptor\r | |
436 | // such as the the size of the Block Entry and the address of the last BlockEntry of the Table Descriptor\r | |
437 | BlockEntrySize = RemainingRegionLength;\r | |
438 | BlockEntry = GetBlockEntryListFromAddress (RootTable, RegionStart, &TableLevel, &BlockEntrySize, &LastBlockEntry);\r | |
439 | if (BlockEntry == NULL) {\r | |
440 | // GetBlockEntryListFromAddress() return NULL when it fails to allocate new pages from the Translation Tables\r | |
441 | return RETURN_OUT_OF_RESOURCES;\r | |
442 | }\r | |
443 | \r | |
444 | if (TableLevel != 3) {\r | |
445 | Type = TT_TYPE_BLOCK_ENTRY;\r | |
446 | } else {\r | |
447 | Type = TT_TYPE_BLOCK_ENTRY_LEVEL3;\r | |
448 | }\r | |
449 | \r | |
450 | do {\r | |
451 | // Fill the Block Entry with attribute and output block address\r | |
452 | *BlockEntry = (RegionStart & TT_ADDRESS_MASK_BLOCK_ENTRY) | Attributes | Type;\r | |
453 | \r | |
454 | // Go to the next BlockEntry\r | |
455 | RegionStart += BlockEntrySize;\r | |
456 | RemainingRegionLength -= BlockEntrySize;\r | |
457 | BlockEntry++;\r | |
84836814 HG |
458 | \r |
459 | // Break the inner loop when next block is a table\r | |
460 | // Rerun GetBlockEntryListFromAddress to avoid page table memory leak\r | |
461 | if (TableLevel != 3 &&\r | |
462 | (*BlockEntry & TT_TYPE_MASK) == TT_TYPE_TABLE_ENTRY) {\r | |
463 | break;\r | |
464 | }\r | |
25402f5d HL |
465 | } while ((RemainingRegionLength >= BlockEntrySize) && (BlockEntry <= LastBlockEntry));\r |
466 | } while (RemainingRegionLength != 0);\r | |
467 | \r | |
468 | return RETURN_SUCCESS;\r | |
469 | }\r | |
470 | \r | |
471 | RETURN_STATUS\r | |
472 | SetMemoryAttributes (\r | |
473 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
474 | IN UINT64 Length,\r | |
475 | IN UINT64 Attributes,\r | |
476 | IN EFI_PHYSICAL_ADDRESS VirtualMask\r | |
477 | )\r | |
e6f3ed43 | 478 | {\r |
25402f5d HL |
479 | RETURN_STATUS Status;\r |
480 | ARM_MEMORY_REGION_DESCRIPTOR MemoryRegion;\r | |
481 | UINT64 *TranslationTable;\r | |
482 | \r | |
483 | MemoryRegion.PhysicalBase = BaseAddress;\r | |
484 | MemoryRegion.VirtualBase = BaseAddress;\r | |
485 | MemoryRegion.Length = Length;\r | |
486 | MemoryRegion.Attributes = GcdAttributeToArmAttribute (Attributes);\r | |
487 | \r | |
488 | TranslationTable = ArmGetTTBR0BaseAddress ();\r | |
489 | \r | |
e6f3ed43 LL |
490 | Status = FillTranslationTable (TranslationTable, &MemoryRegion);\r |
491 | if (RETURN_ERROR (Status)) {\r | |
492 | return Status;\r | |
25402f5d HL |
493 | }\r |
494 | \r | |
495 | // Flush d-cache so descriptors make it back to uncached memory for subsequent table walks\r | |
496 | // flush and invalidate pages\r | |
497 | ArmCleanInvalidateDataCache ();\r | |
498 | \r | |
499 | ArmInvalidateInstructionCache ();\r | |
500 | \r | |
501 | // Invalidate all TLB entries so changes are synced\r | |
502 | ArmInvalidateTlb ();\r | |
503 | \r | |
504 | return RETURN_SUCCESS;\r | |
505 | }\r | |
506 | \r | |
507 | RETURN_STATUS\r | |
508 | EFIAPI\r | |
509 | ArmConfigureMmu (\r | |
510 | IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,\r | |
511 | OUT VOID **TranslationTableBase OPTIONAL,\r | |
512 | OUT UINTN *TranslationTableSize OPTIONAL\r | |
513 | )\r | |
514 | {\r | |
515 | VOID* TranslationTable;\r | |
516 | UINTN TranslationTablePageCount;\r | |
517 | UINT32 TranslationTableAttribute;\r | |
518 | ARM_MEMORY_REGION_DESCRIPTOR *MemoryTableEntry;\r | |
519 | UINT64 MaxAddress;\r | |
520 | UINT64 TopAddress;\r | |
521 | UINTN T0SZ;\r | |
522 | UINTN RootTableEntryCount;\r | |
523 | UINT64 TCR;\r | |
524 | RETURN_STATUS Status;\r | |
525 | \r | |
8bb7f03a | 526 | if(MemoryTable == NULL) {\r |
19dc108b OM |
527 | ASSERT (MemoryTable != NULL);\r |
528 | return RETURN_INVALID_PARAMETER;\r | |
529 | }\r | |
25402f5d HL |
530 | \r |
531 | // Identify the highest address of the memory table\r | |
532 | MaxAddress = MemoryTable->PhysicalBase + MemoryTable->Length - 1;\r | |
533 | MemoryTableEntry = MemoryTable;\r | |
534 | while (MemoryTableEntry->Length != 0) {\r | |
535 | TopAddress = MemoryTableEntry->PhysicalBase + MemoryTableEntry->Length - 1;\r | |
536 | if (TopAddress > MaxAddress) {\r | |
537 | MaxAddress = TopAddress;\r | |
538 | }\r | |
539 | MemoryTableEntry++;\r | |
540 | }\r | |
541 | \r | |
542 | // Lookup the Table Level to get the information\r | |
543 | LookupAddresstoRootTable (MaxAddress, &T0SZ, &RootTableEntryCount);\r | |
544 | \r | |
545 | //\r | |
546 | // Set TCR that allows us to retrieve T0SZ in the subsequent functions\r | |
547 | //\r | |
e21227c6 OM |
548 | // Ideally we will be running at EL2, but should support EL1 as well.\r |
549 | // UEFI should not run at EL3.\r | |
550 | if (ArmReadCurrentEL () == AARCH64_EL2) {\r | |
551 | //Note: Bits 23 and 31 are reserved(RES1) bits in TCR_EL2\r | |
25402f5d HL |
552 | TCR = T0SZ | (1UL << 31) | (1UL << 23) | TCR_TG0_4KB;\r |
553 | \r | |
554 | // Set the Physical Address Size using MaxAddress\r | |
555 | if (MaxAddress < SIZE_4GB) {\r | |
556 | TCR |= TCR_PS_4GB;\r | |
557 | } else if (MaxAddress < SIZE_64GB) {\r | |
558 | TCR |= TCR_PS_64GB;\r | |
559 | } else if (MaxAddress < SIZE_1TB) {\r | |
560 | TCR |= TCR_PS_1TB;\r | |
561 | } else if (MaxAddress < SIZE_4TB) {\r | |
562 | TCR |= TCR_PS_4TB;\r | |
563 | } else if (MaxAddress < SIZE_16TB) {\r | |
564 | TCR |= TCR_PS_16TB;\r | |
565 | } else if (MaxAddress < SIZE_256TB) {\r | |
566 | TCR |= TCR_PS_256TB;\r | |
567 | } else {\r | |
e21227c6 OM |
568 | DEBUG ((EFI_D_ERROR, "ArmConfigureMmu: The MaxAddress 0x%lX is not supported by this MMU configuration.\n", MaxAddress));\r |
569 | ASSERT (0); // Bigger than 48-bit memory space are not supported\r | |
570 | return RETURN_UNSUPPORTED;\r | |
571 | }\r | |
572 | } else if (ArmReadCurrentEL () == AARCH64_EL1) {\r | |
573 | TCR = T0SZ | TCR_TG0_4KB;\r | |
574 | \r | |
575 | // Set the Physical Address Size using MaxAddress\r | |
576 | if (MaxAddress < SIZE_4GB) {\r | |
577 | TCR |= TCR_IPS_4GB;\r | |
578 | } else if (MaxAddress < SIZE_64GB) {\r | |
579 | TCR |= TCR_IPS_64GB;\r | |
580 | } else if (MaxAddress < SIZE_1TB) {\r | |
581 | TCR |= TCR_IPS_1TB;\r | |
582 | } else if (MaxAddress < SIZE_4TB) {\r | |
583 | TCR |= TCR_IPS_4TB;\r | |
584 | } else if (MaxAddress < SIZE_16TB) {\r | |
585 | TCR |= TCR_IPS_16TB;\r | |
586 | } else if (MaxAddress < SIZE_256TB) {\r | |
587 | TCR |= TCR_IPS_256TB;\r | |
588 | } else {\r | |
589 | DEBUG ((EFI_D_ERROR, "ArmConfigureMmu: The MaxAddress 0x%lX is not supported by this MMU configuration.\n", MaxAddress));\r | |
25402f5d HL |
590 | ASSERT (0); // Bigger than 48-bit memory space are not supported\r |
591 | return RETURN_UNSUPPORTED;\r | |
592 | }\r | |
593 | } else {\r | |
e21227c6 | 594 | ASSERT (0); // UEFI is only expected to run at EL2 and EL1, not EL3.\r |
25402f5d HL |
595 | return RETURN_UNSUPPORTED;\r |
596 | }\r | |
597 | \r | |
598 | // Set TCR\r | |
599 | ArmSetTCR (TCR);\r | |
600 | \r | |
601 | // Allocate pages for translation table\r | |
7d189f99 HG |
602 | TranslationTablePageCount = EFI_SIZE_TO_PAGES(RootTableEntryCount * sizeof(UINT64));\r |
603 | TranslationTable = (UINT64*)AllocateAlignedPages (TranslationTablePageCount, TT_ALIGNMENT_DESCRIPTION_TABLE);\r | |
25402f5d HL |
604 | if (TranslationTable == NULL) {\r |
605 | return RETURN_OUT_OF_RESOURCES;\r | |
606 | }\r | |
25402f5d HL |
607 | // We set TTBR0 just after allocating the table to retrieve its location from the subsequent\r |
608 | // functions without needing to pass this value across the functions. The MMU is only enabled\r | |
609 | // after the translation tables are populated.\r | |
610 | ArmSetTTBR0 (TranslationTable);\r | |
611 | \r | |
612 | if (TranslationTableBase != NULL) {\r | |
613 | *TranslationTableBase = TranslationTable;\r | |
614 | }\r | |
615 | \r | |
616 | if (TranslationTableSize != NULL) {\r | |
617 | *TranslationTableSize = RootTableEntryCount * sizeof(UINT64);\r | |
618 | }\r | |
619 | \r | |
620 | ZeroMem (TranslationTable, RootTableEntryCount * sizeof(UINT64));\r | |
621 | \r | |
622 | // Disable MMU and caches. ArmDisableMmu() also invalidates the TLBs\r | |
623 | ArmDisableMmu ();\r | |
624 | ArmDisableDataCache ();\r | |
625 | ArmDisableInstructionCache ();\r | |
626 | \r | |
627 | // Make sure nothing sneaked into the cache\r | |
628 | ArmCleanInvalidateDataCache ();\r | |
629 | ArmInvalidateInstructionCache ();\r | |
630 | \r | |
631 | TranslationTableAttribute = TT_ATTR_INDX_INVALID;\r | |
632 | while (MemoryTable->Length != 0) {\r | |
633 | // Find the memory attribute for the Translation Table\r | |
634 | if (((UINTN)TranslationTable >= MemoryTable->PhysicalBase) &&\r | |
635 | ((UINTN)TranslationTable <= MemoryTable->PhysicalBase - 1 + MemoryTable->Length)) {\r | |
636 | TranslationTableAttribute = MemoryTable->Attributes;\r | |
637 | }\r | |
638 | \r | |
639 | Status = FillTranslationTable (TranslationTable, MemoryTable);\r | |
640 | if (RETURN_ERROR (Status)) {\r | |
641 | goto FREE_TRANSLATION_TABLE;\r | |
642 | }\r | |
643 | MemoryTable++;\r | |
644 | }\r | |
645 | \r | |
646 | // Translate the Memory Attributes into Translation Table Register Attributes\r | |
647 | if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED) ||\r | |
648 | (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED)) {\r | |
649 | TCR |= TCR_SH_NON_SHAREABLE | TCR_RGN_OUTER_NON_CACHEABLE | TCR_RGN_INNER_NON_CACHEABLE;\r | |
650 | } else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK) ||\r | |
651 | (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK)) {\r | |
652 | TCR |= TCR_SH_INNER_SHAREABLE | TCR_RGN_OUTER_WRITE_BACK_ALLOC | TCR_RGN_INNER_WRITE_BACK_ALLOC;\r | |
653 | } else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH) ||\r | |
654 | (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH)) {\r | |
655 | TCR |= TCR_SH_NON_SHAREABLE | TCR_RGN_OUTER_WRITE_THROUGH | TCR_RGN_INNER_WRITE_THROUGH;\r | |
656 | } else {\r | |
657 | // If we failed to find a mapping that contains the root translation table then it probably means the translation table\r | |
658 | // is not mapped in the given memory map.\r | |
659 | ASSERT (0);\r | |
660 | Status = RETURN_UNSUPPORTED;\r | |
661 | goto FREE_TRANSLATION_TABLE;\r | |
662 | }\r | |
663 | \r | |
1eb5b4f2 OM |
664 | // Set again TCR after getting the Translation Table attributes\r |
665 | ArmSetTCR (TCR);\r | |
666 | \r | |
25402f5d HL |
667 | ArmSetMAIR (MAIR_ATTR(TT_ATTR_INDX_DEVICE_MEMORY, MAIR_ATTR_DEVICE_MEMORY) | // mapped to EFI_MEMORY_UC\r |
668 | MAIR_ATTR(TT_ATTR_INDX_MEMORY_NON_CACHEABLE, MAIR_ATTR_NORMAL_MEMORY_NON_CACHEABLE) | // mapped to EFI_MEMORY_WC\r | |
669 | MAIR_ATTR(TT_ATTR_INDX_MEMORY_WRITE_THROUGH, MAIR_ATTR_NORMAL_MEMORY_WRITE_THROUGH) | // mapped to EFI_MEMORY_WT\r | |
670 | MAIR_ATTR(TT_ATTR_INDX_MEMORY_WRITE_BACK, MAIR_ATTR_NORMAL_MEMORY_WRITE_BACK)); // mapped to EFI_MEMORY_WB\r | |
671 | \r | |
672 | ArmDisableAlignmentCheck ();\r | |
673 | ArmEnableInstructionCache ();\r | |
674 | ArmEnableDataCache ();\r | |
675 | \r | |
676 | ArmEnableMmu ();\r | |
677 | return RETURN_SUCCESS;\r | |
678 | \r | |
679 | FREE_TRANSLATION_TABLE:\r | |
680 | FreePages (TranslationTable, TranslationTablePageCount);\r | |
681 | return Status;\r | |
682 | }\r |