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1e57a462 | 1 | //------------------------------------------------------------------------------ \r |
2 | //\r | |
3 | // Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r | |
4 | //\r | |
5 | // This program and the accompanying materials\r | |
6 | // are licensed and made available under the terms and conditions of the BSD License\r | |
7 | // which accompanies this distribution. The full text of the license may be found at\r | |
8 | // http://opensource.org/licenses/bsd-license.php\r | |
9 | //\r | |
10 | // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | //\r | |
13 | //------------------------------------------------------------------------------\r | |
14 | \r | |
15 | EXPORT ArmCleanInvalidateDataCache\r | |
16 | EXPORT ArmCleanDataCache\r | |
17 | EXPORT ArmInvalidateDataCache\r | |
18 | EXPORT ArmInvalidateInstructionCache\r | |
19 | EXPORT ArmInvalidateDataCacheEntryByMVA\r | |
20 | EXPORT ArmCleanDataCacheEntryByMVA\r | |
21 | EXPORT ArmCleanInvalidateDataCacheEntryByMVA\r | |
22 | EXPORT ArmEnableMmu\r | |
23 | EXPORT ArmDisableMmu\r | |
24 | EXPORT ArmMmuEnabled\r | |
25 | EXPORT ArmEnableDataCache\r | |
26 | EXPORT ArmDisableDataCache\r | |
27 | EXPORT ArmEnableInstructionCache\r | |
28 | EXPORT ArmDisableInstructionCache\r | |
29 | EXPORT ArmEnableBranchPrediction\r | |
30 | EXPORT ArmDisableBranchPrediction\r | |
31 | EXPORT ArmDataMemoryBarrier\r | |
32 | EXPORT ArmDataSyncronizationBarrier\r | |
33 | EXPORT ArmInstructionSynchronizationBarrier\r | |
34 | \r | |
35 | \r | |
36 | DC_ON EQU ( 0x1:SHL:2 )\r | |
37 | IC_ON EQU ( 0x1:SHL:12 )\r | |
38 | XP_ON EQU ( 0x1:SHL:23 )\r | |
39 | \r | |
40 | \r | |
41 | AREA ArmCacheLib, CODE, READONLY\r | |
42 | PRESERVE8\r | |
43 | \r | |
44 | \r | |
45 | ArmInvalidateDataCacheEntryByMVA\r | |
46 | mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line \r | |
47 | bx lr\r | |
48 | \r | |
49 | \r | |
50 | ArmCleanDataCacheEntryByMVA\r | |
51 | mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line \r | |
52 | bx lr\r | |
53 | \r | |
54 | \r | |
55 | ArmCleanInvalidateDataCacheEntryByMVA\r | |
56 | mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line\r | |
57 | bx lr\r | |
58 | \r | |
59 | \r | |
60 | ArmCleanDataCache\r | |
61 | mcr p15, 0, r0, c7, c10, 0 ; clean entire data cache\r | |
62 | bx lr\r | |
63 | \r | |
64 | \r | |
65 | ArmCleanInvalidateDataCache\r | |
66 | mcr p15, 0, r0, c7, c14, 0 ; clean and invalidate entire data cache\r | |
67 | bx lr\r | |
68 | \r | |
69 | \r | |
70 | ArmInvalidateDataCache\r | |
71 | mcr p15, 0, r0, c7, c6, 0 ; invalidate entire data cache\r | |
72 | bx lr\r | |
73 | \r | |
74 | \r | |
75 | ArmInvalidateInstructionCache\r | |
76 | mcr p15, 0, r0, c7, c5, 0 ;invalidate entire instruction cache\r | |
77 | mov R0,#0\r | |
78 | mcr p15,0,R0,c7,c5,4 ;Flush Prefetch buffer\r | |
79 | bx lr\r | |
80 | \r | |
81 | ArmEnableMmu\r | |
82 | mrc p15,0,R0,c1,c0,0\r | |
83 | orr R0,R0,#1\r | |
84 | mcr p15,0,R0,c1,c0,0\r | |
85 | bx LR\r | |
86 | \r | |
87 | ArmMmuEnabled\r | |
88 | mrc p15,0,R0,c1,c0,0\r | |
89 | and R0,R0,#1\r | |
90 | bx LR\r | |
91 | \r | |
92 | ArmDisableMmu\r | |
93 | mrc p15,0,R0,c1,c0,0\r | |
94 | bic R0,R0,#1\r | |
95 | mcr p15,0,R0,c1,c0,0\r | |
96 | mov R0,#0\r | |
97 | mcr p15,0,R0,c7,c10,4 ;Data synchronization barrier\r | |
98 | mov R0,#0\r | |
99 | mcr p15,0,R0,c7,c5,4 ;Flush Prefetch buffer\r | |
100 | bx LR\r | |
101 | \r | |
102 | ArmEnableDataCache\r | |
103 | LDR R1,=DC_ON\r | |
104 | MRC p15,0,R0,c1,c0,0 ;Read control register configuration data\r | |
105 | ORR R0,R0,R1 ;Set C bit\r | |
106 | MCR p15,0,r0,c1,c0,0 ;Write control register configuration data\r | |
107 | BX LR\r | |
108 | \r | |
109 | ArmDisableDataCache\r | |
110 | LDR R1,=DC_ON\r | |
111 | MRC p15,0,R0,c1,c0,0 ;Read control register configuration data\r | |
112 | BIC R0,R0,R1 ;Clear C bit\r | |
113 | MCR p15,0,r0,c1,c0,0 ;Write control register configuration data\r | |
114 | BX LR\r | |
115 | \r | |
116 | ArmEnableInstructionCache\r | |
117 | LDR R1,=IC_ON\r | |
118 | MRC p15,0,R0,c1,c0,0 ;Read control register configuration data\r | |
119 | ORR R0,R0,R1 ;Set I bit\r | |
120 | MCR p15,0,r0,c1,c0,0 ;Write control register configuration data\r | |
121 | BX LR\r | |
122 | \r | |
123 | ArmDisableInstructionCache\r | |
124 | LDR R1,=IC_ON\r | |
125 | MRC p15,0,R0,c1,c0,0 ;Read control register configuration data\r | |
126 | BIC R0,R0,R1 ;Clear I bit.\r | |
127 | MCR p15,0,r0,c1,c0,0 ;Write control register configuration data\r | |
128 | BX LR\r | |
129 | \r | |
130 | ArmEnableBranchPrediction\r | |
131 | mrc p15, 0, r0, c1, c0, 0\r | |
132 | orr r0, r0, #0x00000800\r | |
133 | mcr p15, 0, r0, c1, c0, 0\r | |
134 | bx LR\r | |
135 | \r | |
136 | ArmDisableBranchPrediction\r | |
137 | mrc p15, 0, r0, c1, c0, 0\r | |
138 | bic r0, r0, #0x00000800\r | |
139 | mcr p15, 0, r0, c1, c0, 0\r | |
140 | bx LR\r | |
141 | \r | |
142 | ASM_PFX(ArmDataMemoryBarrier):\r | |
143 | mov R0, #0\r | |
144 | mcr P15, #0, R0, C7, C10, #5 \r | |
145 | bx LR\r | |
146 | \r | |
147 | ASM_PFX(ArmDataSyncronizationBarrier):\r | |
148 | mov R0, #0\r | |
149 | mcr P15, #0, R0, C7, C10, #4 \r | |
150 | bx LR\r | |
151 | \r | |
152 | ASM_PFX(ArmInstructionSynchronizationBarrier):\r | |
153 | MOV R0, #0\r | |
154 | MCR P15, #0, R0, C7, C5, #4 \r | |
155 | bx LR\r | |
156 | \r | |
157 | END\r |