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1e57a462 | 1 | #------------------------------------------------------------------------------\r |
2 | #\r | |
3 | # Copyright (c) 2011, ARM. All rights reserved.<BR>\r | |
4 | #\r | |
5 | # This program and the accompanying materials\r | |
6 | # are licensed and made available under the terms and conditions of the BSD License\r | |
7 | # which accompanies this distribution. The full text of the license may be found at\r | |
8 | # http://opensource.org/licenses/bsd-license.php\r | |
9 | #\r | |
10 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | #\r | |
13 | #------------------------------------------------------------------------------\r | |
14 | \r | |
15 | .text\r | |
16 | .align 2\r | |
17 | GCC_ASM_EXPORT(__aeabi_uidiv)\r | |
18 | GCC_ASM_EXPORT(__aeabi_uidivmod)\r | |
19 | GCC_ASM_EXPORT(__aeabi_idiv)\r | |
20 | GCC_ASM_EXPORT(__aeabi_idivmod)\r | |
21 | \r | |
22 | # AREA Math, CODE, READONLY\r | |
23 | \r | |
24 | #\r | |
25 | #UINT32\r | |
26 | #EFIAPI\r | |
27 | #__aeabi_uidivmode (\r | |
28 | # IN UINT32 Dividen\r | |
29 | # IN UINT32 Divisor\r | |
30 | # );\r | |
31 | #\r | |
32 | \r | |
33 | ASM_PFX(__aeabi_uidiv):\r | |
34 | ASM_PFX(__aeabi_uidivmod):\r | |
35 | rsbs r12, r1, r0, LSR #4\r | |
36 | mov r2, #0\r | |
37 | bcc ASM_PFX(__arm_div4)\r | |
38 | rsbs r12, r1, r0, LSR #8\r | |
39 | bcc ASM_PFX(__arm_div8)\r | |
40 | mov r3, #0\r | |
41 | b ASM_PFX(__arm_div_large)\r | |
42 | \r | |
43 | #\r | |
44 | #INT32\r | |
45 | #EFIAPI\r | |
46 | #__aeabi_idivmode (\r | |
47 | # IN INT32 Dividen\r | |
48 | # IN INT32 Divisor\r | |
49 | # );\r | |
50 | #\r | |
51 | ASM_PFX(__aeabi_idiv):\r | |
52 | ASM_PFX(__aeabi_idivmod):\r | |
53 | orrs r12, r0, r1\r | |
54 | bmi ASM_PFX(__arm_div_negative)\r | |
55 | rsbs r12, r1, r0, LSR #1\r | |
56 | mov r2, #0\r | |
57 | bcc ASM_PFX(__arm_div1)\r | |
58 | rsbs r12, r1, r0, LSR #4\r | |
59 | bcc ASM_PFX(__arm_div4)\r | |
60 | rsbs r12, r1, r0, LSR #8\r | |
61 | bcc ASM_PFX(__arm_div8)\r | |
62 | mov r3, #0\r | |
63 | b ASM_PFX(__arm_div_large)\r | |
64 | ASM_PFX(__arm_div8):\r | |
65 | rsbs r12, r1, r0, LSR #7\r | |
66 | subcs r0, r0, r1, LSL #7\r | |
67 | adc r2, r2, r2\r | |
68 | rsbs r12, r1, r0,LSR #6\r | |
69 | subcs r0, r0, r1, LSL #6\r | |
70 | adc r2, r2, r2\r | |
71 | rsbs r12, r1, r0, LSR #5\r | |
72 | subcs r0, r0, r1, LSL #5\r | |
73 | adc r2, r2, r2\r | |
74 | rsbs r12, r1, r0, LSR #4\r | |
75 | subcs r0, r0, r1, LSL #4\r | |
76 | adc r2, r2, r2\r | |
77 | ASM_PFX(__arm_div4):\r | |
78 | rsbs r12, r1, r0, LSR #3\r | |
79 | subcs r0, r0, r1, LSL #3\r | |
80 | adc r2, r2, r2\r | |
81 | rsbs r12, r1, r0, LSR #2\r | |
82 | subcs r0, r0, r1, LSL #2\r | |
83 | adcs r2, r2, r2\r | |
84 | rsbs r12, r1, r0, LSR #1\r | |
85 | subcs r0, r0, r1, LSL #1\r | |
86 | adc r2, r2, r2\r | |
87 | ASM_PFX(__arm_div1):\r | |
88 | subs r1, r0, r1\r | |
89 | movcc r1, r0\r | |
90 | adc r0, r2, r2\r | |
91 | bx r14\r | |
92 | ASM_PFX(__arm_div_negative):\r | |
93 | ands r2, r1, #0x80000000\r | |
94 | rsbmi r1, r1, #0\r | |
95 | eors r3, r2, r0, ASR #32\r | |
96 | rsbcs r0, r0, #0\r | |
97 | rsbs r12, r1, r0, LSR #4\r | |
98 | bcc label1\r | |
99 | rsbs r12, r1, r0, LSR #8\r | |
100 | bcc label2\r | |
101 | ASM_PFX(__arm_div_large):\r | |
102 | lsl r1, r1, #6\r | |
103 | rsbs r12, r1, r0, LSR #8\r | |
104 | orr r2, r2, #0xfc000000\r | |
105 | bcc label2\r | |
106 | lsl r1, r1, #6\r | |
107 | rsbs r12, r1, r0, LSR #8\r | |
108 | orr r2, r2, #0x3f00000\r | |
109 | bcc label2\r | |
110 | lsl r1, r1, #6\r | |
111 | rsbs r12, r1, r0, LSR #8\r | |
112 | orr r2, r2, #0xfc000\r | |
113 | orrcs r2, r2, #0x3f00\r | |
114 | lslcs r1, r1, #6\r | |
115 | rsbs r12, r1, #0\r | |
116 | bcs ASM_PFX(__aeabi_idiv0)\r | |
117 | label3:\r | |
118 | lsrcs r1, r1, #6\r | |
119 | label2:\r | |
120 | rsbs r12, r1, r0, LSR #7\r | |
121 | subcs r0, r0, r1, LSL #7\r | |
122 | adc r2, r2, r2\r | |
123 | rsbs r12, r1, r0, LSR #6\r | |
124 | subcs r0, r0, r1, LSL #6\r | |
125 | adc r2, r2, r2\r | |
126 | rsbs r12, r1, r0, LSR #5\r | |
127 | subcs r0, r0, r1, LSL #5\r | |
128 | adc r2, r2, r2\r | |
129 | rsbs r12, r1, r0, LSR #4\r | |
130 | subcs r0, r0, r1, LSL #4\r | |
131 | adc r2, r2, r2\r | |
132 | label1:\r | |
133 | rsbs r12, r1, r0, LSR #3\r | |
134 | subcs r0, r0, r1, LSL #3\r | |
135 | adc r2, r2, r2\r | |
136 | rsbs r12, r1, r0, LSR #2\r | |
137 | subcs r0, r0, r1, LSL #2\r | |
138 | adcs r2, r2, r2\r | |
139 | bcs label3\r | |
140 | rsbs r12, r1, r0, LSR #1\r | |
141 | subcs r0, r0, r1, LSL #1\r | |
142 | adc r2, r2, r2\r | |
143 | subs r1, r0, r1\r | |
144 | movcc r1, r0\r | |
145 | adc r0, r2, r2\r | |
146 | asrs r3, r3, #31\r | |
147 | rsbmi r0, r0, #0\r | |
148 | rsbcs r1, r1, #0\r | |
149 | bx r14\r | |
150 | \r | |
151 | @ What to do about division by zero? For now, just return.\r | |
152 | ASM_PFX(__aeabi_idiv0):\r | |
153 | bx r14\r |