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1 | /** @file\r |
2 | *\r | |
3 | * Copyright (c) 2013-2014, ARM Limited. All rights reserved.\r | |
4 | *\r | |
5 | * This program and the accompanying materials\r | |
6 | * are licensed and made available under the terms and conditions of the BSD License\r | |
7 | * which accompanies this distribution. The full text of the license may be found at\r | |
8 | * http://opensource.org/licenses/bsd-license.php\r | |
9 | *\r | |
10 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | *\r | |
13 | **/\r | |
14 | \r | |
15 | #ifndef __ARM_JUNO_H__\r | |
16 | #define __ARM_JUNO_H__\r | |
17 | \r | |
18 | #include <VExpressMotherBoard.h>\r | |
19 | \r | |
20 | /***********************************************************************************\r | |
21 | // Platform Memory Map\r | |
22 | ************************************************************************************/\r | |
23 | \r | |
24 | // Motherboard Peripheral and On-chip peripheral\r | |
25 | #define ARM_VE_BOARD_PERIPH_BASE 0x1C010000\r | |
26 | \r | |
27 | // NOR Flash 0\r | |
28 | #define ARM_VE_SMB_NOR0_BASE 0x08000000\r | |
29 | #define ARM_VE_SMB_NOR0_SZ SIZE_64MB\r | |
30 | \r | |
31 | // Off-Chip peripherals (USB, Ethernet, VRAM)\r | |
32 | #define ARM_VE_SMB_PERIPH_BASE 0x18000000\r | |
33 | #define ARM_VE_SMB_PERIPH_SZ (SIZE_64MB + SIZE_2MB)\r | |
34 | \r | |
35 | // On-Chip non-secure ROM\r | |
36 | #define ARM_JUNO_NON_SECURE_ROM_BASE 0x1F000000\r | |
37 | #define ARM_JUNO_NON_SECURE_ROM_SZ SIZE_16MB\r | |
38 | \r | |
39 | // On-Chip Peripherals\r | |
40 | #define ARM_JUNO_PERIPHERALS_BASE 0x20000000\r | |
41 | #define ARM_JUNO_PERIPHERALS_SZ 0x0E000000\r | |
42 | \r | |
43 | // On-Chip non-secure SRAM\r | |
44 | #define ARM_JUNO_NON_SECURE_SRAM_BASE 0x2E000000\r | |
45 | #define ARM_JUNO_NON_SECURE_SRAM_SZ SIZE_16MB\r | |
46 | \r | |
47 | // SOC peripherals (HDLCD, UART, I2C, I2S, USB, SMC-PL354, etc)\r | |
48 | #define ARM_JUNO_SOC_PERIPHERALS_BASE 0x7FF50000\r | |
49 | #define ARM_JUNO_SOC_PERIPHERALS_SZ (SIZE_64KB * 9)\r | |
50 | \r | |
51 | // 6GB of DRAM from the 64bit address space\r | |
52 | #define ARM_JUNO_EXTRA_SYSTEM_MEMORY_BASE 0x0880000000\r | |
53 | #define ARM_JUNO_EXTRA_SYSTEM_MEMORY_SZ (SIZE_2GB + SIZE_4GB)\r | |
54 | \r | |
3399d5be OM |
55 | //\r |
56 | // ACPI table information used to initialize tables.\r | |
57 | //\r | |
58 | #define EFI_ACPI_ARM_OEM_ID 'A','R','M','L','T','D' // OEMID 6 bytes long\r | |
59 | #define EFI_ACPI_ARM_OEM_TABLE_ID SIGNATURE_64('A','R','M','-','J','U','N','O') // OEM table id 8 bytes long\r | |
60 | #define EFI_ACPI_ARM_OEM_REVISION 0x20140727\r | |
61 | #define EFI_ACPI_ARM_CREATOR_ID SIGNATURE_32('A','R','M',' ')\r | |
62 | #define EFI_ACPI_ARM_CREATOR_REVISION 0x00000099\r | |
63 | \r | |
64 | // A macro to initialise the common header part of EFI ACPI tables as defined by\r | |
65 | // EFI_ACPI_DESCRIPTION_HEADER structure.\r | |
66 | #define ARM_ACPI_HEADER(Signature, Type, Revision) { \\r | |
67 | Signature, /* UINT32 Signature */ \\r | |
68 | sizeof (Type), /* UINT32 Length */ \\r | |
69 | Revision, /* UINT8 Revision */ \\r | |
70 | 0, /* UINT8 Checksum */ \\r | |
71 | { EFI_ACPI_ARM_OEM_ID }, /* UINT8 OemId[6] */ \\r | |
72 | EFI_ACPI_ARM_OEM_TABLE_ID, /* UINT64 OemTableId */ \\r | |
73 | EFI_ACPI_ARM_OEM_REVISION, /* UINT32 OemRevision */ \\r | |
74 | EFI_ACPI_ARM_CREATOR_ID, /* UINT32 CreatorId */ \\r | |
75 | EFI_ACPI_ARM_CREATOR_REVISION /* UINT32 CreatorRevision */ \\r | |
76 | }\r | |
77 | \r | |
9f38945f | 78 | #endif\r |