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11c20f4e | 1 | #/** @file\r |
2 | #\r | |
7dfe9309 | 3 | # Copyright (c) 2011-2016, ARM Limited. All rights reserved.\r |
ad7a56e5 | 4 | # Copyright (c) 2015, Intel Corporation. All rights reserved.\r |
11c20f4e | 5 | #\r |
3402aac7 RC |
6 | # This program and the accompanying materials\r |
7 | # are licensed and made available under the terms and conditions of the BSD License\r | |
8 | # which accompanies this distribution. The full text of the license may be found at\r | |
9 | # http://opensource.org/licenses/bsd-license.php\r | |
10 | #\r | |
11 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
11c20f4e | 13 | #\r |
14 | #**/\r | |
15 | \r | |
16 | [Defines]\r | |
17 | DEC_SPECIFICATION = 0x00010005\r | |
18 | PACKAGE_NAME = ArmPlatformPkg\r | |
3402aac7 | 19 | PACKAGE_GUID = 3308e0a0-1d94-11e0-915c-0002a5d5c51b\r |
11c20f4e | 20 | PACKAGE_VERSION = 0.1\r |
21 | \r | |
22 | ################################################################################\r | |
23 | #\r | |
24 | # Include Section - list of Include Paths that are provided by this package.\r | |
25 | # Comments are used for Keywords and Module Types.\r | |
26 | #\r | |
27 | # Supported Module Types:\r | |
28 | # BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION\r | |
29 | #\r | |
30 | ################################################################################\r | |
31 | [Includes.common]\r | |
32 | Include # Root include for the package\r | |
33 | \r | |
34 | [Guids.common]\r | |
35 | gArmPlatformTokenSpaceGuid = { 0x9c0aaed4, 0x74c5, 0x4043, { 0xb4, 0x17, 0xa3, 0x22, 0x38, 0x14, 0xce, 0x76 } }\r | |
36 | #\r | |
37 | # Following Guid must match FILE_GUID in MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf\r | |
38 | #\r | |
39 | gVariableRuntimeDxeFileGuid = { 0xcbd2e4d5, 0x7068, 0x4ff5, { 0xb4, 0x62, 0x98, 0x22, 0xb4, 0xad, 0x8d, 0x60 } }\r | |
40 | \r | |
da5daf36 HL |
41 | gArmBootMonFsFileInfoGuid = { 0x41e26b9c, 0xada6, 0x45b3, { 0x80, 0x8e, 0x23, 0x57, 0xa3, 0x5b, 0x60, 0xd6 } }\r |
42 | \r | |
11c20f4e | 43 | [PcdsFeatureFlag.common]\r |
44 | # Set this PCD to TRUE to map NORFlash at 0x0. FALSE means the DRAM is mapped at 0x0.\r | |
45 | gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping|FALSE|BOOLEAN|0x00000012\r | |
3402aac7 | 46 | \r |
11c20f4e | 47 | gArmPlatformTokenSpaceGuid.PcdStandalone|TRUE|BOOLEAN|0x00000001\r |
48 | gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|FALSE|BOOLEAN|0x00000002\r | |
49 | gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|FALSE|BOOLEAN|0x00000004\r | |
50 | \r | |
68dda854 | 51 | gArmPlatformTokenSpaceGuid.PcdNorFlashCheckBlockLocked|FALSE|BOOLEAN|0x0000003C\r |
d8c4bb9a OM |
52 | \r |
53 | # Disable the GOP controller on ExitBootServices(). By default the value is FALSE,\r | |
54 | # we assume the OS will handle the FrameBuffer from the UEFI GOP information.\r | |
55 | gArmPlatformTokenSpaceGuid.PcdGopDisableOnExitBootServices|FALSE|BOOLEAN|0x0000003D\r | |
56 | \r | |
5d9e9d1a OM |
57 | # Enable Legacy Linux support in the BDS\r |
58 | gArmPlatformTokenSpaceGuid.PcdBdsLinuxSupport|TRUE|BOOLEAN|0x0000002E\r | |
59 | \r | |
11c20f4e | 60 | [PcdsFixedAtBuild.common]\r |
695df8ba | 61 | gArmPlatformTokenSpaceGuid.PcdCoreCount|1|UINT32|0x00000039\r |
2dbcb8f0 | 62 | gArmPlatformTokenSpaceGuid.PcdClusterCount|1|UINT32|0x00000038\r |
3402aac7 | 63 | \r |
11c20f4e | 64 | # Stack for CPU Cores in Secure Mode\r |
91673dfd | 65 | gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0|UINT64|0x00000005\r |
2dbcb8f0 | 66 | gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x10000|UINT32|0x00000036\r |
67 | gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize|0x1000|UINT32|0x00000006\r | |
11c20f4e | 68 | \r |
11c20f4e | 69 | # Stack for CPU Cores in Non Secure Mode\r |
bb5420bb | 70 | gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0|UINT64|0x00000009\r |
2dbcb8f0 | 71 | gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000|UINT32|0x00000037\r |
72 | gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x1000|UINT32|0x0000000A\r | |
3402aac7 | 73 | \r |
11c20f4e | 74 | # Size of the region used by UEFI in permanent memory (Reserved 128MB by default)\r |
75 | gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x08000000|UINT32|0x00000015\r | |
76 | \r | |
94e0955d OM |
77 | # Boot Monitor FileSystem\r |
78 | gArmPlatformTokenSpaceGuid.PcdBootMonFsSupportedDevicePaths|L""|VOID*|0x0000003A\r | |
79 | \r | |
11c20f4e | 80 | #\r |
81 | # ARM Primecells\r | |
82 | #\r | |
83 | \r | |
84 | ## SP804 DualTimer\r | |
85 | gArmPlatformTokenSpaceGuid.PcdSP804TimerFrequencyInMHz|1|UINT32|0x0000001D\r | |
86 | gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicInterruptNum|0|UINT32|0x0000001E\r | |
87 | gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicBase|0|UINT32|0x0000002A\r | |
88 | gArmPlatformTokenSpaceGuid.PcdSP804TimerPerformanceBase|0|UINT32|0x0000002B\r | |
89 | gArmPlatformTokenSpaceGuid.PcdSP804TimerMetronomeBase|0|UINT32|0x0000002C\r | |
90 | \r | |
91 | ## SP805 Watchdog\r | |
92 | gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x0|UINT32|0x00000023\r | |
93 | gArmPlatformTokenSpaceGuid.PcdSP805WatchdogClockFrequencyInHz|32000|UINT32|0x00000021\r | |
94 | \r | |
95 | ## PL011 UART\r | |
051e63bb | 96 | gArmPlatformTokenSpaceGuid.PL011UartClkInHz|24000000|UINT32|0x0000001F\r |
97 | gArmPlatformTokenSpaceGuid.PL011UartInteger|0|UINT32|0x00000020\r | |
98 | gArmPlatformTokenSpaceGuid.PL011UartFractional|0|UINT32|0x0000002D\r | |
7dfe9309 | 99 | gArmPlatformTokenSpaceGuid.PL011UartInterrupt|0x00000000|UINT32|0x0000002F\r |
11c20f4e | 100 | \r |
11c20f4e | 101 | ## PL061 GPIO\r |
102 | gArmPlatformTokenSpaceGuid.PcdPL061GpioBase|0x0|UINT32|0x00000025\r | |
3402aac7 | 103 | \r |
98622390 | 104 | ## PL111 Lcd & HdLcd\r |
11c20f4e | 105 | gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x0|UINT32|0x00000026\r |
106 | gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase|0x0|UINT32|0x00000027\r | |
3402aac7 | 107 | \r |
11c20f4e | 108 | ## PL180 MCI\r |
109 | gArmPlatformTokenSpaceGuid.PcdPL180SysMciRegAddress|0x00000000|UINT32|0x00000028\r | |
110 | gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress|0x00000000|UINT32|0x00000029\r | |
111 | \r | |
112 | #\r | |
113 | # BDS - Boot Manager\r | |
114 | #\r | |
115 | gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Platform"|VOID*|0x00000019\r | |
116 | gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Default Boot Device"|VOID*|0x0000000C\r | |
117 | gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L""|VOID*|0x0000000D\r | |
6bcedcec | 118 | gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|L""|VOID*|0x000000F\r |
3402aac7 | 119 | \r |
11c20f4e | 120 | gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L""|VOID*|0x0000001B\r |
121 | gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L""|VOID*|0x0000001C\r | |
1bc83266 | 122 | \r |
b4e2799b AB |
123 | [PcdsFixedAtBuild.common,PcdsDynamic.common]\r |
124 | ## PL031 RealTimeClock\r | |
125 | gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0|UINT32|0x00000024\r | |
126 | gArmPlatformTokenSpaceGuid.PcdPL031RtcPpmAccuracy|300000000|UINT32|0x00000022\r | |
127 | \r | |
e48f1f15 LE |
128 | #\r |
129 | # Inclusive range of allowed PCI buses.\r | |
130 | #\r | |
131 | gArmPlatformTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x0000003E\r | |
132 | gArmPlatformTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x0000003F\r | |
133 | \r | |
134 | #\r | |
135 | # Bases, sizes and translation offsets of IO and MMIO spaces, respectively.\r | |
136 | # Note that "IO" is just another MMIO range that simulates IO space; there\r | |
137 | # are no special instructions to access it.\r | |
138 | #\r | |
139 | # The base addresses PcdPciIoBase, PcdPciMmio32Base and PcdPciMmio64Base are\r | |
140 | # specific to their containing address spaces. In order to get the physical\r | |
141 | # address for the CPU, for a given access, the respective translation value\r | |
142 | # has to be added.\r | |
143 | #\r | |
144 | # The translations always have to be initialized like this, using UINT64:\r | |
145 | #\r | |
146 | # UINT64 IoCpuBase; // mapping target in 64-bit cpu-physical space\r | |
147 | # UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space\r | |
148 | # UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space\r | |
149 | #\r | |
150 | # PcdPciIoTranslation = IoCpuBase - PcdPciIoBase;\r | |
151 | # PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base;\r | |
152 | # PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base;\r | |
153 | #\r | |
154 | # because (a) the target address space (ie. the cpu-physical space) is\r | |
155 | # 64-bit, and (b) the translation values are meant as offsets for *modular*\r | |
156 | # arithmetic.\r | |
157 | #\r | |
158 | # Accordingly, the translation itself needs to be implemented as:\r | |
159 | #\r | |
160 | # UINT64 UntranslatedIoAddress; // input parameter\r | |
161 | # UINT32 UntranslatedMmio32Address; // input parameter\r | |
162 | # UINT64 UntranslatedMmio64Address; // input parameter\r | |
163 | #\r | |
164 | # UINT64 TranslatedIoAddress; // output parameter\r | |
165 | # UINT64 TranslatedMmio32Address; // output parameter\r | |
166 | # UINT64 TranslatedMmio64Address; // output parameter\r | |
167 | #\r | |
168 | # TranslatedIoAddress = UntranslatedIoAddress +\r | |
169 | # PcdPciIoTranslation;\r | |
170 | # TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address +\r | |
171 | # PcdPciMmio32Translation;\r | |
172 | # TranslatedMmio64Address = UntranslatedMmio64Address +\r | |
173 | # PcdPciMmio64Translation;\r | |
174 | #\r | |
175 | # The modular arithmetic performed in UINT64 ensures that the translation\r | |
176 | # works correctly regardless of the relation between IoCpuBase and\r | |
177 | # PcdPciIoBase, Mmio32CpuBase and PcdPciMmio32Base, and Mmio64CpuBase and\r | |
178 | # PcdPciMmio64Base.\r | |
179 | #\r | |
180 | gArmPlatformTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00000040\r | |
181 | gArmPlatformTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00000041\r | |
182 | gArmPlatformTokenSpaceGuid.PcdPciIoTranslation|0x0|UINT64|0x00000042\r | |
183 | gArmPlatformTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT32|0x00000043\r | |
184 | gArmPlatformTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT32|0x00000044\r | |
185 | gArmPlatformTokenSpaceGuid.PcdPciMmio32Translation|0x0|UINT64|0x00000045\r | |
186 | gArmPlatformTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x00000046\r | |
187 | gArmPlatformTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x00000047\r | |
188 | gArmPlatformTokenSpaceGuid.PcdPciMmio64Translation|0x0|UINT64|0x00000048\r | |
189 | \r | |
1bc83266 HL |
190 | [PcdsFixedAtBuild.ARM]\r |
191 | # Stack for CPU Cores in Secure Monitor Mode\r | |
91673dfd | 192 | gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT64|0x00000007\r |
1bc83266 HL |
193 | gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x1000|UINT32|0x00000008\r |
194 | \r | |
195 | [PcdsFixedAtBuild.AARCH64]\r | |
196 | # The Secure World is only running in EL3. Only one set of stacks is needed for AArch64.\r | |
197 | # The Secure stacks are described by PcdCPUCoresSecStackBase, PcdCPUCoreSecPrimaryStackSize\r | |
198 | # and PcdCPUCoreSecSecondaryStackSize\r | |
91673dfd | 199 | gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT64|0x00000007\r |
1bc83266 HL |
200 | gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x0|UINT32|0x00000008\r |
201 | \r |