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11c20f4e | 1 | #/** @file\r |
2 | #\r | |
ecfe4796 | 3 | # Copyright (c) 2011-2021, ARM Limited. All rights reserved.\r |
ad7a56e5 | 4 | # Copyright (c) 2015, Intel Corporation. All rights reserved.\r |
11c20f4e | 5 | #\r |
f4dfad05 | 6 | # SPDX-License-Identifier: BSD-2-Clause-Patent\r |
11c20f4e | 7 | #\r |
8 | #**/\r | |
9 | \r | |
10 | [Defines]\r | |
11 | DEC_SPECIFICATION = 0x00010005\r | |
12 | PACKAGE_NAME = ArmPlatformPkg\r | |
3402aac7 | 13 | PACKAGE_GUID = 3308e0a0-1d94-11e0-915c-0002a5d5c51b\r |
11c20f4e | 14 | PACKAGE_VERSION = 0.1\r |
15 | \r | |
16 | ################################################################################\r | |
17 | #\r | |
18 | # Include Section - list of Include Paths that are provided by this package.\r | |
19 | # Comments are used for Keywords and Module Types.\r | |
20 | #\r | |
21 | # Supported Module Types:\r | |
22 | # BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION\r | |
23 | #\r | |
24 | ################################################################################\r | |
25 | [Includes.common]\r | |
26 | Include # Root include for the package\r | |
27 | \r | |
12156134 | 28 | [LibraryClasses]\r |
ecfe4796 PG |
29 | ## @libraryclass Provides an interface to query platform information.\r |
30 | #\r | |
d9b53608 | 31 | ArmPlatformLib|Include/Library/ArmPlatformLib.h\r |
ecfe4796 PG |
32 | \r |
33 | ## @libraryclass Provides an interface to initialize/shutdown a LCD screen.\r | |
34 | #\r | |
99cfb43a | 35 | LcdHwLib|Include/Library/LcdHwLib.h\r |
ecfe4796 PG |
36 | \r |
37 | ## @libraryclass Provides an interface to configure a LCD screen.\r | |
38 | #\r | |
d9b53608 | 39 | LcdPlatformLib|Include/Library/LcdPlatformLib.h\r |
ecfe4796 PG |
40 | \r |
41 | ## @libraryclass Provides a Nor flash interface.\r | |
42 | #\r | |
d9b53608 | 43 | NorFlashPlatformLib|Include/Library/NorFlashPlatformLib.h\r |
ecfe4796 PG |
44 | \r |
45 | ## @libraryclass Provides an interface to the clock of a PL011 device.\r | |
46 | #\r | |
cbba5ca1 | 47 | PL011UartClockLib|Include/Library/PL011UartClockLib.h\r |
ecfe4796 PG |
48 | \r |
49 | ## @libraryclass Provides an interface to a PL011 uart.\r | |
50 | #\r | |
12156134 AB |
51 | PL011UartLib|Include/Library/PL011UartLib.h\r |
52 | \r | |
11c20f4e | 53 | [Guids.common]\r |
54 | gArmPlatformTokenSpaceGuid = { 0x9c0aaed4, 0x74c5, 0x4043, { 0xb4, 0x17, 0xa3, 0x22, 0x38, 0x14, 0xce, 0x76 } }\r | |
11c20f4e | 55 | \r |
56 | [PcdsFeatureFlag.common]\r | |
11c20f4e | 57 | gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|FALSE|BOOLEAN|0x00000004\r |
58 | \r | |
68dda854 | 59 | gArmPlatformTokenSpaceGuid.PcdNorFlashCheckBlockLocked|FALSE|BOOLEAN|0x0000003C\r |
d8c4bb9a OM |
60 | \r |
61 | # Disable the GOP controller on ExitBootServices(). By default the value is FALSE,\r | |
62 | # we assume the OS will handle the FrameBuffer from the UEFI GOP information.\r | |
63 | gArmPlatformTokenSpaceGuid.PcdGopDisableOnExitBootServices|FALSE|BOOLEAN|0x0000003D\r | |
64 | \r | |
11c20f4e | 65 | [PcdsFixedAtBuild.common]\r |
695df8ba | 66 | gArmPlatformTokenSpaceGuid.PcdCoreCount|1|UINT32|0x00000039\r |
2dbcb8f0 | 67 | gArmPlatformTokenSpaceGuid.PcdClusterCount|1|UINT32|0x00000038\r |
3402aac7 | 68 | \r |
11c20f4e | 69 | # Stack for CPU Cores in Non Secure Mode\r |
bb5420bb | 70 | gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0|UINT64|0x00000009\r |
2dbcb8f0 | 71 | gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000|UINT32|0x00000037\r |
72 | gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x1000|UINT32|0x0000000A\r | |
3402aac7 | 73 | \r |
11c20f4e | 74 | # Size of the region used by UEFI in permanent memory (Reserved 128MB by default)\r |
75 | gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x08000000|UINT32|0x00000015\r | |
76 | \r | |
11c20f4e | 77 | #\r |
78 | # ARM Primecells\r | |
79 | #\r | |
80 | \r | |
11c20f4e | 81 | ## SP805 Watchdog\r |
82 | gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x0|UINT32|0x00000023\r | |
83 | gArmPlatformTokenSpaceGuid.PcdSP805WatchdogClockFrequencyInHz|32000|UINT32|0x00000021\r | |
5afabd5e | 84 | gArmPlatformTokenSpaceGuid.PcdSP805WatchdogInterrupt|0|UINT32|0x0000002E\r |
11c20f4e | 85 | \r |
86 | ## PL011 UART\r | |
051e63bb | 87 | gArmPlatformTokenSpaceGuid.PL011UartClkInHz|24000000|UINT32|0x0000001F\r |
88 | gArmPlatformTokenSpaceGuid.PL011UartInteger|0|UINT32|0x00000020\r | |
89 | gArmPlatformTokenSpaceGuid.PL011UartFractional|0|UINT32|0x0000002D\r | |
7dfe9309 | 90 | gArmPlatformTokenSpaceGuid.PL011UartInterrupt|0x00000000|UINT32|0x0000002F\r |
d4f6c35c | 91 | gArmPlatformTokenSpaceGuid.PL011UartRegOffsetVariant|0|UINT8|0x0000003E\r |
11c20f4e | 92 | \r |
0312b14d EL |
93 | ## PL011 Serial Debug UART\r |
94 | gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|0x00000000|UINT64|0x00000030\r | |
95 | gArmPlatformTokenSpaceGuid.PcdSerialDbgUartBaudRate|0x00000000|UINT64|0x00000031\r | |
96 | gArmPlatformTokenSpaceGuid.PcdSerialDbgUartClkInHz|0x00000000|UINT32|0x00000032\r | |
97 | \r | |
11c20f4e | 98 | ## PL061 GPIO\r |
99 | gArmPlatformTokenSpaceGuid.PcdPL061GpioBase|0x0|UINT32|0x00000025\r | |
3402aac7 | 100 | \r |
98622390 | 101 | ## PL111 Lcd & HdLcd\r |
11c20f4e | 102 | gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x0|UINT32|0x00000026\r |
103 | gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase|0x0|UINT32|0x00000027\r | |
3402aac7 | 104 | \r |
36bbbf4f GP |
105 | ## Default size for display modes upto 1920x1080 (1920 * 1080 * 4 Bytes Per Pixel)\r |
106 | gArmPlatformTokenSpaceGuid.PcdArmLcdDdrFrameBufferSize|0x7E9000|UINT32|0x00000043\r | |
107 | ## If set, framebuffer memory will be reserved and mapped in the system RAM\r | |
108 | gArmPlatformTokenSpaceGuid.PcdArmLcdDdrFrameBufferBase|0x0|UINT64|0x00000044\r | |
109 | \r | |
b99f8126 GP |
110 | ## ARM Mali Display Processor DP500/DP550/DP650\r |
111 | gArmPlatformTokenSpaceGuid.PcdArmMaliDpBase|0x0|UINT64|0x00000050\r | |
112 | gArmPlatformTokenSpaceGuid.PcdArmMaliDpMemoryRegionLength|0x0|UINT32|0x00000051\r | |
113 | \r | |
fe787dfb GP |
114 | # Graphics Output Pixel format\r |
115 | # 0 : PixelRedGreenBlueReserved8BitPerColor\r | |
116 | # 1 : PixelBlueGreenRedReserved8BitPerColor\r | |
117 | # 2 : PixelBitMask\r | |
118 | # Default is set to UEFI console font format PixelBlueGreenRedReserved8BitPerColor\r | |
119 | gArmPlatformTokenSpaceGuid.PcdGopPixelFormat|0x00000001|UINT32|0x00000040\r | |
120 | \r | |
268aad67 GP |
121 | ## If set, this will swap settings for HDLCD RED_SELECT and BLUE_SELECT registers\r |
122 | gArmPlatformTokenSpaceGuid.PcdArmHdLcdSwapBlueRedSelect|FALSE|BOOLEAN|0x00000045\r | |
123 | \r | |
b4e2799b AB |
124 | [PcdsFixedAtBuild.common,PcdsDynamic.common]\r |
125 | ## PL031 RealTimeClock\r | |
126 | gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0|UINT32|0x00000024\r | |
127 | gArmPlatformTokenSpaceGuid.PcdPL031RtcPpmAccuracy|300000000|UINT32|0x00000022\r | |
128 | \r | |
08e94eee | 129 | gArmPlatformTokenSpaceGuid.PcdWatchdogCount|0x0|UINT32|0x00000033\r |