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11c20f4e | 1 | #/** @file\r |
2 | #\r | |
fe787dfb | 3 | # Copyright (c) 2011-2018, ARM Limited. All rights reserved.\r |
ad7a56e5 | 4 | # Copyright (c) 2015, Intel Corporation. All rights reserved.\r |
11c20f4e | 5 | #\r |
3402aac7 RC |
6 | # This program and the accompanying materials\r |
7 | # are licensed and made available under the terms and conditions of the BSD License\r | |
8 | # which accompanies this distribution. The full text of the license may be found at\r | |
9 | # http://opensource.org/licenses/bsd-license.php\r | |
10 | #\r | |
11 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
11c20f4e | 13 | #\r |
14 | #**/\r | |
15 | \r | |
16 | [Defines]\r | |
17 | DEC_SPECIFICATION = 0x00010005\r | |
18 | PACKAGE_NAME = ArmPlatformPkg\r | |
3402aac7 | 19 | PACKAGE_GUID = 3308e0a0-1d94-11e0-915c-0002a5d5c51b\r |
11c20f4e | 20 | PACKAGE_VERSION = 0.1\r |
21 | \r | |
22 | ################################################################################\r | |
23 | #\r | |
24 | # Include Section - list of Include Paths that are provided by this package.\r | |
25 | # Comments are used for Keywords and Module Types.\r | |
26 | #\r | |
27 | # Supported Module Types:\r | |
28 | # BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION\r | |
29 | #\r | |
30 | ################################################################################\r | |
31 | [Includes.common]\r | |
32 | Include # Root include for the package\r | |
33 | \r | |
12156134 | 34 | [LibraryClasses]\r |
d9b53608 | 35 | ArmPlatformLib|Include/Library/ArmPlatformLib.h\r |
99cfb43a | 36 | LcdHwLib|Include/Library/LcdHwLib.h\r |
d9b53608 AB |
37 | LcdPlatformLib|Include/Library/LcdPlatformLib.h\r |
38 | NorFlashPlatformLib|Include/Library/NorFlashPlatformLib.h\r | |
cbba5ca1 | 39 | PL011UartClockLib|Include/Library/PL011UartClockLib.h\r |
12156134 AB |
40 | PL011UartLib|Include/Library/PL011UartLib.h\r |
41 | \r | |
11c20f4e | 42 | [Guids.common]\r |
43 | gArmPlatformTokenSpaceGuid = { 0x9c0aaed4, 0x74c5, 0x4043, { 0xb4, 0x17, 0xa3, 0x22, 0x38, 0x14, 0xce, 0x76 } }\r | |
11c20f4e | 44 | \r |
45 | [PcdsFeatureFlag.common]\r | |
11c20f4e | 46 | gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|FALSE|BOOLEAN|0x00000004\r |
47 | \r | |
68dda854 | 48 | gArmPlatformTokenSpaceGuid.PcdNorFlashCheckBlockLocked|FALSE|BOOLEAN|0x0000003C\r |
d8c4bb9a OM |
49 | \r |
50 | # Disable the GOP controller on ExitBootServices(). By default the value is FALSE,\r | |
51 | # we assume the OS will handle the FrameBuffer from the UEFI GOP information.\r | |
52 | gArmPlatformTokenSpaceGuid.PcdGopDisableOnExitBootServices|FALSE|BOOLEAN|0x0000003D\r | |
53 | \r | |
11c20f4e | 54 | [PcdsFixedAtBuild.common]\r |
695df8ba | 55 | gArmPlatformTokenSpaceGuid.PcdCoreCount|1|UINT32|0x00000039\r |
2dbcb8f0 | 56 | gArmPlatformTokenSpaceGuid.PcdClusterCount|1|UINT32|0x00000038\r |
3402aac7 | 57 | \r |
11c20f4e | 58 | # Stack for CPU Cores in Non Secure Mode\r |
bb5420bb | 59 | gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0|UINT64|0x00000009\r |
2dbcb8f0 | 60 | gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000|UINT32|0x00000037\r |
61 | gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x1000|UINT32|0x0000000A\r | |
3402aac7 | 62 | \r |
11c20f4e | 63 | # Size of the region used by UEFI in permanent memory (Reserved 128MB by default)\r |
64 | gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x08000000|UINT32|0x00000015\r | |
65 | \r | |
11c20f4e | 66 | #\r |
67 | # ARM Primecells\r | |
68 | #\r | |
69 | \r | |
11c20f4e | 70 | ## SP805 Watchdog\r |
71 | gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x0|UINT32|0x00000023\r | |
72 | gArmPlatformTokenSpaceGuid.PcdSP805WatchdogClockFrequencyInHz|32000|UINT32|0x00000021\r | |
5afabd5e | 73 | gArmPlatformTokenSpaceGuid.PcdSP805WatchdogInterrupt|0|UINT32|0x0000002E\r |
11c20f4e | 74 | \r |
75 | ## PL011 UART\r | |
051e63bb | 76 | gArmPlatformTokenSpaceGuid.PL011UartClkInHz|24000000|UINT32|0x0000001F\r |
77 | gArmPlatformTokenSpaceGuid.PL011UartInteger|0|UINT32|0x00000020\r | |
78 | gArmPlatformTokenSpaceGuid.PL011UartFractional|0|UINT32|0x0000002D\r | |
7dfe9309 | 79 | gArmPlatformTokenSpaceGuid.PL011UartInterrupt|0x00000000|UINT32|0x0000002F\r |
d4f6c35c | 80 | gArmPlatformTokenSpaceGuid.PL011UartRegOffsetVariant|0|UINT8|0x0000003E\r |
11c20f4e | 81 | \r |
0312b14d EL |
82 | ## PL011 Serial Debug UART\r |
83 | gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|0x00000000|UINT64|0x00000030\r | |
84 | gArmPlatformTokenSpaceGuid.PcdSerialDbgUartBaudRate|0x00000000|UINT64|0x00000031\r | |
85 | gArmPlatformTokenSpaceGuid.PcdSerialDbgUartClkInHz|0x00000000|UINT32|0x00000032\r | |
86 | \r | |
11c20f4e | 87 | ## PL061 GPIO\r |
88 | gArmPlatformTokenSpaceGuid.PcdPL061GpioBase|0x0|UINT32|0x00000025\r | |
3402aac7 | 89 | \r |
98622390 | 90 | ## PL111 Lcd & HdLcd\r |
11c20f4e | 91 | gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x0|UINT32|0x00000026\r |
92 | gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase|0x0|UINT32|0x00000027\r | |
3402aac7 | 93 | \r |
36bbbf4f GP |
94 | ## Default size for display modes upto 1920x1080 (1920 * 1080 * 4 Bytes Per Pixel)\r |
95 | gArmPlatformTokenSpaceGuid.PcdArmLcdDdrFrameBufferSize|0x7E9000|UINT32|0x00000043\r | |
96 | ## If set, framebuffer memory will be reserved and mapped in the system RAM\r | |
97 | gArmPlatformTokenSpaceGuid.PcdArmLcdDdrFrameBufferBase|0x0|UINT64|0x00000044\r | |
98 | \r | |
b99f8126 GP |
99 | ## ARM Mali Display Processor DP500/DP550/DP650\r |
100 | gArmPlatformTokenSpaceGuid.PcdArmMaliDpBase|0x0|UINT64|0x00000050\r | |
101 | gArmPlatformTokenSpaceGuid.PcdArmMaliDpMemoryRegionLength|0x0|UINT32|0x00000051\r | |
102 | \r | |
11c20f4e | 103 | ## PL180 MCI\r |
104 | gArmPlatformTokenSpaceGuid.PcdPL180SysMciRegAddress|0x00000000|UINT32|0x00000028\r | |
105 | gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress|0x00000000|UINT32|0x00000029\r | |
106 | \r | |
fe787dfb GP |
107 | # Graphics Output Pixel format\r |
108 | # 0 : PixelRedGreenBlueReserved8BitPerColor\r | |
109 | # 1 : PixelBlueGreenRedReserved8BitPerColor\r | |
110 | # 2 : PixelBitMask\r | |
111 | # Default is set to UEFI console font format PixelBlueGreenRedReserved8BitPerColor\r | |
112 | gArmPlatformTokenSpaceGuid.PcdGopPixelFormat|0x00000001|UINT32|0x00000040\r | |
113 | \r | |
268aad67 GP |
114 | ## If set, this will swap settings for HDLCD RED_SELECT and BLUE_SELECT registers\r |
115 | gArmPlatformTokenSpaceGuid.PcdArmHdLcdSwapBlueRedSelect|FALSE|BOOLEAN|0x00000045\r | |
116 | \r | |
b4e2799b AB |
117 | [PcdsFixedAtBuild.common,PcdsDynamic.common]\r |
118 | ## PL031 RealTimeClock\r | |
119 | gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0|UINT32|0x00000024\r | |
120 | gArmPlatformTokenSpaceGuid.PcdPL031RtcPpmAccuracy|300000000|UINT32|0x00000022\r | |
121 | \r | |
08e94eee | 122 | gArmPlatformTokenSpaceGuid.PcdWatchdogCount|0x0|UINT32|0x00000033\r |