]>
Commit | Line | Data |
---|---|---|
1d5d0ae9 | 1 | /** @file\r |
2 | * Header defining RealView EB constants (Base addresses, sizes, flags)\r | |
3 | *\r | |
4 | * Copyright (c) 2011, ARM Limited. All rights reserved.\r | |
5 | * \r | |
6 | * This program and the accompanying materials \r | |
7 | * are licensed and made available under the terms and conditions of the BSD License \r | |
8 | * which accompanies this distribution. The full text of the license may be found at \r | |
9 | * http://opensource.org/licenses/bsd-license.php \r | |
10 | *\r | |
11 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
12 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
13 | *\r | |
14 | **/\r | |
15 | \r | |
16 | #ifndef __ARM_EB_H__\r | |
17 | #define __ARM_EB_H__\r | |
18 | \r | |
19 | /*******************************************\r | |
20 | // Platform Memory Map\r | |
21 | *******************************************/\r | |
22 | \r | |
23 | // Can be NOR, DOC, DRAM, SRAM\r | |
9bc6ef02 | 24 | #define ARM_EB_REMAP_BASE 0x00000000\r |
25 | #define ARM_EB_REMAP_SZ 0x04000000\r | |
1d5d0ae9 | 26 | \r |
27 | // Motherboard Peripheral and On-chip peripheral\r | |
9bc6ef02 | 28 | #define ARM_EB_SMB_MB_ON_CHIP_PERIPH_BASE 0x10000000\r |
6aaa8d7d | 29 | #define ARM_EB_SMB_MB_ON_CHIP_PERIPH_SZ 0x10000000\r |
9bc6ef02 | 30 | #define ARM_EB_BOARD_PERIPH_BASE 0x10000000\r |
31 | //#define ARM_EB_CHIP_PERIPH_BASE 0x10020000\r | |
1d5d0ae9 | 32 | \r |
33 | // SMC\r | |
9bc6ef02 | 34 | #define ARM_EB_SMC_BASE 0x40000000\r |
35 | #define ARM_EB_SMC_SZ 0x20000000\r | |
1d5d0ae9 | 36 | \r |
37 | // NOR Flash 1\r | |
9bc6ef02 | 38 | #define ARM_EB_SMB_NOR_BASE 0x40000000\r |
39 | #define ARM_EB_SMB_NOR_SZ 0x04000000 /* 64 MB */\r | |
1d5d0ae9 | 40 | // DOC Flash\r |
9bc6ef02 | 41 | #define ARM_EB_SMB_DOC_BASE 0x44000000\r |
42 | #define ARM_EB_SMB_DOC_SZ 0x04000000 /* 64 MB */\r | |
1d5d0ae9 | 43 | // SRAM\r |
9bc6ef02 | 44 | #define ARM_EB_SMB_SRAM_BASE 0x48000000\r |
45 | #define ARM_EB_SMB_SRAM_SZ 0x02000000 /* 32 MB */\r | |
1d5d0ae9 | 46 | // USB, Ethernet, VRAM\r |
9bc6ef02 | 47 | #define ARM_EB_SMB_PERIPH_BASE 0x4E000000\r |
48 | //#define ARM_EB_SMB_PERIPH_VRAM 0x4C000000\r | |
49 | #define ARM_EB_SMB_PERIPH_SZ 0x02000000 /* 32 MB */\r | |
1d5d0ae9 | 50 | \r |
1d5d0ae9 | 51 | // Logic Tile\r |
9bc6ef02 | 52 | #define ARM_EB_LOGIC_TILE_BASE 0xC0000000\r |
53 | #define ARM_EB_LOGIC_TILE_SZ 0x40000000\r | |
1d5d0ae9 | 54 | \r |
55 | /*******************************************\r | |
56 | // Motherboard peripherals\r | |
57 | *******************************************/\r | |
58 | \r | |
59 | // Define MotherBoard SYS flags offsets (from ARM_EB_BOARD_PERIPH_BASE)\r | |
f4ee7a82 | 60 | #define ARM_EB_SYS_ID_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00000)\r |
9bc6ef02 | 61 | #define ARM_EB_SYS_OSC4_REG (ARM_EB_BOARD_PERIPH_BASE + 0x0001C)\r |
62 | #define ARM_EB_SYS_LOCK_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00020)\r | |
63 | #define ARM_EB_SYS_100HZ_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00024)\r | |
64 | #define ARM_EB_SYS_FLAGS_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00030)\r | |
65 | #define ARM_EB_SYS_FLAGS_SET_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00030)\r | |
66 | #define ARM_EB_SYS_FLAGS_CLR_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00034)\r | |
67 | #define ARM_EB_SYS_FLAGS_NV_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00038)\r | |
68 | #define ARM_EB_SYS_FLAGS_NV_SET_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00038)\r | |
69 | #define ARM_EB_SYS_FLAGS_NV_CLR_REG (ARM_EB_BOARD_PERIPH_BASE + 0x0003C)\r | |
f4ee7a82 | 70 | #define ARM_EB_SYS_RESETCTL_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00040)\r |
9bc6ef02 | 71 | #define ARM_EB_SYS_CLCD_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00050)\r |
72 | #define ARM_EB_SYS_PROCID0_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00084)\r | |
73 | #define ARM_EB_SYS_PROCID1_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00088)\r | |
1d5d0ae9 | 74 | \r |
75 | // SP810 Controller\r | |
9bc6ef02 | 76 | #define SP810_CTRL_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x01000)\r |
1d5d0ae9 | 77 | \r |
78 | // SYSTRCL Register\r | |
9bc6ef02 | 79 | #define ARM_EB_SYSCTRL 0x10001000\r |
1d5d0ae9 | 80 | \r |
1d5d0ae9 | 81 | // Dynamic Memory Controller Base\r |
6aaa8d7d | 82 | #define ARM_EB_DMC_BASE 0x10018000\r |
1d5d0ae9 | 83 | \r |
84 | // Static Memory Controller Base\r | |
6aaa8d7d | 85 | #define ARM_EB_SMC_CTRL_BASE 0x10080000\r |
86 | \r | |
9bc6ef02 | 87 | //Note: Moving the framebuffer into the 0x70000000-0x80000000 region does not seem to work\r |
88 | #define PL111_CLCD_VRAM_BASE 0x00100000\r | |
1d5d0ae9 | 89 | \r |
90 | /*// System Configuration Controller register Base addresses\r | |
91 | //#define ARM_EB_SYS_CFG_CTRL_BASE 0x100E2000\r | |
92 | #define ARM_EB_SYS_CFGRW0_REG 0x100E2000\r | |
93 | #define ARM_EB_SYS_CFGRW1_REG 0x100E2004\r | |
94 | #define ARM_EB_SYS_CFGRW2_REG 0x100E2008\r | |
95 | \r | |
96 | #define ARM_EB_CFGRW1_REMAP_NOR0 0\r | |
97 | #define ARM_EB_CFGRW1_REMAP_NOR1 (1 << 28)\r | |
98 | #define ARM_EB_CFGRW1_REMAP_EXT_AXI (1 << 29)\r | |
99 | #define ARM_EB_CFGRW1_REMAP_DRAM (1 << 30)\r | |
100 | \r | |
101 | // PL301 Fast AXI Base Address\r | |
102 | #define ARM_EB_FAXI_BASE 0x100E9000\r | |
103 | \r | |
104 | // L2x0 Cache Controller Base Address\r | |
105 | //#define ARM_EB_L2x0_CTLR_BASE 0x1E00A000*/\r | |
106 | \r | |
2575b726 | 107 | #define ARM_EB_SYS_PROC_ID_MASK (UINT32)(0xFFU << 24)\r |
108 | #define ARM_EB_SYS_PROC_ID_CORTEX_A8 (UINT32)(0x0EU << 24)\r | |
109 | #define ARM_EB_SYS_PROC_ID_CORTEX_A9 (UINT32)(0x0CU << 24)\r | |
1d5d0ae9 | 110 | \r |
6aaa8d7d | 111 | /*******************************************\r |
112 | // System Configuration Control\r | |
113 | *******************************************/\r | |
114 | \r | |
115 | // Sites where the peripheral is fitted\r | |
116 | #define ARM_EB_UNSUPPORTED ~0\r | |
117 | \r | |
118 | #define VIRTUAL_SYS_CFG(site,func) (((site) << 24) | (func))\r | |
119 | \r | |
120 | #define SYS_CFG_RTC VIRTUAL_SYS_CFG(ARM_EB_UNSUPPORTED,1)\r | |
121 | \r | |
1d5d0ae9 | 122 | #endif \r |