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1d5d0ae9 | 1 | /** @file\r |
2 | * Header defining RealView EB constants (Base addresses, sizes, flags)\r | |
3 | *\r | |
4 | * Copyright (c) 2011, ARM Limited. All rights reserved.\r | |
5 | * \r | |
6 | * This program and the accompanying materials \r | |
7 | * are licensed and made available under the terms and conditions of the BSD License \r | |
8 | * which accompanies this distribution. The full text of the license may be found at \r | |
9 | * http://opensource.org/licenses/bsd-license.php \r | |
10 | *\r | |
11 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
12 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
13 | *\r | |
14 | **/\r | |
15 | \r | |
16 | #ifndef __ARM_EB_H__\r | |
17 | #define __ARM_EB_H__\r | |
18 | \r | |
19 | /*******************************************\r | |
20 | // Platform Memory Map\r | |
21 | *******************************************/\r | |
22 | \r | |
23 | // Can be NOR, DOC, DRAM, SRAM\r | |
9bc6ef02 | 24 | #define ARM_EB_REMAP_BASE 0x00000000\r |
25 | #define ARM_EB_REMAP_SZ 0x04000000\r | |
1d5d0ae9 | 26 | \r |
27 | // Motherboard Peripheral and On-chip peripheral\r | |
9bc6ef02 | 28 | #define ARM_EB_SMB_MB_ON_CHIP_PERIPH_BASE 0x10000000\r |
6aaa8d7d | 29 | #define ARM_EB_SMB_MB_ON_CHIP_PERIPH_SZ 0x10000000\r |
9bc6ef02 | 30 | #define ARM_EB_BOARD_PERIPH_BASE 0x10000000\r |
31 | //#define ARM_EB_CHIP_PERIPH_BASE 0x10020000\r | |
1d5d0ae9 | 32 | \r |
33 | // SMC\r | |
9bc6ef02 | 34 | #define ARM_EB_SMC_BASE 0x40000000\r |
35 | #define ARM_EB_SMC_SZ 0x20000000\r | |
1d5d0ae9 | 36 | \r |
37 | // NOR Flash 1\r | |
9bc6ef02 | 38 | #define ARM_EB_SMB_NOR_BASE 0x40000000\r |
39 | #define ARM_EB_SMB_NOR_SZ 0x04000000 /* 64 MB */\r | |
1d5d0ae9 | 40 | // DOC Flash\r |
9bc6ef02 | 41 | #define ARM_EB_SMB_DOC_BASE 0x44000000\r |
42 | #define ARM_EB_SMB_DOC_SZ 0x04000000 /* 64 MB */\r | |
1d5d0ae9 | 43 | // SRAM\r |
9bc6ef02 | 44 | #define ARM_EB_SMB_SRAM_BASE 0x48000000\r |
45 | #define ARM_EB_SMB_SRAM_SZ 0x02000000 /* 32 MB */\r | |
1d5d0ae9 | 46 | // USB, Ethernet, VRAM\r |
9bc6ef02 | 47 | #define ARM_EB_SMB_PERIPH_BASE 0x4E000000\r |
48 | //#define ARM_EB_SMB_PERIPH_VRAM 0x4C000000\r | |
49 | #define ARM_EB_SMB_PERIPH_SZ 0x02000000 /* 32 MB */\r | |
1d5d0ae9 | 50 | \r |
51 | // DRAM\r | |
9bc6ef02 | 52 | #define ARM_EB_DRAM_BASE 0x70000000\r |
53 | #define ARM_EB_DRAM_SZ 0x10000000\r | |
1d5d0ae9 | 54 | \r |
55 | // Logic Tile\r | |
9bc6ef02 | 56 | #define ARM_EB_LOGIC_TILE_BASE 0xC0000000\r |
57 | #define ARM_EB_LOGIC_TILE_SZ 0x40000000\r | |
1d5d0ae9 | 58 | \r |
59 | /*******************************************\r | |
60 | // Motherboard peripherals\r | |
61 | *******************************************/\r | |
62 | \r | |
63 | // Define MotherBoard SYS flags offsets (from ARM_EB_BOARD_PERIPH_BASE)\r | |
9bc6ef02 | 64 | #define ARM_EB_SYS_OSC4_REG (ARM_EB_BOARD_PERIPH_BASE + 0x0001C)\r |
65 | #define ARM_EB_SYS_LOCK_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00020)\r | |
66 | #define ARM_EB_SYS_100HZ_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00024)\r | |
67 | #define ARM_EB_SYS_FLAGS_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00030)\r | |
68 | #define ARM_EB_SYS_FLAGS_SET_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00030)\r | |
69 | #define ARM_EB_SYS_FLAGS_CLR_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00034)\r | |
70 | #define ARM_EB_SYS_FLAGS_NV_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00038)\r | |
71 | #define ARM_EB_SYS_FLAGS_NV_SET_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00038)\r | |
72 | #define ARM_EB_SYS_FLAGS_NV_CLR_REG (ARM_EB_BOARD_PERIPH_BASE + 0x0003C)\r | |
73 | #define ARM_EB_SYS_CLCD_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00050)\r | |
74 | #define ARM_EB_SYS_PROCID0_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00084)\r | |
75 | #define ARM_EB_SYS_PROCID1_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00088)\r | |
1d5d0ae9 | 76 | \r |
77 | // SP810 Controller\r | |
9bc6ef02 | 78 | #define SP810_CTRL_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x01000)\r |
1d5d0ae9 | 79 | \r |
80 | // SYSTRCL Register\r | |
9bc6ef02 | 81 | #define ARM_EB_SYSCTRL 0x10001000\r |
1d5d0ae9 | 82 | \r |
83 | // Uart0\r | |
9bc6ef02 | 84 | #define PL011_CONSOLE_UART_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x09000)\r |
1d5d0ae9 | 85 | \r |
86 | // SP804 Timer Bases\r | |
9bc6ef02 | 87 | #define SP804_TIMER0_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x11000)\r |
88 | #define SP804_TIMER1_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x11020)\r | |
89 | #define SP804_TIMER2_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x12000)\r | |
90 | #define SP804_TIMER3_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x12020)\r | |
1d5d0ae9 | 91 | \r |
0f4386e7 | 92 | // PL301 RTC\r |
93 | #define PL031_RTC_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x17000)\r | |
94 | \r | |
1d5d0ae9 | 95 | // Dynamic Memory Controller Base\r |
6aaa8d7d | 96 | #define ARM_EB_DMC_BASE 0x10018000\r |
1d5d0ae9 | 97 | \r |
98 | // Static Memory Controller Base\r | |
6aaa8d7d | 99 | #define ARM_EB_SMC_CTRL_BASE 0x10080000\r |
100 | \r | |
9bc6ef02 | 101 | #define PL111_CLCD_BASE 0x10020000\r |
102 | //Note: Moving the framebuffer into the 0x70000000-0x80000000 region does not seem to work\r | |
103 | #define PL111_CLCD_VRAM_BASE 0x00100000\r | |
1d5d0ae9 | 104 | \r |
105 | /*// System Configuration Controller register Base addresses\r | |
106 | //#define ARM_EB_SYS_CFG_CTRL_BASE 0x100E2000\r | |
107 | #define ARM_EB_SYS_CFGRW0_REG 0x100E2000\r | |
108 | #define ARM_EB_SYS_CFGRW1_REG 0x100E2004\r | |
109 | #define ARM_EB_SYS_CFGRW2_REG 0x100E2008\r | |
110 | \r | |
111 | #define ARM_EB_CFGRW1_REMAP_NOR0 0\r | |
112 | #define ARM_EB_CFGRW1_REMAP_NOR1 (1 << 28)\r | |
113 | #define ARM_EB_CFGRW1_REMAP_EXT_AXI (1 << 29)\r | |
114 | #define ARM_EB_CFGRW1_REMAP_DRAM (1 << 30)\r | |
115 | \r | |
116 | // PL301 Fast AXI Base Address\r | |
117 | #define ARM_EB_FAXI_BASE 0x100E9000\r | |
118 | \r | |
119 | // L2x0 Cache Controller Base Address\r | |
120 | //#define ARM_EB_L2x0_CTLR_BASE 0x1E00A000*/\r | |
121 | \r | |
122 | \r | |
0f4386e7 | 123 | // PL031 RTC - Other settings\r |
124 | #define PL031_PPM_ACCURACY 300000000\r | |
125 | \r | |
126 | \r | |
1d5d0ae9 | 127 | /*******************************************\r |
128 | // EFI Memory Map in Permanent Memory (DRAM)\r | |
129 | *******************************************/\r | |
130 | \r | |
131 | // This region is allocated at the bottom of the DRAM. It will be used\r | |
132 | // for fixed address allocations such as Vector Table\r | |
133 | #define ARM_EB_EFI_FIX_ADDRESS_REGION_SZ SIZE_8MB\r | |
134 | \r | |
135 | // This region is the memory declared to PEI as permanent memory for PEI\r | |
136 | // and DXE. EFI stacks and heaps will be declared in this region.\r | |
137 | #define ARM_EB_EFI_MEMORY_REGION_SZ 0x1000000\r | |
138 | \r | |
6aaa8d7d | 139 | /*******************************************\r |
140 | // System Configuration Control\r | |
141 | *******************************************/\r | |
142 | \r | |
143 | // Sites where the peripheral is fitted\r | |
144 | #define ARM_EB_UNSUPPORTED ~0\r | |
145 | \r | |
146 | #define VIRTUAL_SYS_CFG(site,func) (((site) << 24) | (func))\r | |
147 | \r | |
148 | #define SYS_CFG_RTC VIRTUAL_SYS_CFG(ARM_EB_UNSUPPORTED,1)\r | |
149 | \r | |
1d5d0ae9 | 150 | #endif \r |