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1d5d0ae9 | 1 | /** @file\r |
2 | *\r | |
3 | * Copyright (c) 2011, ARM Limited. All rights reserved.\r | |
4 | * \r | |
5 | * This program and the accompanying materials \r | |
6 | * are licensed and made available under the terms and conditions of the BSD License \r | |
7 | * which accompanies this distribution. The full text of the license may be found at \r | |
8 | * http://opensource.org/licenses/bsd-license.php \r | |
9 | *\r | |
10 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
11 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
12 | *\r | |
13 | **/\r | |
14 | \r | |
15 | #include <Library/ArmPlatformLib.h>\r | |
16 | #include <Library/DebugLib.h>\r | |
17 | #include <Library/PcdLib.h>\r | |
18 | #include <Library/MemoryAllocationLib.h>\r | |
6377d2f1 | 19 | #include <Library/IoLib.h>\r |
1d5d0ae9 | 20 | \r |
5cc45b70 | 21 | #include <ArmPlatform.h>\r |
22 | \r | |
f598bf12 | 23 | #define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 6\r |
24 | \r | |
1d5d0ae9 | 25 | // DDR attributes\r |
26 | #define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK\r | |
27 | #define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED\r | |
1d5d0ae9 | 28 | \r |
1d5d0ae9 | 29 | /**\r |
30 | Return the Virtual Memory Map of your platform\r | |
31 | \r | |
32 | This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.\r | |
33 | \r | |
34 | @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-\r | |
35 | Virtual Memory mapping. This array must be ended by a zero-filled\r | |
36 | entry\r | |
37 | \r | |
38 | **/\r | |
f598bf12 | 39 | VOID\r |
40 | ArmPlatformGetVirtualMemoryMap (\r | |
41 | IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap\r | |
42 | )\r | |
43 | {\r | |
44 | UINT32 CacheAttributes;\r | |
f598bf12 | 45 | UINTN Index = 0;\r |
46 | ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;\r | |
47 | \r | |
48 | ASSERT(VirtualMemoryMap != NULL);\r | |
49 | \r | |
12c5ae23 | 50 | VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages (EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));\r |
f598bf12 | 51 | if (VirtualMemoryTable == NULL) {\r |
52 | return;\r | |
53 | }\r | |
54 | \r | |
55 | if (FeaturePcdGet(PcdCacheEnable) == TRUE) {\r | |
12c5ae23 | 56 | CacheAttributes = DDR_ATTRIBUTES_CACHED;\r |
f598bf12 | 57 | } else {\r |
12c5ae23 | 58 | CacheAttributes = DDR_ATTRIBUTES_UNCACHED;\r |
f598bf12 | 59 | }\r |
60 | \r | |
61 | // ReMap (Either NOR Flash or DRAM)\r | |
62 | VirtualMemoryTable[Index].PhysicalBase = ARM_EB_REMAP_BASE;\r | |
63 | VirtualMemoryTable[Index].VirtualBase = ARM_EB_REMAP_BASE;\r | |
64 | VirtualMemoryTable[Index].Length = ARM_EB_REMAP_SZ;\r | |
65 | VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;\r | |
66 | \r | |
67 | // DDR\r | |
c357fd6a OM |
68 | VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdSystemMemoryBase);\r |
69 | VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdSystemMemoryBase);\r | |
70 | VirtualMemoryTable[Index].Length = PcdGet64 (PcdSystemMemorySize);\r | |
f598bf12 | 71 | VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;\r |
72 | \r | |
73 | // SMC CS7\r | |
74 | VirtualMemoryTable[++Index].PhysicalBase = ARM_EB_SMB_MB_ON_CHIP_PERIPH_BASE;\r | |
75 | VirtualMemoryTable[Index].VirtualBase = ARM_EB_SMB_MB_ON_CHIP_PERIPH_BASE;\r | |
76 | VirtualMemoryTable[Index].Length = ARM_EB_SMB_MB_ON_CHIP_PERIPH_SZ;\r | |
7fffeef9 | 77 | VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r |
f598bf12 | 78 | \r |
79 | // SMB CS0-CS1 - NOR Flash 1 & 2\r | |
80 | VirtualMemoryTable[++Index].PhysicalBase = ARM_EB_SMB_NOR_BASE;\r | |
81 | VirtualMemoryTable[Index].VirtualBase = ARM_EB_SMB_NOR_BASE;\r | |
82 | VirtualMemoryTable[Index].Length = ARM_EB_SMB_NOR_SZ + ARM_EB_SMB_DOC_SZ;\r | |
7fffeef9 | 83 | VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r |
f598bf12 | 84 | \r |
85 | // SMB CS2 - SRAM\r | |
86 | VirtualMemoryTable[++Index].PhysicalBase = ARM_EB_SMB_SRAM_BASE;\r | |
87 | VirtualMemoryTable[Index].VirtualBase = ARM_EB_SMB_SRAM_BASE;\r | |
88 | VirtualMemoryTable[Index].Length = ARM_EB_SMB_SRAM_SZ;\r | |
89 | VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;\r | |
90 | \r | |
91 | // SMB CS3-CS6 - Motherboard Peripherals\r | |
92 | VirtualMemoryTable[++Index].PhysicalBase = ARM_EB_SMB_PERIPH_BASE;\r | |
93 | VirtualMemoryTable[Index].VirtualBase = ARM_EB_SMB_PERIPH_BASE;\r | |
94 | VirtualMemoryTable[Index].Length = ARM_EB_SMB_PERIPH_SZ;\r | |
7fffeef9 | 95 | VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r |
f598bf12 | 96 | \r |
97 | // If a Logic Tile is connected to The ARM Versatile Express Motherboard\r | |
98 | if (MmioRead32(ARM_EB_SYS_PROCID1_REG) != 0) {\r | |
99 | VirtualMemoryTable[++Index].PhysicalBase = ARM_EB_LOGIC_TILE_BASE;\r | |
100 | VirtualMemoryTable[Index].VirtualBase = ARM_EB_LOGIC_TILE_BASE;\r | |
101 | VirtualMemoryTable[Index].Length = ARM_EB_LOGIC_TILE_SZ;\r | |
7fffeef9 | 102 | VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r |
f598bf12 | 103 | \r |
104 | ASSERT((Index + 1) == (MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS + 1));\r | |
105 | } else {\r | |
106 | ASSERT((Index + 1) == MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);\r | |
107 | }\r | |
108 | \r | |
109 | // End of Table\r | |
110 | VirtualMemoryTable[++Index].PhysicalBase = 0;\r | |
111 | VirtualMemoryTable[Index].VirtualBase = 0;\r | |
112 | VirtualMemoryTable[Index].Length = 0;\r | |
113 | VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;\r | |
114 | \r | |
115 | *VirtualMemoryMap = VirtualMemoryTable;\r | |
1d5d0ae9 | 116 | }\r |