[mirror_edk2.git] / ArmPlatformPkg / ArmVExpressPkg / ArmVExpress-RTSM-A15_MPCore.fdf

# FLASH layout file for ARM VE.\r
#\r
#  Copyright (c) 2011, ARM Limited. All rights reserved.\r
#  \r
#  This program and the accompanying materials                          \r
#  are licensed and made available under the terms and conditions of the BSD License         \r
#  which accompanies this distribution.  The full text of the license may be found at        \r
#  http://opensource.org/licenses/bsd-license.php                                            \r
#\r
#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
#\r
\r
################################################################################\r
#\r
# FD Section\r
# The [FD] Section is made up of the definition statements and a\r
# description of what goes into  the Flash Device Image.  Each FD section\r
# defines one flash "device" image.  A flash device image may be one of\r
# the following: Removable media bootable image (like a boot floppy\r
# image,) an Option ROM image (that would be "flashed" into an add-in\r
# card,) a System "Flash"  image (that would be burned into a system's\r
# flash) or an Update ("Capsule") image that will be used to update and\r
# existing system flash.\r
#\r
################################################################################\r
\r
[FD.RTSM_VE_Cortex-A15_MPCore_EFI]\r
BaseAddress   = 0x08000000|gArmTokenSpaceGuid.PcdFdBaseAddress  # The base address of the Firmware in NOR Flash.\r
Size          = 0x00300000|gArmTokenSpaceGuid.PcdFdSize         # The size in bytes of the FLASH Device\r
ErasePolarity = 1\r
\r
# This one is tricky, it must be: BlockSize * NumBlocks = Size\r
BlockSize     = 0x00001000\r
NumBlocks     = 0x300\r
\r
################################################################################\r
#\r
# Following are lists of FD Region layout which correspond to the locations of different\r
# images within the flash device.\r
#\r
# Regions must be defined in ascending order and may not overlap.\r
#\r
# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by\r
# the pipe "|" character, followed by the size of the region, also in hex with the leading\r
# "0x" characters. Like:\r
# Offset|Size\r
# PcdOffsetCName|PcdSizeCName\r
# RegionType <FV, DATA, or FILE>\r
#\r
################################################################################\r
\r
0x00000000|0x00080000\r
gArmTokenSpaceGuid.PcdSecureFvBaseAddress|gArmTokenSpaceGuid.PcdSecureFvSize\r
FV = FVMAIN_SEC\r
\r
0x00080000|0x00280000\r
gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize\r
FV = FVMAIN_COMPACT\r
\r
\r
################################################################################\r
#\r
# FV Section\r
#\r
# [FV] section is used to define what components or modules are placed within a flash\r
# device file.  This section also defines order the components and modules are positioned\r
# within the image.  The [FV] section consists of define statements, set statements and\r
# module statements.\r
#\r
################################################################################\r
\r
[FV.FVMAIN_SEC]\r
FvAlignment        = 8\r
ERASE_POLARITY     = 1\r
MEMORY_MAPPED      = TRUE\r
STICKY_WRITE       = TRUE\r
LOCK_CAP           = TRUE\r
LOCK_STATUS        = TRUE\r
WRITE_DISABLED_CAP = TRUE\r
WRITE_ENABLED_CAP  = TRUE\r
WRITE_STATUS       = TRUE\r
WRITE_LOCK_CAP     = TRUE\r
WRITE_LOCK_STATUS  = TRUE\r
READ_DISABLED_CAP  = TRUE\r
READ_ENABLED_CAP   = TRUE\r
READ_STATUS        = TRUE\r
READ_LOCK_CAP      = TRUE\r
READ_LOCK_STATUS   = TRUE\r
\r
  INF ArmPlatformPkg/Sec/Sec.inf\r
\r
\r
[FV.FvMain]\r
BlockSize          = 0x40\r
NumBlocks          = 0         # This FV gets compressed so make it just big enough\r
FvAlignment        = 8         # FV alignment and FV attributes setting.\r
ERASE_POLARITY     = 1\r
MEMORY_MAPPED      = TRUE\r
STICKY_WRITE       = TRUE\r
LOCK_CAP           = TRUE\r
LOCK_STATUS        = TRUE\r
WRITE_DISABLED_CAP = TRUE\r
WRITE_ENABLED_CAP  = TRUE\r
WRITE_STATUS       = TRUE\r
WRITE_LOCK_CAP     = TRUE\r
WRITE_LOCK_STATUS  = TRUE\r
READ_DISABLED_CAP  = TRUE\r
READ_ENABLED_CAP   = TRUE\r
READ_STATUS        = TRUE\r
READ_LOCK_CAP      = TRUE\r
READ_LOCK_STATUS   = TRUE\r
\r
  INF MdeModulePkg/Core/Dxe/DxeMain.inf \r
\r
  #\r
  # PI DXE Drivers producing Architectural Protocols (EFI Services) \r
  #\r
  INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf\r
  INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf\r
  INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf\r
  INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf\r
  INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf\r
  INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf\r
  INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf\r
  INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf\r
  INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf\r
  INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf\r
\r
  INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf\r
  \r
  #\r
  # Multiple Console IO support\r
  #\r
  INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf\r
  INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf\r
  INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf\r
  INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf\r
  INF EmbeddedPkg/SerialDxe/SerialDxe.inf\r
\r
  INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf\r
  INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf\r
  INF ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf\r
  INF ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf\r
  INF ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf\r
\r
  #\r
  # Semi-hosting filesystem\r
  #\r
  INF ArmPkg/Filesystem/SemihostFs/SemihostFs.inf\r
  \r
  #\r
  # FAT filesystem + GPT/MBR partitioning\r
  #\r
  INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf\r
  INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf\r
  INF FatBinPkg/EnhancedFatDxe/Fat.inf\r
  INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf\r
\r
  #\r
  # Multimedia Card Interface\r
  #\r
  INF EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf\r
  INF ArmPlatformPkg/Drivers/PL180MciDxe/PL180MciDxe.inf\r
\r
  #\r
  # Platform  Driver
  #
  INF ArmPlatformPkg/ArmVExpressPkg/ArmFvpDxe/ArmFvpDxe.inf
  INF OvmfPkg/VirtioBlkDxe/VirtioBlk.inf

  #
  # UEFI application (Shell Embedded Boot Loader) \r
  #  \r
  INF ShellBinPkg/UefiShell/UefiShell.inf \r
  \r
  #\r
  # Bds\r
  #\r
  INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf\r
  INF ArmPlatformPkg/Bds/Bds.inf\r
\r
\r
[FV.FVMAIN_COMPACT]\r
FvAlignment        = 8\r
ERASE_POLARITY     = 1\r
MEMORY_MAPPED      = TRUE\r
STICKY_WRITE       = TRUE\r
LOCK_CAP           = TRUE\r
LOCK_STATUS        = TRUE\r
WRITE_DISABLED_CAP = TRUE\r
WRITE_ENABLED_CAP  = TRUE\r
WRITE_STATUS       = TRUE\r
WRITE_LOCK_CAP     = TRUE\r
WRITE_LOCK_STATUS  = TRUE\r
READ_DISABLED_CAP  = TRUE\r
READ_ENABLED_CAP   = TRUE\r
READ_STATUS        = TRUE\r
READ_LOCK_CAP      = TRUE\r
READ_LOCK_STATUS   = TRUE\r
\r
!if $(EDK2_SKIP_PEICORE) == 1\r
  INF ArmPlatformPkg/PrePi/PeiMPCore.inf\r
!else\r
  INF ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf\r
  INF MdeModulePkg/Core/Pei/PeiMain.inf\r
  INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf\r
  INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf\r
  INF ArmPkg/Drivers/CpuPei/CpuPei.inf\r
  INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf\r
  INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf\r
  INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf\r
  INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf\r
!endif\r
  \r
  FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {\r
    SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {\r
      SECTION FV_IMAGE = FVMAIN\r
    }\r
  }\r
\r
\r
################################################################################\r
#\r
# Rules are use with the [FV] section's module INF type to define\r
# how an FFS file is created for a given INF file. The following Rule are the default\r
# rules for the different module type. User can add the customized rules to define the\r
# content of the FFS file.\r
#\r
################################################################################\r
\r
\r
############################################################################\r
# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section   # \r
############################################################################\r
#\r
#[Rule.Common.DXE_DRIVER]\r
#  FILE DRIVER = $(NAMED_GUID) {\r
#    DXE_DEPEX    DXE_DEPEX               Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
#    COMPRESS PI_STD {\r
#      GUIDED {\r
#        PE32     PE32                    $(INF_OUTPUT)/$(MODULE_NAME).efi\r
#        UI       STRING="$(MODULE_NAME)" Optional\r
#        VERSION  STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
#      }\r
#    }\r
#  }\r
#\r
############################################################################\r
\r
[Rule.Common.SEC]\r
  FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {\r
    TE  TE    Align = 32                $(INF_OUTPUT)/$(MODULE_NAME).efi\r
  }\r
\r
[Rule.Common.PEI_CORE]\r
  FILE PEI_CORE = $(NAMED_GUID) {\r
    TE     TE                           $(INF_OUTPUT)/$(MODULE_NAME).efi\r
    UI     STRING ="$(MODULE_NAME)" Optional         \r
  }\r
\r
[Rule.Common.PEIM]\r
  FILE PEIM = $(NAMED_GUID) {\r
     PEI_DEPEX PEI_DEPEX Optional       $(INF_OUTPUT)/$(MODULE_NAME).depex\r
     TE       TE                        $(INF_OUTPUT)/$(MODULE_NAME).efi\r
     UI       STRING="$(MODULE_NAME)" Optional         \r
  }\r
\r
[Rule.Common.PEIM.TIANOCOMPRESSED]\r
  FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {\r
    PEI_DEPEX PEI_DEPEX Optional        $(INF_OUTPUT)/$(MODULE_NAME).depex\r
    GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {\r
      PE32      PE32                    $(INF_OUTPUT)/$(MODULE_NAME).efi\r
      UI        STRING="$(MODULE_NAME)" Optional\r
    }\r
  }\r
\r
[Rule.Common.DXE_CORE]\r
  FILE DXE_CORE = $(NAMED_GUID) {\r
    PE32     PE32                       $(INF_OUTPUT)/$(MODULE_NAME).efi\r
    UI       STRING="$(MODULE_NAME)" Optional\r
  }\r
\r
[Rule.Common.UEFI_DRIVER]\r
  FILE DRIVER = $(NAMED_GUID) {\r
    DXE_DEPEX    DXE_DEPEX              Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
    PE32         PE32                   $(INF_OUTPUT)/$(MODULE_NAME).efi\r
    UI           STRING="$(MODULE_NAME)" Optional\r
  }\r
\r
[Rule.Common.DXE_DRIVER]\r
  FILE DRIVER = $(NAMED_GUID) {\r
    DXE_DEPEX    DXE_DEPEX              Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
    PE32         PE32                   $(INF_OUTPUT)/$(MODULE_NAME).efi\r
    UI           STRING="$(MODULE_NAME)" Optional\r
  }\r
\r
[Rule.Common.DXE_RUNTIME_DRIVER]\r
  FILE DRIVER = $(NAMED_GUID) {\r
    DXE_DEPEX    DXE_DEPEX              Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
    PE32         PE32                   $(INF_OUTPUT)/$(MODULE_NAME).efi\r
    UI           STRING="$(MODULE_NAME)" Optional\r
  }\r
\r
[Rule.Common.UEFI_APPLICATION]\r
  FILE APPLICATION = $(NAMED_GUID) {\r
    UI     STRING ="$(MODULE_NAME)" Optional         \r
    PE32   PE32                         $(INF_OUTPUT)/$(MODULE_NAME).efi\r
  }\r
\r
[Rule.Common.UEFI_DRIVER.BINARY]\r
  FILE DRIVER = $(NAMED_GUID) {\r
    DXE_DEPEX DXE_DEPEX Optional      |.depex\r
    PE32      PE32                    |.efi\r
    UI        STRING="$(MODULE_NAME)" Optional\r
    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
  }\r
\r
[Rule.Common.UEFI_APPLICATION.BINARY]\r
  FILE APPLICATION = $(NAMED_GUID) {\r
    PE32      PE32                    |.efi\r
    UI        STRING="$(MODULE_NAME)" Optional\r
    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
  }\r
Commit	Line	Data
1e57a462	1	# FLASH layout file for ARM VE.\r
	2	#\r
	3	# Copyright (c) 2011, ARM Limited. All rights reserved.\r
	4	# \r
	5	# This program and the accompanying materials \r
	6	# are licensed and made available under the terms and conditions of the BSD License \r
	7	# which accompanies this distribution. The full text of the license may be found at \r
	8	# http://opensource.org/licenses/bsd-license.php \r
	9	#\r
	10	# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
	11	# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
	12	#\r
	13	\r
	14	################################################################################\r
	15	#\r
	16	# FD Section\r
	17	# The [FD] Section is made up of the definition statements and a\r
	18	# description of what goes into the Flash Device Image. Each FD section\r
	19	# defines one flash "device" image. A flash device image may be one of\r
	20	# the following: Removable media bootable image (like a boot floppy\r
	21	# image,) an Option ROM image (that would be "flashed" into an add-in\r
	22	# card,) a System "Flash" image (that would be burned into a system's\r
	23	# flash) or an Update ("Capsule") image that will be used to update and\r
	24	# existing system flash.\r
	25	#\r
	26	################################################################################\r
	27	\r
	28	[FD.RTSM_VE_Cortex-A15_MPCore_EFI]\r
	29	BaseAddress = 0x08000000\|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash.\r
9e2e89f0	30	Size = 0x00300000\|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device\r
1e57a462	31	ErasePolarity = 1\r
	32	\r
	33	# This one is tricky, it must be: BlockSize * NumBlocks = Size\r
	34	BlockSize = 0x00001000\r
9e2e89f0	35	NumBlocks = 0x300\r
1e57a462	36	\r
	37	################################################################################\r
	38	#\r
	39	# Following are lists of FD Region layout which correspond to the locations of different\r
	40	# images within the flash device.\r
	41	#\r
	42	# Regions must be defined in ascending order and may not overlap.\r
	43	#\r
	44	# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by\r
	45	# the pipe "\|" character, followed by the size of the region, also in hex with the leading\r
	46	# "0x" characters. Like:\r
	47	# Offset\|Size\r
	48	# PcdOffsetCName\|PcdSizeCName\r
	49	# RegionType <FV, DATA, or FILE>\r
	50	#\r
	51	################################################################################\r
	52	\r
	53	0x00000000\|0x00080000\r
	54	gArmTokenSpaceGuid.PcdSecureFvBaseAddress\|gArmTokenSpaceGuid.PcdSecureFvSize\r
	55	FV = FVMAIN_SEC\r
	56	\r
	57	0x00080000\|0x00280000\r
	58	gArmTokenSpaceGuid.PcdFvBaseAddress\|gArmTokenSpaceGuid.PcdFvSize\r
	59	FV = FVMAIN_COMPACT\r
	60	\r
	61	\r
	62	################################################################################\r
	63	#\r
	64	# FV Section\r
	65	#\r
	66	# [FV] section is used to define what components or modules are placed within a flash\r
	67	# device file. This section also defines order the components and modules are positioned\r
	68	# within the image. The [FV] section consists of define statements, set statements and\r
	69	# module statements.\r
	70	#\r
	71	################################################################################\r
	72	\r
	73	[FV.FVMAIN_SEC]\r
	74	FvAlignment = 8\r
	75	ERASE_POLARITY = 1\r
	76	MEMORY_MAPPED = TRUE\r
	77	STICKY_WRITE = TRUE\r
	78	LOCK_CAP = TRUE\r
	79	LOCK_STATUS = TRUE\r
	80	WRITE_DISABLED_CAP = TRUE\r
	81	WRITE_ENABLED_CAP = TRUE\r
	82	WRITE_STATUS = TRUE\r
	83	WRITE_LOCK_CAP = TRUE\r
	84	WRITE_LOCK_STATUS = TRUE\r
	85	READ_DISABLED_CAP = TRUE\r
	86	READ_ENABLED_CAP = TRUE\r
	87	READ_STATUS = TRUE\r
	88	READ_LOCK_CAP = TRUE\r
	89	READ_LOCK_STATUS = TRUE\r
	90	\r
	91	INF ArmPlatformPkg/Sec/Sec.inf\r
	92	\r
	93	\r
	94	[FV.FvMain]\r
	95	BlockSize = 0x40\r
	96	NumBlocks = 0 # This FV gets compressed so make it just big enough\r
	97	FvAlignment = 8 # FV alignment and FV attributes setting.\r
	98	ERASE_POLARITY = 1\r
	99	MEMORY_MAPPED = TRUE\r
100	STICKY_WRITE = TRUE\r
101	LOCK_CAP = TRUE\r
102	LOCK_STATUS = TRUE\r
103	WRITE_DISABLED_CAP = TRUE\r
104	WRITE_ENABLED_CAP = TRUE\r
105	WRITE_STATUS = TRUE\r
106	WRITE_LOCK_CAP = TRUE\r
107	WRITE_LOCK_STATUS = TRUE\r
108	READ_DISABLED_CAP = TRUE\r
109	READ_ENABLED_CAP = TRUE\r
110	READ_STATUS = TRUE\r
111	READ_LOCK_CAP = TRUE\r
112	READ_LOCK_STATUS = TRUE\r
113	\r
114	INF MdeModulePkg/Core/Dxe/DxeMain.inf \r
115	\r
116	#\r
117	# PI DXE Drivers producing Architectural Protocols (EFI Services) \r
118	#\r
119	INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf\r
120	INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf\r
121	INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf\r
122	INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf\r
123	INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf\r
124	INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf\r
125	INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf\r
126	INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf\r
127	INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf\r
128	INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf\r
129	\r
130	INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf\r
131	\r
132	#\r
133	# Multiple Console IO support\r
134	#\r
135	INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf\r
136	INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf\r
137	INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf\r
138	INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf\r
139	INF EmbeddedPkg/SerialDxe/SerialDxe.inf\r
140	\r
017baa1c	141	INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf\r
1e57a462	142	INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf\r
	143	INF ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf\r
	144	INF ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf\r
	145	INF ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf\r
	146	\r
	147	#\r
	148	# Semi-hosting filesystem\r
	149	#\r
	150	INF ArmPkg/Filesystem/SemihostFs/SemihostFs.inf\r
	151	\r
	152	#\r
	153	# FAT filesystem + GPT/MBR partitioning\r
	154	#\r
	155	INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf\r
	156	INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf\r
	157	INF FatBinPkg/EnhancedFatDxe/Fat.inf\r
	158	INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf\r
	159	\r
	160	#\r
	161	# Multimedia Card Interface\r
	162	#\r
	163	INF EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf\r
	164	INF ArmPlatformPkg/Drivers/PL180MciDxe/PL180MciDxe.inf\r
	165	\r
	166	#\r
4b128e5d RH	167	# Platform Driver
	168	#
	169	INF ArmPlatformPkg/ArmVExpressPkg/ArmFvpDxe/ArmFvpDxe.inf
	170	INF OvmfPkg/VirtioBlkDxe/VirtioBlk.inf
	171
	172	#
1e57a462	173	# UEFI application (Shell Embedded Boot Loader) \r
	174	# \r
	175	INF ShellBinPkg/UefiShell/UefiShell.inf \r
	176	\r
	177	#\r
	178	# Bds\r
	179	#\r
	180	INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf\r
	181	INF ArmPlatformPkg/Bds/Bds.inf\r
	182	\r
	183	\r
	184	[FV.FVMAIN_COMPACT]\r
	185	FvAlignment = 8\r
	186	ERASE_POLARITY = 1\r
	187	MEMORY_MAPPED = TRUE\r
	188	STICKY_WRITE = TRUE\r
	189	LOCK_CAP = TRUE\r
	190	LOCK_STATUS = TRUE\r
	191	WRITE_DISABLED_CAP = TRUE\r
	192	WRITE_ENABLED_CAP = TRUE\r
	193	WRITE_STATUS = TRUE\r
	194	WRITE_LOCK_CAP = TRUE\r
	195	WRITE_LOCK_STATUS = TRUE\r
	196	READ_DISABLED_CAP = TRUE\r
	197	READ_ENABLED_CAP = TRUE\r
	198	READ_STATUS = TRUE\r
	199	READ_LOCK_CAP = TRUE\r
	200	READ_LOCK_STATUS = TRUE\r
	201	\r
	202	!if $(EDK2_SKIP_PEICORE) == 1\r
	203	INF ArmPlatformPkg/PrePi/PeiMPCore.inf\r
	204	!else\r
	205	INF ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf\r
	206	INF MdeModulePkg/Core/Pei/PeiMain.inf\r
	207	INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf\r
	208	INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf\r
	209	INF ArmPkg/Drivers/CpuPei/CpuPei.inf\r
	210	INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf\r
	211	INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf\r
	212	INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf\r
	213	INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf\r
	214	!endif\r
	215	\r
	216	FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {\r
	217	SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {\r
	218	SECTION FV_IMAGE = FVMAIN\r
	219	}\r
	220	}\r
	221	\r
	222	\r
	223	################################################################################\r
	224	#\r
	225	# Rules are use with the [FV] section's module INF type to define\r
	226	# how an FFS file is created for a given INF file. The following Rule are the default\r
	227	# rules for the different module type. User can add the customized rules to define the\r
	228	# content of the FFS file.\r
	229	#\r
	230	################################################################################\r
	231	\r
	232	\r
	233	############################################################################\r
	234	# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section # \r
	235	############################################################################\r
	236	#\r
237	#[Rule.Common.DXE_DRIVER]\r
238	# FILE DRIVER = $(NAMED_GUID) {\r
239	# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
240	# COMPRESS PI_STD {\r
241	# GUIDED {\r
242	# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
243	# UI STRING="$(MODULE_NAME)" Optional\r
244	# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
245	# }\r
246	# }\r
247	# }\r
248	#\r
249	############################################################################\r
250	\r
251	[Rule.Common.SEC]\r
252	FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {\r
253	TE TE Align = 32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
254	}\r
255	\r
256	[Rule.Common.PEI_CORE]\r
257	FILE PEI_CORE = $(NAMED_GUID) {\r
258	TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi\r
259	UI STRING ="$(MODULE_NAME)" Optional \r
260	}\r
261	\r
262	[Rule.Common.PEIM]\r
263	FILE PEIM = $(NAMED_GUID) {\r
264	PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
265	TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi\r
266	UI STRING="$(MODULE_NAME)" Optional \r
267	}\r
268	\r
269	[Rule.Common.PEIM.TIANOCOMPRESSED]\r
270	FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {\r
271	PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
272	GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {\r
273	PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
274	UI STRING="$(MODULE_NAME)" Optional\r
275	}\r
276	}\r
277	\r
278	[Rule.Common.DXE_CORE]\r
279	FILE DXE_CORE = $(NAMED_GUID) {\r
280	PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
281	UI STRING="$(MODULE_NAME)" Optional\r
282	}\r
283	\r
284	[Rule.Common.UEFI_DRIVER]\r
285	FILE DRIVER = $(NAMED_GUID) {\r
286	DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
287	PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
288	UI STRING="$(MODULE_NAME)" Optional\r
289	}\r
290	\r
291	[Rule.Common.DXE_DRIVER]\r
292	FILE DRIVER = $(NAMED_GUID) {\r
293	DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
294	PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
295	UI STRING="$(MODULE_NAME)" Optional\r
296	}\r
297	\r
298	[Rule.Common.DXE_RUNTIME_DRIVER]\r
299	FILE DRIVER = $(NAMED_GUID) {\r
300	DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
301	PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
302	UI STRING="$(MODULE_NAME)" Optional\r
303	}\r
304	\r
305	[Rule.Common.UEFI_APPLICATION]\r
306	FILE APPLICATION = $(NAMED_GUID) {\r
307	UI STRING ="$(MODULE_NAME)" Optional \r
308	PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
309	}\r
310	\r
311	[Rule.Common.UEFI_DRIVER.BINARY]\r
312	FILE DRIVER = $(NAMED_GUID) {\r
313	DXE_DEPEX DXE_DEPEX Optional \|.depex\r
314	PE32 PE32 \|.efi\r
315	UI STRING="$(MODULE_NAME)" Optional\r
316	VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
317	}\r
318	\r
319	[Rule.Common.UEFI_APPLICATION.BINARY]\r
320	FILE APPLICATION = $(NAMED_GUID) {\r
321	PE32 PE32 \|.efi\r
322	UI STRING="$(MODULE_NAME)" Optional\r
323	VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
324	}\r