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295c2eb8 | 1 | /** @file\r |
2 | * Header defining Versatile Express constants (Base addresses, sizes, flags)\r | |
3 | *\r | |
4 | * Copyright (c) 2012, ARM Limited. All rights reserved.\r | |
5 | *\r | |
6 | * This program and the accompanying materials\r | |
7 | * are licensed and made available under the terms and conditions of the BSD License\r | |
8 | * which accompanies this distribution. The full text of the license may be found at\r | |
9 | * http://opensource.org/licenses/bsd-license.php\r | |
10 | *\r | |
11 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | *\r | |
14 | **/\r | |
15 | \r | |
16 | #ifndef __ARM_VEXPRESS_CTA15A7_H__\r | |
17 | #define __ARM_VEXPRESS_CTA15A7_H__\r | |
18 | \r | |
19 | #include <VExpressMotherBoard.h>\r | |
20 | \r | |
21 | /***********************************************************************************\r | |
22 | // Platform Memory Map\r | |
23 | ************************************************************************************/\r | |
24 | \r | |
25 | // Motherboard Peripheral and On-chip peripheral\r | |
26 | #define ARM_VE_BOARD_PERIPH_BASE 0x1C010000\r | |
27 | \r | |
28 | #ifdef ARM_BIGLITTLE_TC2\r | |
29 | \r | |
30 | // Secure NOR Flash\r | |
31 | #define ARM_VE_SEC_NOR0_BASE 0x00000000\r | |
32 | #define ARM_VE_SEC_NOR0_SZ SIZE_64MB\r | |
33 | \r | |
34 | // Secure RAM\r | |
35 | #define ARM_VE_SEC_RAM0_BASE 0x04000000\r | |
36 | #define ARM_VE_SEC_RAM0_SZ SIZE_64MB\r | |
37 | \r | |
38 | #endif\r | |
39 | \r | |
40 | // NOR Flash 0\r | |
41 | #define ARM_VE_SMB_NOR0_BASE 0x08000000\r | |
42 | #define ARM_VE_SMB_NOR0_SZ SIZE_64MB\r | |
43 | // NOR Flash 1\r | |
44 | #define ARM_VE_SMB_NOR1_BASE 0x0C000000\r | |
45 | #define ARM_VE_SMB_NOR1_SZ SIZE_64MB\r | |
46 | \r | |
47 | // SRAM\r | |
48 | #define ARM_VE_SMB_SRAM_BASE 0x14000000\r | |
49 | #define ARM_VE_SMB_SRAM_SZ SIZE_32MB\r | |
50 | \r | |
51 | // USB, Ethernet, VRAM\r | |
52 | #ifdef ARM_BIGLITTLE_TC2\r | |
53 | #define ARM_VE_SMB_PERIPH_BASE 0x18000000\r | |
54 | #define ARM_VE_SMB_PERIPH_SZ (SIZE_64MB + SIZE_32MB + SIZE_16MB)\r | |
55 | #else\r | |
56 | #define ARM_VE_SMB_PERIPH_BASE 0x1C000000\r | |
57 | #define ARM_VE_SMB_PERIPH_SZ (SIZE_64MB + SIZE_16MB)\r | |
58 | #endif\r | |
59 | #define PL111_CLCD_VRAM_MOTHERBOARD_BASE ARM_VE_SMB_PERIPH_BASE\r | |
60 | \r | |
61 | // On-Chip non-secure ROM\r | |
62 | #ifdef ARM_BIGLITTLE_TC2\r | |
63 | #define ARM_VE_TC2_NON_SECURE_ROM_BASE 0x1F000000\r | |
64 | #define ARM_VE_TC2_NON_SECURE_ROM_SZ SIZE_16MB\r | |
65 | #endif\r | |
66 | \r | |
67 | // On-Chip Peripherals\r | |
68 | #define ARM_VE_ONCHIP_PERIPH_BASE 0x20000000\r | |
69 | #define ARM_VE_ONCHIP_PERIPH_SZ 0x10000000\r | |
70 | \r | |
71 | // On-Chip non-secure SRAM\r | |
72 | #ifdef ARM_BIGLITTLE_TC2\r | |
73 | #define ARM_VE_TC2_NON_SECURE_SRAM_BASE 0x2E000000\r | |
74 | #define ARM_VE_TC2_NON_SECURE_SRAM_SZ SIZE_64KB\r | |
75 | #endif\r | |
76 | \r | |
77 | // Allocate a section for the VRAM (Video RAM)\r | |
78 | // If 0 then allow random memory allocation\r | |
79 | #define LCD_VRAM_CORE_TILE_BASE 0\r | |
80 | \r | |
81 | // Define SEC phase sync point\r | |
82 | #define ARM_SEC_EVENT_BOOT_IMAGE_TABLE_IS_AVAILABLE (ARM_SEC_EVENT_MAX + 1)\r | |
83 | \r | |
84 | /***********************************************************************************\r | |
85 | Core Tile memory-mapped Peripherals\r | |
86 | ************************************************************************************/\r | |
87 | \r | |
88 | // PL354 Static Memory Controller Base\r | |
89 | #ifdef ARM_BIGLITTLE_TC2\r | |
90 | #define ARM_VE_SMC_CTRL_BASE 0x7FFD0000\r | |
91 | #else\r | |
92 | #define ARM_VE_SMC_CTRL_BASE (ARM_VE_BOARD_PERIPH_BASE + 0xE1000)\r | |
93 | #endif\r | |
94 | \r | |
95 | #define ARM_CTA15A7_SCC_BASE 0x7FFF0000\r | |
96 | #define ARM_CTA15A7_SCC_CFGREG48 (ARM_CTA15A7_SCC_BASE + 0x700)\r | |
97 | \r | |
98 | #define ARM_CTA15A7_SCC_SYSINFO ARM_CTA15A7_SCC_CFGREG48\r | |
99 | \r | |
100 | #define ARM_CTA15A7_SCC_SYSINFO_CLUSTER_A7_NUM_CPU(val) (((val) >> 20) & 0xF)\r | |
101 | #define ARM_CTA15A7_SCC_SYSINFO_CLUSTER_A15_NUM_CPU(val) (((val) >> 16) & 0xF)\r | |
102 | #define ARM_CTA15A7_SCC_SYSINFO_ACTIVE_CLUSTER_A15 (1 << 0)\r | |
103 | #define ARM_CTA15A7_SCC_SYSINFO_ACTIVE_CLUSTER_A7 (1 << 1)\r | |
104 | \r | |
105 | #define ARM_CTA15A7_SPC_BASE 0x7FFF0B00\r | |
106 | #define ARM_CTA15A7_SPC_WAKE_INT_MASK (ARM_CTA15A7_SPC_BASE + 0x24)\r | |
107 | #define ARM_CTA15A7_SPC_STANDBYWFI_STAT (ARM_CTA15A7_SPC_BASE + 0x3C)\r | |
108 | #define ARM_CTA15A7_SPC_A15_BX_ADDR0 (ARM_CTA15A7_SPC_BASE + 0x68)\r | |
109 | #define ARM_CTA15A7_SPC_A15_BX_ADDR1 (ARM_CTA15A7_SPC_BASE + 0x6C)\r | |
110 | #define ARM_CTA15A7_SPC_A15_BX_ADDR2 (ARM_CTA15A7_SPC_BASE + 0x70)\r | |
111 | #define ARM_CTA15A7_SPC_A15_BX_ADDR3 (ARM_CTA15A7_SPC_BASE + 0x74)\r | |
112 | #define ARM_CTA15A7_SPC_A7_BX_ADDR0 (ARM_CTA15A7_SPC_BASE + 0x78)\r | |
113 | #define ARM_CTA15A7_SPC_A7_BX_ADDR1 (ARM_CTA15A7_SPC_BASE + 0x7C)\r | |
114 | #define ARM_CTA15A7_SPC_A7_BX_ADDR2 (ARM_CTA15A7_SPC_BASE + 0x80)\r | |
115 | #define ARM_CTA15A7_SPC_A7_BX_ADDR3 (ARM_CTA15A7_SPC_BASE + 0x84)\r | |
116 | \r | |
117 | #define ARM_CTA15A7_SPC_WAKE_INT_MASK_IRQ_A15_MASK_0 (1 << 0)\r | |
118 | #define ARM_CTA15A7_SPC_WAKE_INT_MASK_IRQ_A15_MASK_1 (1 << 1)\r | |
119 | #define ARM_CTA15A7_SPC_WAKE_INT_MASK_FIQ_A15_MASK_0 (1 << 2)\r | |
120 | #define ARM_CTA15A7_SPC_WAKE_INT_MASK_FIQ_A15_MASK_1 (1 << 3)\r | |
121 | #define ARM_CTA15A7_SPC_WAKE_INT_MASK_IRQ_A7_MASK_0 (1 << 4)\r | |
122 | #define ARM_CTA15A7_SPC_WAKE_INT_MASK_IRQ_A7_MASK_1 (1 << 5)\r | |
123 | #define ARM_CTA15A7_SPC_WAKE_INT_MASK_IRQ_A7_MASK_2 (1 << 6)\r | |
124 | #define ARM_CTA15A7_SPC_WAKE_INT_MASK_FIQ_A7_MASK_0 (1 << 7)\r | |
125 | #define ARM_CTA15A7_SPC_WAKE_INT_MASK_FIQ_A7_MASK_1 (1 << 8)\r | |
126 | #define ARM_CTA15A7_SPC_WAKE_INT_MASK_FIQ_A7_MASK_2 (1 << 9)\r | |
127 | \r | |
128 | #define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A15_0 (1 << 0)\r | |
129 | #define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A15_1 (1 << 1)\r | |
130 | #define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A15_L2 (1 << 2)\r | |
131 | #define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A7_0 (1 << 3)\r | |
132 | #define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A7_1 (1 << 4)\r | |
133 | #define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A7_2 (1 << 5)\r | |
134 | #define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A7_L2 (1 << 6)\r | |
135 | \r | |
136 | \r | |
137 | /***********************************************************************************\r | |
138 | // Memory-mapped peripherals\r | |
139 | ************************************************************************************/\r | |
140 | \r | |
141 | /*// SP810 Controller\r | |
142 | #undef SP810_CTRL_BASE\r | |
143 | #define SP810_CTRL_BASE 0x1C020000\r | |
144 | \r | |
145 | // PL111 Colour LCD Controller\r | |
146 | #define PL111_CLCD_SITE ARM_VE_MOTHERBOARD_SITE\r | |
147 | #define PL111_CLCD_MOTHERBOARD_VIDEO_MODE_OSC_ID 1\r | |
148 | #define PL111_CLCD_CORE_TILE_VIDEO_MODE_OSC_ID 1\r | |
149 | \r | |
150 | // VRAM offset for the PL111 Colour LCD Controller on the motherboard\r | |
151 | #define VRAM_MOTHERBOARD_BASE (ARM_VE_SMB_PERIPH_BASE + 0x00000)*/\r | |
152 | \r | |
153 | #endif\r |