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1ddb209e | 1 | /** @file\r |
2 | * Header defining Versatile Express constants (Base addresses, sizes, flags)\r | |
3 | *\r | |
4 | * Copyright (c) 2011, ARM Limited. All rights reserved.\r | |
5 | *\r | |
6 | * This program and the accompanying materials\r | |
7 | * are licensed and made available under the terms and conditions of the BSD License\r | |
8 | * which accompanies this distribution. The full text of the license may be found at\r | |
9 | * http://opensource.org/licenses/bsd-license.php\r | |
10 | *\r | |
11 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | *\r | |
14 | **/\r | |
15 | \r | |
16 | #ifndef __ARM_VEXPRESS_H__\r | |
17 | #define __ARM_VEXPRESS_H__\r | |
18 | \r | |
19 | #include <VExpressMotherBoard.h>\r | |
20 | \r | |
21 | /***********************************************************************************\r | |
22 | // Platform Memory Map\r | |
23 | ************************************************************************************/\r | |
24 | \r | |
25 | // Can be NOR0, NOR1, DRAM\r | |
26 | #define ARM_VE_REMAP_BASE 0x00000000\r | |
27 | #define ARM_VE_REMAP_SZ SIZE_64MB\r | |
28 | \r | |
29 | // Motherboard Peripheral and On-chip peripheral\r | |
30 | #define ARM_VE_BOARD_PERIPH_BASE 0x1C010000\r | |
31 | \r | |
32 | // NOR Flash 1 | |
33 | // There is typo in the reference manual for the Base address of NOR Flash 1\r | |
34 | #define ARM_VE_SMB_NOR0_BASE 0x08000000\r | |
35 | #define ARM_VE_SMB_NOR0_SZ SIZE_64MB\r | |
36 | // NOR Flash 2\r | |
37 | #define ARM_VE_SMB_NOR1_BASE 0x0C000000\r | |
38 | #define ARM_VE_SMB_NOR1_SZ SIZE_64MB\r | |
39 | // SRAM\r | |
40 | #define ARM_VE_SMB_SRAM_BASE 0x2E000000\r | |
41 | #define ARM_VE_SMB_SRAM_SZ SIZE_64KB\r | |
42 | // USB, Ethernet, VRAM\r | |
43 | #define ARM_VE_SMB_PERIPH_BASE 0x18000000\r | |
44 | #define PL111_CLCD_VRAM_MOTHERBOARD_BASE ARM_VE_SMB_PERIPH_BASE\r | |
45 | #define ARM_VE_SMB_PERIPH_SZ SIZE_64MB\r | |
46 | \r | |
47 | // DRAM\r | |
48 | #define ARM_VE_DRAM_BASE PcdGet32 (PcdSystemMemoryBase)\r | |
49 | #define ARM_VE_DRAM_SZ PcdGet32 (PcdSystemMemorySize)\r | |
50 | \r | |
51 | // This can be any value since we only support motherboard PL111\r | |
52 | #define LCD_VRAM_CORE_TILE_BASE 0x00000000\r | |
53 | \r | |
54 | // On-chip peripherals (Snoop Control Unit etc...)\r | |
55 | #define ARM_VE_ON_CHIP_PERIPH_BASE 0x2C000000\r | |
56 | // Note: The TRM says not all the peripherals are implemented\r | |
57 | #define ARM_VE_ON_CHIP_PERIPH_SZ SIZE_256MB\r | |
58 | \r | |
59 | \r | |
60 | // External AXI between daughterboards (Logic Tile)\r | |
61 | #define ARM_VE_EXT_AXI_BASE 0x2E010000 // Not modelled\r | |
62 | #define ARM_VE_EXT_AXI_SZ 0x20000000 /* 512 MB */\r | |
63 | \r | |
64 | /***********************************************************************************\r | |
65 | // Memory-mapped peripherals\r | |
66 | ************************************************************************************/\r | |
67 | \r | |
68 | // Note: There is no System Configuration Controller on the Model,\r | |
69 | // So do dummy definition to avoid build failures\r | |
70 | #define ARM_VE_SCC_BASE\r | |
71 | \r | |
72 | // SP810 Controller\r | |
73 | #define SP810_CTRL_BASE 0x1C020000\r | |
74 | \r | |
75 | // PL111 Colour LCD Controller\r | |
76 | #define PL111_CLCD_SITE ARM_VE_MOTHERBOARD_SITE\r | |
77 | #define PL111_CLCD_MOTHERBOARD_VIDEO_MODE_OSC_ID 1\r | |
78 | #define PL111_CLCD_CORE_TILE_VIDEO_MODE_OSC_ID 1\r | |
79 | \r | |
80 | // VRAM offset for the PL111 Colour LCD Controller on the motherboard\r | |
81 | #define VRAM_MOTHERBOARD_BASE (ARM_VE_SMB_PERIPH_BASE + 0x00000)\r | |
82 | \r | |
83 | #endif\r |