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295c2eb8 | 1 | /** @file\r |
2 | *\r | |
3 | * Copyright (c) 2012, ARM Limited. All rights reserved.\r | |
295c2eb8 | 4 | *\r |
3402aac7 RC |
5 | * This program and the accompanying materials\r |
6 | * are licensed and made available under the terms and conditions of the BSD License\r | |
7 | * which accompanies this distribution. The full text of the license may be found at\r | |
8 | * http://opensource.org/licenses/bsd-license.php\r | |
9 | *\r | |
10 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
295c2eb8 | 12 | *\r |
13 | **/\r | |
14 | \r | |
15 | #include <Library/IoLib.h>\r | |
16 | #include <Library/ArmPlatformLib.h>\r | |
17 | #include <Library/DebugLib.h>\r | |
18 | #include <Library/PcdLib.h>\r | |
19 | \r | |
20 | #include <Ppi/ArmMpCoreInfo.h>\r | |
21 | \r | |
22 | #include <ArmPlatform.h>\r | |
23 | \r | |
24 | ARM_CORE_INFO mVersatileExpressCTA15A7InfoTable[] = {\r | |
25 | {\r | |
26 | // Cluster 0, Core 0\r | |
27 | 0x0, 0x0,\r | |
28 | \r | |
29 | // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r | |
30 | (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR0,\r | |
31 | (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR0,\r | |
32 | (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR0,\r | |
33 | (UINT64)0\r | |
34 | },\r | |
35 | {\r | |
36 | // Cluster 0, Core 1\r | |
37 | 0x0, 0x1,\r | |
38 | \r | |
39 | // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r | |
40 | (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR1,\r | |
41 | (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR1,\r | |
42 | (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR1,\r | |
43 | (UINT64)0\r | |
44 | },\r | |
45 | #ifndef ARM_BIGLITTLE_TC2\r | |
46 | {\r | |
47 | // Cluster 0, Core 2\r | |
48 | 0x0, 0x2,\r | |
49 | \r | |
50 | // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r | |
51 | (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR2,\r | |
52 | (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR2,\r | |
53 | (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR2,\r | |
54 | (UINT64)0\r | |
55 | },\r | |
56 | {\r | |
57 | // Cluster 0, Core 3\r | |
58 | 0x0, 0x3,\r | |
59 | \r | |
60 | // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r | |
61 | (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR3,\r | |
62 | (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR3,\r | |
63 | (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR3,\r | |
64 | (UINT64)0\r | |
65 | },\r | |
66 | #endif\r | |
67 | {\r | |
68 | // Cluster 1, Core 0\r | |
69 | 0x1, 0x0,\r | |
70 | \r | |
71 | // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r | |
72 | (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR0,\r | |
73 | (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR0,\r | |
74 | (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR0,\r | |
75 | (UINT64)0\r | |
76 | },\r | |
77 | {\r | |
78 | // Cluster 1, Core 1\r | |
79 | 0x1, 0x1,\r | |
80 | \r | |
81 | // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r | |
82 | (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR1,\r | |
83 | (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR1,\r | |
84 | (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR1,\r | |
85 | (UINT64)0\r | |
86 | },\r | |
87 | {\r | |
88 | // Cluster 1, Core 2\r | |
89 | 0x1, 0x2,\r | |
90 | \r | |
91 | // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r | |
92 | (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR2,\r | |
93 | (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR2,\r | |
94 | (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR2,\r | |
95 | (UINT64)0\r | |
96 | }\r | |
97 | #ifndef ARM_BIGLITTLE_TC2\r | |
98 | ,{\r | |
99 | // Cluster 1, Core 3\r | |
100 | 0x1, 0x3,\r | |
101 | \r | |
102 | // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r | |
103 | (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR3,\r | |
104 | (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR3,\r | |
105 | (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR3,\r | |
106 | (UINT64)0\r | |
107 | }\r | |
108 | #endif\r | |
109 | };\r | |
110 | \r | |
111 | /**\r | |
112 | Return the current Boot Mode\r | |
113 | \r | |
114 | This function returns the boot reason on the platform\r | |
115 | \r | |
116 | @return Return the current Boot Mode of the platform\r | |
117 | \r | |
118 | **/\r | |
119 | EFI_BOOT_MODE\r | |
120 | ArmPlatformGetBootMode (\r | |
121 | VOID\r | |
122 | )\r | |
123 | {\r | |
9f5c60c3 | 124 | if (MmioRead32(ARM_CTA15A7_SCC_SYSINFO) & ARM_CTA15A7_SCC_SYSINFO_UEFI_RESTORE_DEFAULT_NORFLASH) {\r |
125 | return BOOT_WITH_DEFAULT_SETTINGS;\r | |
126 | } else {\r | |
127 | return BOOT_WITH_FULL_CONFIGURATION;\r | |
128 | }\r | |
295c2eb8 | 129 | }\r |
130 | \r | |
131 | /**\r | |
132 | Initialize controllers that must setup in the normal world\r | |
133 | \r | |
134 | This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim\r | |
135 | in the PEI phase.\r | |
136 | \r | |
137 | **/\r | |
138 | RETURN_STATUS\r | |
139 | ArmPlatformInitialize (\r | |
140 | IN UINTN MpId\r | |
141 | )\r | |
142 | {\r | |
bebda7ce | 143 | if (!ArmPlatformIsPrimaryCore (MpId)) {\r |
295c2eb8 | 144 | return RETURN_SUCCESS;\r |
145 | }\r | |
146 | \r | |
147 | // Nothing to do here\r | |
148 | \r | |
149 | return RETURN_SUCCESS;\r | |
150 | }\r | |
151 | \r | |
152 | /**\r | |
153 | Initialize the system (or sometimes called permanent) memory\r | |
154 | \r | |
155 | This memory is generally represented by the DRAM.\r | |
156 | \r | |
157 | **/\r | |
158 | VOID\r | |
159 | ArmPlatformInitializeSystemMemory (\r | |
160 | VOID\r | |
161 | )\r | |
162 | {\r | |
163 | }\r | |
164 | \r | |
165 | EFI_STATUS\r | |
166 | PrePeiCoreGetMpCoreInfo (\r | |
167 | OUT UINTN *CoreCount,\r | |
168 | OUT ARM_CORE_INFO **ArmCoreTable\r | |
169 | )\r | |
170 | {\r | |
171 | // Only support one cluster\r | |
172 | *CoreCount = sizeof(mVersatileExpressCTA15A7InfoTable) / sizeof(ARM_CORE_INFO);\r | |
173 | *ArmCoreTable = mVersatileExpressCTA15A7InfoTable;\r | |
174 | return EFI_SUCCESS;\r | |
175 | }\r | |
176 | \r | |
177 | // Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore\r | |
178 | EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID;\r | |
179 | ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };\r | |
180 | \r | |
181 | EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {\r | |
182 | {\r | |
183 | EFI_PEI_PPI_DESCRIPTOR_PPI,\r | |
184 | &mArmMpCoreInfoPpiGuid,\r | |
185 | &mMpCoreInfoPpi\r | |
186 | }\r | |
187 | };\r | |
188 | \r | |
189 | VOID\r | |
190 | ArmPlatformGetPlatformPpiList (\r | |
191 | OUT UINTN *PpiListSize,\r | |
192 | OUT EFI_PEI_PPI_DESCRIPTOR **PpiList\r | |
193 | )\r | |
194 | {\r | |
195 | *PpiListSize = sizeof(gPlatformPpiTable);\r | |
196 | *PpiList = gPlatformPpiTable;\r | |
197 | }\r |