ArmPlatformPkg: Remove an unused function.

[mirror_edk2.git] / ArmPlatformPkg / ArmVExpressPkg / Library / ArmVExpressLibRTSM / RTSMMem.c

/** @file\r
*\r
*  Copyright (c) 2011, ARM Limited. All rights reserved.\r
*  \r
*  This program and the accompanying materials                          \r
*  are licensed and made available under the terms and conditions of the BSD License         \r
*  which accompanies this distribution.  The full text of the license may be found at        \r
*  http://opensource.org/licenses/bsd-license.php                                            \r
*\r
*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
*\r
**/\r
\r
#include <Library/ArmPlatformLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/PcdLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
#include <ArmPlatform.h>\r
\r
// Number of Virtual Memory Map Descriptors without a Logic Tile\r
#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS          5\r
\r
// DDR attributes\r
#define DDR_ATTRIBUTES_CACHED           ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK\r
#define DDR_ATTRIBUTES_UNCACHED         ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED\r
\r
/**\r
  Return the Virtual Memory Map of your platform\r
\r
  This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.\r
\r
  @param[out]   VirtualMemoryMap    Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-\r
                                    Virtual Memory mapping. This array must be ended by a zero-filled\r
                                    entry\r
\r
**/\r
VOID\r
ArmPlatformGetVirtualMemoryMap (\r
  IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap\r
  )\r
{\r
  ARM_MEMORY_REGION_ATTRIBUTES  CacheAttributes;\r
  UINTN                         Index = 0;\r
  ARM_MEMORY_REGION_DESCRIPTOR  *VirtualMemoryTable;\r
\r
  ASSERT(VirtualMemoryMap != NULL);\r
\r
  VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));\r
  if (VirtualMemoryTable == NULL) {\r
      return;\r
  }\r
\r
  if (FeaturePcdGet(PcdCacheEnable) == TRUE) {\r
      CacheAttributes = DDR_ATTRIBUTES_CACHED;\r
  } else {\r
      CacheAttributes = DDR_ATTRIBUTES_UNCACHED;\r
  }\r
\r
  // ReMap (Either NOR Flash or DRAM)\r
  VirtualMemoryTable[Index].PhysicalBase = ARM_VE_REMAP_BASE;\r
  VirtualMemoryTable[Index].VirtualBase  = ARM_VE_REMAP_BASE;\r
  VirtualMemoryTable[Index].Length       = ARM_VE_REMAP_SZ;\r
\r
  if (FeaturePcdGet(PcdNorFlashRemapping) == FALSE) {\r
    // Map the NOR Flash as Secure Memory\r
    if (FeaturePcdGet(PcdCacheEnable) == TRUE) {\r
      VirtualMemoryTable[Index].Attributes   = DDR_ATTRIBUTES_CACHED;\r
    } else {\r
      VirtualMemoryTable[Index].Attributes   = DDR_ATTRIBUTES_UNCACHED;\r
    }\r
  } else {\r
    // DRAM mapping\r
    VirtualMemoryTable[Index].Attributes   = CacheAttributes;\r
  }\r
\r
  // DDR\r
  VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_DRAM_BASE;\r
  VirtualMemoryTable[Index].VirtualBase  = ARM_VE_DRAM_BASE;\r
  VirtualMemoryTable[Index].Length       = ARM_VE_DRAM_SZ;\r
  VirtualMemoryTable[Index].Attributes   = CacheAttributes;\r
\r
  // CPU peripherals. TRM. Manual says not all of them are implemented.\r
  VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_ON_CHIP_PERIPH_BASE;\r
  VirtualMemoryTable[Index].VirtualBase  = ARM_VE_ON_CHIP_PERIPH_BASE;\r
  VirtualMemoryTable[Index].Length       = ARM_VE_ON_CHIP_PERIPH_SZ;\r
  VirtualMemoryTable[Index].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
\r
  // SMB CS0-CS1 - NOR Flash 1 & 2\r
  VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR0_BASE;\r
  VirtualMemoryTable[Index].VirtualBase  = ARM_VE_SMB_NOR0_BASE;\r
  VirtualMemoryTable[Index].Length       = ARM_VE_SMB_NOR0_SZ + ARM_VE_SMB_NOR1_SZ;\r
  VirtualMemoryTable[Index].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
\r
  // SMB CS2 - SRAM\r
  VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_SRAM_BASE;\r
  VirtualMemoryTable[Index].VirtualBase  = ARM_VE_SMB_SRAM_BASE;\r
  VirtualMemoryTable[Index].Length       = ARM_VE_SMB_SRAM_SZ;\r
  VirtualMemoryTable[Index].Attributes   = CacheAttributes;\r
\r
  // Peripheral CS2 and CS3\r
  VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_PERIPH_BASE;\r
  VirtualMemoryTable[Index].VirtualBase  = ARM_VE_SMB_PERIPH_BASE;\r
  VirtualMemoryTable[Index].Length       = 2 * ARM_VE_SMB_PERIPH_SZ;\r
  VirtualMemoryTable[Index].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
\r
//TODO:This should be enabled for final release. Right now, ARM VE RTSM crashes.\r
//  // If a Logic Tile is connected to The ARM Versatile Express Motherboard\r
//  if (MmioRead32(ARM_VE_SYS_PROCID1_REG) != 0) {\r
//      VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_EXT_AXI_BASE;\r
//      VirtualMemoryTable[Index].VirtualBase  = ARM_VE_EXT_AXI_BASE;\r
//      VirtualMemoryTable[Index].Length       = ARM_VE_EXT_AXI_SZ;\r
//      VirtualMemoryTable[Index].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
//\r
//      ASSERT((Index + 1) == (MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS + 1));\r
//  } else {\r
//    ASSERT((Index + 1) == MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);\r
//  }\r
\r
  // End of Table\r
  VirtualMemoryTable[++Index].PhysicalBase = 0;\r
  VirtualMemoryTable[Index].VirtualBase  = 0;\r
  VirtualMemoryTable[Index].Length       = 0;\r
  VirtualMemoryTable[Index].Attributes   = (ARM_MEMORY_REGION_ATTRIBUTES)0;\r
\r
  *VirtualMemoryMap = VirtualMemoryTable;\r
}\r