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7d0f2f23 | 1 | /** @file\r |
2 | \r | |
3 | Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>\r | |
4 | This program and the accompanying materials\r | |
5 | are licensed and made available under the terms and conditions of the BSD License\r | |
6 | which accompanies this distribution. The full text of the license may be found at\r | |
7 | http://opensource.org/licenses/bsd-license.php\r | |
8 | \r | |
9 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
10 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
11 | \r | |
12 | **/\r | |
13 | \r | |
14 | #include <PiDxe.h>\r | |
15 | \r | |
16 | #include <Library/ArmPlatformSysConfigLib.h>\r | |
17 | #include <Library/IoLib.h>\r | |
18 | #include <Library/PcdLib.h>\r | |
19 | #include <Library/DebugLib.h>\r | |
20 | #include <Library/LcdPlatformLib.h>\r | |
21 | #include <Library/UefiBootServicesTableLib.h>\r | |
22 | \r | |
23 | #include <Protocol/Cpu.h>\r | |
24 | \r | |
25 | #include <ArmPlatform.h>\r | |
26 | \r | |
27 | #define PL111_CLCD_SITE ARM_VE_DAUGHTERBOARD_1_SITE\r | |
28 | \r | |
29 | typedef struct {\r | |
30 | UINT32 Mode;\r | |
31 | UINT32 HorizontalResolution;\r | |
32 | UINT32 VerticalResolution;\r | |
33 | LCD_BPP Bpp;\r | |
34 | UINT32 OscFreq;\r | |
35 | \r | |
36 | UINT32 HSync;\r | |
37 | UINT32 HBackPorch;\r | |
38 | UINT32 HFrontPorch;\r | |
39 | UINT32 VSync;\r | |
40 | UINT32 VBackPorch;\r | |
41 | UINT32 VFrontPorch;\r | |
42 | } LCD_RESOLUTION;\r | |
43 | \r | |
44 | \r | |
45 | LCD_RESOLUTION mResolutions[] = {\r | |
46 | { // Mode 0 : VGA : 640 x 480 x 24 bpp\r | |
47 | VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, VGA_OSC_FREQUENCY,\r | |
48 | VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH,\r | |
49 | VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH\r | |
50 | },\r | |
51 | { // Mode 1 : SVGA : 800 x 600 x 24 bpp\r | |
52 | SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, SVGA_OSC_FREQUENCY,\r | |
53 | SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH,\r | |
54 | SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH\r | |
55 | },\r | |
56 | { // Mode 2 : XGA : 1024 x 768 x 24 bpp\r | |
57 | XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, XGA_OSC_FREQUENCY,\r | |
58 | XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH,\r | |
59 | XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH\r | |
60 | },\r | |
61 | { // Mode 3 : SXGA : 1280 x 1024 x 24 bpp\r | |
62 | SXGA, SXGA_H_RES_PIXELS, SXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (SXGA_OSC_FREQUENCY/2),\r | |
63 | SXGA_H_SYNC, SXGA_H_BACK_PORCH, SXGA_H_FRONT_PORCH,\r | |
64 | SXGA_V_SYNC, SXGA_V_BACK_PORCH, SXGA_V_FRONT_PORCH\r | |
65 | },\r | |
66 | { // Mode 4 : UXGA : 1600 x 1200 x 24 bpp\r | |
67 | UXGA, UXGA_H_RES_PIXELS, UXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (UXGA_OSC_FREQUENCY/2),\r | |
68 | UXGA_H_SYNC, UXGA_H_BACK_PORCH, UXGA_H_FRONT_PORCH,\r | |
69 | UXGA_V_SYNC, UXGA_V_BACK_PORCH, UXGA_V_FRONT_PORCH\r | |
70 | },\r | |
71 | { // Mode 5 : HD : 1920 x 1080 x 24 bpp\r | |
72 | HD, HD_H_RES_PIXELS, HD_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (HD_OSC_FREQUENCY/2),\r | |
73 | HD_H_SYNC, HD_H_BACK_PORCH, HD_H_FRONT_PORCH,\r | |
74 | HD_V_SYNC, HD_V_BACK_PORCH, HD_V_FRONT_PORCH\r | |
75 | },\r | |
76 | { // Mode 6 : VGA : 640 x 480 x 16 bpp (565 Mode)\r | |
77 | VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_565, VGA_OSC_FREQUENCY,\r | |
78 | VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH,\r | |
79 | VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH\r | |
80 | },\r | |
81 | { // Mode 7 : SVGA : 800 x 600 x 16 bpp (565 Mode)\r | |
82 | SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_565, SVGA_OSC_FREQUENCY,\r | |
83 | SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH,\r | |
84 | SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH\r | |
85 | },\r | |
86 | { // Mode 8 : XGA : 1024 x 768 x 16 bpp (565 Mode)\r | |
87 | XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_565, XGA_OSC_FREQUENCY,\r | |
88 | XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH,\r | |
89 | XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH\r | |
90 | },\r | |
91 | { // Mode 9 : VGA : 640 x 480 x 15 bpp\r | |
92 | VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, VGA_OSC_FREQUENCY,\r | |
93 | VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH,\r | |
94 | VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH\r | |
95 | },\r | |
96 | { // Mode 10 : SVGA : 800 x 600 x 15 bpp\r | |
97 | SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, SVGA_OSC_FREQUENCY,\r | |
98 | SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH,\r | |
99 | SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH\r | |
100 | },\r | |
101 | { // Mode 11 : XGA : 1024 x 768 x 15 bpp\r | |
102 | XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, XGA_OSC_FREQUENCY,\r | |
103 | XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH,\r | |
104 | XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH\r | |
105 | },\r | |
106 | { // Mode 12 : XGA : 1024 x 768 x 15 bpp - All the timing info is derived from Linux Kernel Driver Settings\r | |
107 | XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, 63500000,\r | |
108 | XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH,\r | |
109 | XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH\r | |
110 | },\r | |
111 | { // Mode 13 : VGA : 640 x 480 x 12 bpp (444 Mode)\r | |
112 | VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_12_444, VGA_OSC_FREQUENCY,\r | |
113 | VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH,\r | |
114 | VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH\r | |
115 | },\r | |
116 | { // Mode 14 : SVGA : 800 x 600 x 12 bpp (444 Mode)\r | |
117 | SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_12_444, SVGA_OSC_FREQUENCY,\r | |
118 | SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH,\r | |
119 | SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH\r | |
120 | },\r | |
121 | { // Mode 15 : XGA : 1024 x 768 x 12 bpp (444 Mode)\r | |
122 | XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_12_444, XGA_OSC_FREQUENCY,\r | |
123 | XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH,\r | |
124 | XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH\r | |
125 | }\r | |
126 | };\r | |
127 | \r | |
128 | EFI_STATUS\r | |
129 | LcdPlatformInitializeDisplay (\r | |
130 | VOID\r | |
131 | ) {\r | |
132 | // Set the FPGA multiplexer to select the video output from the motherboard or the daughterboard\r | |
133 | return ArmPlatformSysConfigSet (SYS_CFG_MUXFPGA, PL111_CLCD_SITE);\r | |
134 | }\r | |
135 | \r | |
136 | EFI_STATUS\r | |
137 | LcdPlatformGetVram (\r | |
138 | OUT EFI_PHYSICAL_ADDRESS* VramBaseAddress,\r | |
139 | OUT UINTN* VramSize\r | |
140 | )\r | |
141 | {\r | |
142 | EFI_STATUS Status;\r | |
143 | EFI_CPU_ARCH_PROTOCOL *Cpu;\r | |
144 | \r | |
145 | // Is it on the motherboard or on the daughterboard?\r | |
146 | switch(PL111_CLCD_SITE) {\r | |
147 | \r | |
148 | case ARM_VE_MOTHERBOARD_SITE:\r | |
149 | *VramBaseAddress = (EFI_PHYSICAL_ADDRESS) PL111_CLCD_VRAM_MOTHERBOARD_BASE;\r | |
150 | *VramSize = LCD_VRAM_SIZE;\r | |
151 | break;\r | |
152 | \r | |
153 | case ARM_VE_DAUGHTERBOARD_1_SITE:\r | |
154 | *VramBaseAddress = (EFI_PHYSICAL_ADDRESS) LCD_VRAM_CORE_TILE_BASE;\r | |
155 | *VramSize = LCD_VRAM_SIZE;\r | |
156 | \r | |
157 | // Allocate the VRAM from the DRAM so that nobody else uses it.\r | |
158 | Status = gBS->AllocatePages( AllocateAddress, EfiBootServicesData, EFI_SIZE_TO_PAGES(((UINTN)LCD_VRAM_SIZE)), VramBaseAddress);\r | |
159 | if (EFI_ERROR(Status)) {\r | |
160 | return Status;\r | |
161 | }\r | |
162 | \r | |
163 | // Ensure the Cpu architectural protocol is already installed\r | |
164 | Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu);\r | |
165 | ASSERT_EFI_ERROR(Status);\r | |
166 | \r | |
167 | // Mark the VRAM as un-cachable. The VRAM is inside the DRAM, which is cachable.\r | |
168 | Status = Cpu->SetMemoryAttributes(Cpu, *VramBaseAddress, *VramSize, EFI_MEMORY_UC);\r | |
169 | ASSERT_EFI_ERROR(Status);\r | |
170 | if (EFI_ERROR(Status)) {\r | |
171 | gBS->FreePool(VramBaseAddress);\r | |
172 | return Status;\r | |
173 | }\r | |
174 | break;\r | |
175 | \r | |
176 | default:\r | |
177 | // Unsupported site\r | |
178 | Status = EFI_UNSUPPORTED;\r | |
179 | break;\r | |
180 | }\r | |
181 | \r | |
182 | return Status;\r | |
183 | }\r | |
184 | \r | |
185 | UINT32\r | |
186 | LcdPlatformGetMaxMode (\r | |
187 | VOID\r | |
188 | )\r | |
189 | {\r | |
190 | // The following line will report correctly the total number of graphics modes\r | |
191 | // supported by the PL111CLCD.\r | |
192 | //return (sizeof(mResolutions) / sizeof(CLCD_RESOLUTION)) - 1;\r | |
193 | \r | |
194 | // However, on some platforms it is desirable to ignore some graphics modes.\r | |
195 | // This could be because the specific implementation of PL111 has certain limitations.\r | |
196 | \r | |
197 | // Set the maximum mode allowed\r | |
5cc45b70 | 198 | return (PcdGet32(PcdPL111LcdMaxMode));\r |
7d0f2f23 | 199 | }\r |
200 | \r | |
201 | EFI_STATUS\r | |
202 | LcdPlatformSetMode (\r | |
203 | IN UINT32 ModeNumber\r | |
204 | )\r | |
205 | {\r | |
206 | EFI_STATUS Status;\r | |
207 | UINT32 LcdSite;\r | |
208 | UINT32 OscillatorId;\r | |
209 | SYS_CONFIG_FUNCTION Function;\r | |
210 | \r | |
211 | if (ModeNumber >= LcdPlatformGetMaxMode ()) {\r | |
212 | return EFI_INVALID_PARAMETER;\r | |
213 | }\r | |
214 | \r | |
215 | LcdSite = PL111_CLCD_SITE;\r | |
216 | \r | |
217 | switch(LcdSite) {\r | |
218 | case ARM_VE_MOTHERBOARD_SITE:\r | |
219 | Function = SYS_CFG_OSC;\r | |
220 | OscillatorId = PL111_CLCD_MOTHERBOARD_VIDEO_MODE_OSC_ID;\r | |
221 | break;\r | |
222 | case ARM_VE_DAUGHTERBOARD_1_SITE:\r | |
223 | Function = SYS_CFG_OSC_SITE1;\r | |
5cc45b70 | 224 | OscillatorId = (UINT32)PcdGet32(PcdPL111LcdVideoModeOscId);\r |
7d0f2f23 | 225 | break;\r |
226 | default:\r | |
227 | return EFI_UNSUPPORTED;\r | |
228 | }\r | |
229 | \r | |
230 | // Set the video mode oscillator\r | |
231 | Status = ArmPlatformSysConfigSetDevice (Function, OscillatorId, mResolutions[ModeNumber].OscFreq);\r | |
232 | if (EFI_ERROR(Status)) {\r | |
233 | ASSERT_EFI_ERROR (Status);\r | |
234 | return Status;\r | |
235 | }\r | |
236 | \r | |
237 | // Set the DVI into the new mode\r | |
238 | Status = ArmPlatformSysConfigSet (SYS_CFG_DVIMODE, mResolutions[ModeNumber].Mode);\r | |
239 | if (EFI_ERROR(Status)) {\r | |
240 | ASSERT_EFI_ERROR (Status);\r | |
241 | return Status;\r | |
242 | }\r | |
243 | \r | |
244 | // Set the multiplexer\r | |
245 | Status = ArmPlatformSysConfigSet (SYS_CFG_MUXFPGA, LcdSite);\r | |
246 | if (EFI_ERROR(Status)) {\r | |
247 | ASSERT_EFI_ERROR (Status);\r | |
248 | return Status;\r | |
249 | }\r | |
250 | \r | |
251 | return Status;\r | |
252 | }\r | |
253 | \r | |
254 | EFI_STATUS\r | |
255 | LcdPlatformQueryMode (\r | |
256 | IN UINT32 ModeNumber,\r | |
257 | OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION *Info\r | |
258 | )\r | |
259 | {\r | |
260 | if (ModeNumber >= LcdPlatformGetMaxMode ()) {\r | |
261 | return EFI_INVALID_PARAMETER;\r | |
262 | }\r | |
263 | \r | |
264 | Info->Version = 0;\r | |
265 | Info->HorizontalResolution = mResolutions[ModeNumber].HorizontalResolution;\r | |
266 | Info->VerticalResolution = mResolutions[ModeNumber].VerticalResolution;\r | |
267 | Info->PixelsPerScanLine = mResolutions[ModeNumber].HorizontalResolution;\r | |
268 | \r | |
269 | switch (mResolutions[ModeNumber].Bpp) {\r | |
270 | case LCD_BITS_PER_PIXEL_24:\r | |
271 | Info->PixelFormat = PixelRedGreenBlueReserved8BitPerColor;\r | |
272 | Info->PixelInformation.RedMask = LCD_24BPP_RED_MASK;\r | |
273 | Info->PixelInformation.GreenMask = LCD_24BPP_GREEN_MASK;\r | |
274 | Info->PixelInformation.BlueMask = LCD_24BPP_BLUE_MASK;\r | |
275 | Info->PixelInformation.ReservedMask = LCD_24BPP_RESERVED_MASK;\r | |
276 | break;\r | |
277 | \r | |
278 | case LCD_BITS_PER_PIXEL_16_555:\r | |
279 | case LCD_BITS_PER_PIXEL_16_565:\r | |
280 | case LCD_BITS_PER_PIXEL_12_444:\r | |
281 | case LCD_BITS_PER_PIXEL_8:\r | |
282 | case LCD_BITS_PER_PIXEL_4:\r | |
283 | case LCD_BITS_PER_PIXEL_2:\r | |
284 | case LCD_BITS_PER_PIXEL_1:\r | |
285 | default:\r | |
286 | // These are not supported\r | |
287 | ASSERT(FALSE);\r | |
288 | break;\r | |
289 | }\r | |
290 | \r | |
291 | return EFI_SUCCESS;\r | |
292 | }\r | |
293 | \r | |
294 | EFI_STATUS\r | |
295 | LcdPlatformGetTimings (\r | |
296 | IN UINT32 ModeNumber,\r | |
297 | OUT UINT32* HRes,\r | |
298 | OUT UINT32* HSync,\r | |
299 | OUT UINT32* HBackPorch,\r | |
300 | OUT UINT32* HFrontPorch,\r | |
301 | OUT UINT32* VRes,\r | |
302 | OUT UINT32* VSync,\r | |
303 | OUT UINT32* VBackPorch,\r | |
304 | OUT UINT32* VFrontPorch\r | |
305 | )\r | |
306 | {\r | |
307 | if (ModeNumber >= LcdPlatformGetMaxMode ()) {\r | |
308 | return EFI_INVALID_PARAMETER;\r | |
309 | }\r | |
310 | \r | |
311 | *HRes = mResolutions[ModeNumber].HorizontalResolution;\r | |
312 | *HSync = mResolutions[ModeNumber].HSync;\r | |
313 | *HBackPorch = mResolutions[ModeNumber].HBackPorch;\r | |
314 | *HFrontPorch = mResolutions[ModeNumber].HFrontPorch;\r | |
315 | *VRes = mResolutions[ModeNumber].VerticalResolution;\r | |
316 | *VSync = mResolutions[ModeNumber].VSync;\r | |
317 | *VBackPorch = mResolutions[ModeNumber].VBackPorch;\r | |
318 | *VFrontPorch = mResolutions[ModeNumber].VFrontPorch;\r | |
319 | \r | |
320 | return EFI_SUCCESS;\r | |
321 | }\r | |
322 | \r | |
323 | EFI_STATUS\r | |
324 | LcdPlatformGetBpp (\r | |
325 | IN UINT32 ModeNumber,\r | |
326 | OUT LCD_BPP * Bpp\r | |
327 | )\r | |
328 | {\r | |
329 | if (ModeNumber >= LcdPlatformGetMaxMode ()) {\r | |
330 | return EFI_INVALID_PARAMETER;\r | |
331 | }\r | |
332 | \r | |
333 | *Bpp = mResolutions[ModeNumber].Bpp;\r | |
334 | \r | |
335 | return EFI_SUCCESS;\r | |
336 | }\r |