[mirror_edk2.git] / ArmPlatformPkg / ArmVExpressPkg / Library / PL111LcdArmVExpressLib / PL111LcdArmVExpress.c

/** @file\r
\r
  Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>\r
  This program and the accompanying materials\r
  are licensed and made available under the terms and conditions of the BSD License\r
  which accompanies this distribution.  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#include <PiDxe.h>\r
\r
#include <Library/ArmPlatformSysConfigLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/PcdLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/LcdPlatformLib.h>\r
#include <Library/UefiBootServicesTableLib.h>\r
\r
#include <Protocol/Cpu.h>\r
\r
#include <ArmPlatform.h>\r
\r
typedef struct {\r
  UINT32                     Mode;\r
  UINT32                     HorizontalResolution;\r
  UINT32                     VerticalResolution;\r
  LCD_BPP                    Bpp;\r
  UINT32                     OscFreq;\r
\r
  UINT32                     HSync;\r
  UINT32                     HBackPorch;\r
  UINT32                     HFrontPorch;\r
  UINT32                     VSync;\r
  UINT32                     VBackPorch;\r
  UINT32                     VFrontPorch;\r
} LCD_RESOLUTION;\r
\r
\r
LCD_RESOLUTION mResolutions[] = {\r
    { // Mode 0 : VGA : 640 x 480 x 24 bpp\r
        VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, VGA_OSC_FREQUENCY,\r
        VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH,\r
        VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH\r
    },\r
    { // Mode 1 : SVGA : 800 x 600 x 24 bpp\r
        SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, SVGA_OSC_FREQUENCY,\r
        SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH,\r
        SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH\r
    },\r
    { // Mode 2 : XGA : 1024 x 768 x 24 bpp\r
        XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, XGA_OSC_FREQUENCY,\r
        XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH,\r
        XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH\r
    },\r
    { // Mode 3 : SXGA : 1280 x 1024 x 24 bpp\r
        SXGA, SXGA_H_RES_PIXELS, SXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (SXGA_OSC_FREQUENCY/2),\r
        SXGA_H_SYNC, SXGA_H_BACK_PORCH, SXGA_H_FRONT_PORCH,\r
        SXGA_V_SYNC, SXGA_V_BACK_PORCH, SXGA_V_FRONT_PORCH\r
    },\r
    { // Mode 4 : UXGA : 1600 x 1200 x 24 bpp\r
        UXGA, UXGA_H_RES_PIXELS, UXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (UXGA_OSC_FREQUENCY/2),\r
        UXGA_H_SYNC, UXGA_H_BACK_PORCH, UXGA_H_FRONT_PORCH,\r
        UXGA_V_SYNC, UXGA_V_BACK_PORCH, UXGA_V_FRONT_PORCH\r
    },\r
    { // Mode 5 : HD : 1920 x 1080 x 24 bpp\r
        HD, HD_H_RES_PIXELS, HD_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (HD_OSC_FREQUENCY/2),\r
        HD_H_SYNC, HD_H_BACK_PORCH, HD_H_FRONT_PORCH,\r
        HD_V_SYNC, HD_V_BACK_PORCH, HD_V_FRONT_PORCH\r
    },\r
    { // Mode 6 : VGA : 640 x 480 x 16 bpp (565 Mode)\r
        VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_565, VGA_OSC_FREQUENCY,\r
        VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH,\r
        VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH\r
    },\r
    { // Mode 7 : SVGA : 800 x 600 x 16 bpp (565 Mode)\r
        SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_565, SVGA_OSC_FREQUENCY,\r
        SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH,\r
        SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH\r
    },\r
    { // Mode 8 : XGA : 1024 x 768 x 16 bpp (565 Mode)\r
        XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_565, XGA_OSC_FREQUENCY,\r
        XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH,\r
        XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH\r
    },\r
    { // Mode 9 : VGA : 640 x 480 x 15 bpp\r
        VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, VGA_OSC_FREQUENCY,\r
        VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH,\r
        VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH\r
    },\r
    { // Mode 10 : SVGA : 800 x 600 x 15 bpp\r
        SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, SVGA_OSC_FREQUENCY,\r
        SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH,\r
        SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH\r
    },\r
    { // Mode 11 : XGA : 1024 x 768 x 15 bpp\r
        XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, XGA_OSC_FREQUENCY,\r
        XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH,\r
        XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH\r
    },\r
    { // Mode 12 : XGA : 1024 x 768 x 15 bpp - All the timing info is derived from Linux Kernel Driver Settings\r
        XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, 63500000,\r
        XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH,\r
        XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH\r
    },\r
    { // Mode 13 : VGA : 640 x 480 x 12 bpp (444 Mode)\r
        VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_12_444, VGA_OSC_FREQUENCY,\r
        VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH,\r
        VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH\r
    },\r
    { // Mode 14 : SVGA : 800 x 600 x 12 bpp (444 Mode)\r
        SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_12_444, SVGA_OSC_FREQUENCY,\r
        SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH,\r
        SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH\r
    },\r
    { // Mode 15 : XGA : 1024 x 768 x 12 bpp (444 Mode)\r
        XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_12_444, XGA_OSC_FREQUENCY,\r
        XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH,\r
        XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH\r
    }\r
};\r
\r
EFI_STATUS\r
LcdPlatformInitializeDisplay (\r
  VOID\r
  ) {\r
  // Set the FPGA multiplexer to select the video output from the motherboard or the daughterboard\r
  return ArmPlatformSysConfigSet (SYS_CFG_MUXFPGA, PL111_CLCD_SITE);\r
}\r
\r
EFI_STATUS\r
LcdPlatformGetVram (\r
  OUT EFI_PHYSICAL_ADDRESS*  VramBaseAddress,\r
  OUT UINTN*                 VramSize\r
  )\r
{\r
  EFI_STATUS              Status;\r
  EFI_CPU_ARCH_PROTOCOL  *Cpu;\r
\r
  Status = EFI_SUCCESS;\r
\r
  // Is it on the motherboard or on the daughterboard?\r
  switch(PL111_CLCD_SITE) {\r
\r
  case ARM_VE_MOTHERBOARD_SITE:\r
    *VramBaseAddress = (EFI_PHYSICAL_ADDRESS) PL111_CLCD_VRAM_MOTHERBOARD_BASE;\r
    *VramSize = LCD_VRAM_SIZE;\r
    break;\r
\r
  case ARM_VE_DAUGHTERBOARD_1_SITE:\r
    *VramBaseAddress = (EFI_PHYSICAL_ADDRESS) LCD_VRAM_CORE_TILE_BASE;\r
    *VramSize = LCD_VRAM_SIZE;\r
\r
    // Allocate the VRAM from the DRAM so that nobody else uses it.\r
    Status = gBS->AllocatePages( AllocateAddress, EfiBootServicesData, EFI_SIZE_TO_PAGES(((UINTN)LCD_VRAM_SIZE)), VramBaseAddress);\r
    if (EFI_ERROR(Status)) {\r
      return Status;\r
    }\r
\r
    // Ensure the Cpu architectural protocol is already installed\r
    Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu);\r
    ASSERT_EFI_ERROR(Status);\r
\r
    // Mark the VRAM as un-cachable. The VRAM is inside the DRAM, which is cachable.\r
    Status = Cpu->SetMemoryAttributes(Cpu, *VramBaseAddress, *VramSize, EFI_MEMORY_UC);\r
    ASSERT_EFI_ERROR(Status);\r
    if (EFI_ERROR(Status)) {\r
      gBS->FreePool(VramBaseAddress);\r
      return Status;\r
    }\r
    break;\r
\r
  default:\r
    // Unsupported site\r
    Status = EFI_UNSUPPORTED;\r
    break;\r
  }\r
\r
  return Status;\r
}\r
\r
UINT32\r
LcdPlatformGetMaxMode (\r
  VOID\r
  )\r
{\r
  // The following line will report correctly the total number of graphics modes\r
  // supported by the PL111CLCD.\r
  //return (sizeof(mResolutions) / sizeof(CLCD_RESOLUTION)) - 1;\r
\r
  // However, on some platforms it is desirable to ignore some graphics modes.\r
  // This could be because the specific implementation of PL111 has certain limitations.\r
\r
  // Set the maximum mode allowed\r
  return (PcdGet32(PcdPL111LcdMaxMode));\r
}\r
\r
EFI_STATUS\r
LcdPlatformSetMode (\r
  IN UINT32                         ModeNumber\r
  )\r
{\r
  EFI_STATUS            Status;\r
  UINT32                LcdSite;\r
  UINT32                OscillatorId;\r
  SYS_CONFIG_FUNCTION   Function;\r
\r
  if (ModeNumber >= LcdPlatformGetMaxMode ()) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  LcdSite = PL111_CLCD_SITE;\r
\r
  switch(LcdSite) {\r
  case ARM_VE_MOTHERBOARD_SITE:\r
    Function = SYS_CFG_OSC;\r
    OscillatorId = PL111_CLCD_MOTHERBOARD_VIDEO_MODE_OSC_ID;\r
    break;\r
  case ARM_VE_DAUGHTERBOARD_1_SITE:\r
    Function = SYS_CFG_OSC_SITE1;\r
    OscillatorId = (UINT32)PcdGet32(PcdPL111LcdVideoModeOscId);\r
    break;\r
  default:\r
    return EFI_UNSUPPORTED;\r
  }\r
\r
  // Set the video mode oscillator\r
  Status = ArmPlatformSysConfigSetDevice (Function, OscillatorId, mResolutions[ModeNumber].OscFreq);\r
  if (EFI_ERROR(Status)) {\r
    ASSERT_EFI_ERROR (Status);\r
    return Status;\r
  }\r
\r
  // On the ARM Versatile Express Model (RTSM) the value of the SysId is equal to 0x225F500.\r
  // Note: The DVI Mode is not modelled on RTSM\r
  if (MmioRead32 (ARM_VE_SYS_ID_REG) != 0x225F500) {\r
    // Set the DVI into the new mode\r
    Status = ArmPlatformSysConfigSet (SYS_CFG_DVIMODE, mResolutions[ModeNumber].Mode);\r
    if (EFI_ERROR(Status)) {\r
      ASSERT_EFI_ERROR (Status);\r
      return Status;\r
    }\r
  }\r
\r
  // Set the multiplexer\r
  Status = ArmPlatformSysConfigSet (SYS_CFG_MUXFPGA, LcdSite);\r
  if (EFI_ERROR(Status)) {\r
    ASSERT_EFI_ERROR (Status);\r
    return Status;\r
  }\r
\r
  return Status;\r
}\r
\r
EFI_STATUS\r
LcdPlatformQueryMode (\r
  IN  UINT32                                ModeNumber,\r
  OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION  *Info\r
  )\r
{\r
  if (ModeNumber >= LcdPlatformGetMaxMode ()) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  Info->Version = 0;\r
  Info->HorizontalResolution = mResolutions[ModeNumber].HorizontalResolution;\r
  Info->VerticalResolution = mResolutions[ModeNumber].VerticalResolution;\r
  Info->PixelsPerScanLine = mResolutions[ModeNumber].HorizontalResolution;\r
\r
  switch (mResolutions[ModeNumber].Bpp) {\r
    case LCD_BITS_PER_PIXEL_24:\r
      Info->PixelFormat                   = PixelRedGreenBlueReserved8BitPerColor;\r
      Info->PixelInformation.RedMask      = LCD_24BPP_RED_MASK;\r
      Info->PixelInformation.GreenMask    = LCD_24BPP_GREEN_MASK;\r
      Info->PixelInformation.BlueMask     = LCD_24BPP_BLUE_MASK;\r
      Info->PixelInformation.ReservedMask = LCD_24BPP_RESERVED_MASK;\r
      break;\r
\r
    case LCD_BITS_PER_PIXEL_16_555:\r
    case LCD_BITS_PER_PIXEL_16_565:\r
    case LCD_BITS_PER_PIXEL_12_444:\r
    case LCD_BITS_PER_PIXEL_8:\r
    case LCD_BITS_PER_PIXEL_4:\r
    case LCD_BITS_PER_PIXEL_2:\r
    case LCD_BITS_PER_PIXEL_1:\r
    default:\r
      // These are not supported\r
      ASSERT(FALSE);\r
      break;\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r
\r
EFI_STATUS\r
LcdPlatformGetTimings (\r
  IN  UINT32                              ModeNumber,\r
  OUT UINT32*                             HRes,\r
  OUT UINT32*                             HSync,\r
  OUT UINT32*                             HBackPorch,\r
  OUT UINT32*                             HFrontPorch,\r
  OUT UINT32*                             VRes,\r
  OUT UINT32*                             VSync,\r
  OUT UINT32*                             VBackPorch,\r
  OUT UINT32*                             VFrontPorch\r
  )\r
{\r
  if (ModeNumber >= LcdPlatformGetMaxMode ()) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  *HRes           = mResolutions[ModeNumber].HorizontalResolution;\r
  *HSync          = mResolutions[ModeNumber].HSync;\r
  *HBackPorch     = mResolutions[ModeNumber].HBackPorch;\r
  *HFrontPorch    = mResolutions[ModeNumber].HFrontPorch;\r
  *VRes           = mResolutions[ModeNumber].VerticalResolution;\r
  *VSync          = mResolutions[ModeNumber].VSync;\r
  *VBackPorch     = mResolutions[ModeNumber].VBackPorch;\r
  *VFrontPorch    = mResolutions[ModeNumber].VFrontPorch;\r
\r
  return EFI_SUCCESS;\r
}\r
\r
EFI_STATUS\r
LcdPlatformGetBpp (\r
  IN  UINT32                              ModeNumber,\r
  OUT LCD_BPP  *                          Bpp\r
  )\r
{\r
  if (ModeNumber >= LcdPlatformGetMaxMode ()) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  *Bpp = mResolutions[ModeNumber].Bpp;\r
\r
  return EFI_SUCCESS;\r
}\r
Commit	Line	Data
7d0f2f23	1	/** @file\r
	2	\r
	3	Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>\r
	4	This program and the accompanying materials\r
	5	are licensed and made available under the terms and conditions of the BSD License\r
	6	which accompanies this distribution. The full text of the license may be found at\r
	7	http://opensource.org/licenses/bsd-license.php\r
	8	\r
	9	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	10	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	11	\r
	12	**/\r
	13	\r
	14	#include <PiDxe.h>\r
	15	\r
	16	#include <Library/ArmPlatformSysConfigLib.h>\r
	17	#include <Library/IoLib.h>\r
	18	#include <Library/PcdLib.h>\r
	19	#include <Library/DebugLib.h>\r
	20	#include <Library/LcdPlatformLib.h>\r
	21	#include <Library/UefiBootServicesTableLib.h>\r
	22	\r
	23	#include <Protocol/Cpu.h>\r
	24	\r
	25	#include <ArmPlatform.h>\r
	26	\r
7d0f2f23	27	typedef struct {\r
	28	UINT32 Mode;\r
	29	UINT32 HorizontalResolution;\r
	30	UINT32 VerticalResolution;\r
	31	LCD_BPP Bpp;\r
	32	UINT32 OscFreq;\r
	33	\r
	34	UINT32 HSync;\r
	35	UINT32 HBackPorch;\r
	36	UINT32 HFrontPorch;\r
	37	UINT32 VSync;\r
	38	UINT32 VBackPorch;\r
	39	UINT32 VFrontPorch;\r
	40	} LCD_RESOLUTION;\r
	41	\r
	42	\r
	43	LCD_RESOLUTION mResolutions[] = {\r
	44	{ // Mode 0 : VGA : 640 x 480 x 24 bpp\r
	45	VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, VGA_OSC_FREQUENCY,\r
	46	VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH,\r
	47	VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH\r
	48	},\r
	49	{ // Mode 1 : SVGA : 800 x 600 x 24 bpp\r
	50	SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, SVGA_OSC_FREQUENCY,\r
	51	SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH,\r
	52	SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH\r
	53	},\r
	54	{ // Mode 2 : XGA : 1024 x 768 x 24 bpp\r
	55	XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, XGA_OSC_FREQUENCY,\r
	56	XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH,\r
	57	XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH\r
	58	},\r
	59	{ // Mode 3 : SXGA : 1280 x 1024 x 24 bpp\r
	60	SXGA, SXGA_H_RES_PIXELS, SXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (SXGA_OSC_FREQUENCY/2),\r
	61	SXGA_H_SYNC, SXGA_H_BACK_PORCH, SXGA_H_FRONT_PORCH,\r
	62	SXGA_V_SYNC, SXGA_V_BACK_PORCH, SXGA_V_FRONT_PORCH\r
	63	},\r
	64	{ // Mode 4 : UXGA : 1600 x 1200 x 24 bpp\r
	65	UXGA, UXGA_H_RES_PIXELS, UXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (UXGA_OSC_FREQUENCY/2),\r
	66	UXGA_H_SYNC, UXGA_H_BACK_PORCH, UXGA_H_FRONT_PORCH,\r
	67	UXGA_V_SYNC, UXGA_V_BACK_PORCH, UXGA_V_FRONT_PORCH\r
	68	},\r
	69	{ // Mode 5 : HD : 1920 x 1080 x 24 bpp\r
	70	HD, HD_H_RES_PIXELS, HD_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (HD_OSC_FREQUENCY/2),\r
	71	HD_H_SYNC, HD_H_BACK_PORCH, HD_H_FRONT_PORCH,\r
	72	HD_V_SYNC, HD_V_BACK_PORCH, HD_V_FRONT_PORCH\r
	73	},\r
	74	{ // Mode 6 : VGA : 640 x 480 x 16 bpp (565 Mode)\r
	75	VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_565, VGA_OSC_FREQUENCY,\r
	76	VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH,\r
	77	VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH\r
	78	},\r
	79	{ // Mode 7 : SVGA : 800 x 600 x 16 bpp (565 Mode)\r
	80	SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_565, SVGA_OSC_FREQUENCY,\r
	81	SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH,\r
	82	SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH\r
	83	},\r
	84	{ // Mode 8 : XGA : 1024 x 768 x 16 bpp (565 Mode)\r
	85	XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_565, XGA_OSC_FREQUENCY,\r
	86	XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH,\r
	87	XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH\r
	88	},\r
	89	{ // Mode 9 : VGA : 640 x 480 x 15 bpp\r
	90	VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, VGA_OSC_FREQUENCY,\r
91	VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH,\r
92	VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH\r
93	},\r
94	{ // Mode 10 : SVGA : 800 x 600 x 15 bpp\r
95	SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, SVGA_OSC_FREQUENCY,\r
96	SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH,\r
97	SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH\r
98	},\r
99	{ // Mode 11 : XGA : 1024 x 768 x 15 bpp\r
100	XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, XGA_OSC_FREQUENCY,\r
101	XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH,\r
102	XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH\r
103	},\r
104	{ // Mode 12 : XGA : 1024 x 768 x 15 bpp - All the timing info is derived from Linux Kernel Driver Settings\r
105	XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, 63500000,\r
106	XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH,\r
107	XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH\r
108	},\r
109	{ // Mode 13 : VGA : 640 x 480 x 12 bpp (444 Mode)\r
110	VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_12_444, VGA_OSC_FREQUENCY,\r
111	VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH,\r
112	VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH\r
113	},\r
114	{ // Mode 14 : SVGA : 800 x 600 x 12 bpp (444 Mode)\r
115	SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_12_444, SVGA_OSC_FREQUENCY,\r
116	SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH,\r
117	SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH\r
118	},\r
119	{ // Mode 15 : XGA : 1024 x 768 x 12 bpp (444 Mode)\r
120	XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_12_444, XGA_OSC_FREQUENCY,\r
121	XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH,\r
122	XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH\r
123	}\r
124	};\r
125	\r
126	EFI_STATUS\r
127	LcdPlatformInitializeDisplay (\r
128	VOID\r
129	) {\r
130	// Set the FPGA multiplexer to select the video output from the motherboard or the daughterboard\r
131	return ArmPlatformSysConfigSet (SYS_CFG_MUXFPGA, PL111_CLCD_SITE);\r
132	}\r
133	\r
134	EFI_STATUS\r
135	LcdPlatformGetVram (\r
136	OUT EFI_PHYSICAL_ADDRESS* VramBaseAddress,\r
137	OUT UINTN* VramSize\r
138	)\r
139	{\r
140	EFI_STATUS Status;\r
141	EFI_CPU_ARCH_PROTOCOL *Cpu;\r
142	\r
11c20f4e	143	Status = EFI_SUCCESS;\r
11c20f4e	144	\r
7d0f2f23	145	// Is it on the motherboard or on the daughterboard?\r
	146	switch(PL111_CLCD_SITE) {\r
	147	\r
	148	case ARM_VE_MOTHERBOARD_SITE:\r
	149	*VramBaseAddress = (EFI_PHYSICAL_ADDRESS) PL111_CLCD_VRAM_MOTHERBOARD_BASE;\r
	150	*VramSize = LCD_VRAM_SIZE;\r
	151	break;\r
	152	\r
	153	case ARM_VE_DAUGHTERBOARD_1_SITE:\r
	154	*VramBaseAddress = (EFI_PHYSICAL_ADDRESS) LCD_VRAM_CORE_TILE_BASE;\r
	155	*VramSize = LCD_VRAM_SIZE;\r
	156	\r
	157	// Allocate the VRAM from the DRAM so that nobody else uses it.\r
	158	Status = gBS->AllocatePages( AllocateAddress, EfiBootServicesData, EFI_SIZE_TO_PAGES(((UINTN)LCD_VRAM_SIZE)), VramBaseAddress);\r
	159	if (EFI_ERROR(Status)) {\r
	160	return Status;\r
	161	}\r
	162	\r
	163	// Ensure the Cpu architectural protocol is already installed\r
	164	Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu);\r
	165	ASSERT_EFI_ERROR(Status);\r
	166	\r
	167	// Mark the VRAM as un-cachable. The VRAM is inside the DRAM, which is cachable.\r
	168	Status = Cpu->SetMemoryAttributes(Cpu, VramBaseAddress, VramSize, EFI_MEMORY_UC);\r
	169	ASSERT_EFI_ERROR(Status);\r
	170	if (EFI_ERROR(Status)) {\r
	171	gBS->FreePool(VramBaseAddress);\r
	172	return Status;\r
	173	}\r
	174	break;\r
	175	\r
	176	default:\r
	177	// Unsupported site\r
	178	Status = EFI_UNSUPPORTED;\r
	179	break;\r
	180	}\r
	181	\r
	182	return Status;\r
	183	}\r
	184	\r
	185	UINT32\r
	186	LcdPlatformGetMaxMode (\r
	187	VOID\r
	188	)\r
	189	{\r
	190	// The following line will report correctly the total number of graphics modes\r
	191	// supported by the PL111CLCD.\r
	192	//return (sizeof(mResolutions) / sizeof(CLCD_RESOLUTION)) - 1;\r
	193	\r
	194	// However, on some platforms it is desirable to ignore some graphics modes.\r
	195	// This could be because the specific implementation of PL111 has certain limitations.\r
	196	\r
	197	// Set the maximum mode allowed\r
5cc45b70	198	return (PcdGet32(PcdPL111LcdMaxMode));\r
7d0f2f23	199	}\r
	200	\r
	201	EFI_STATUS\r
	202	LcdPlatformSetMode (\r
	203	IN UINT32 ModeNumber\r
	204	)\r
	205	{\r
	206	EFI_STATUS Status;\r
	207	UINT32 LcdSite;\r
	208	UINT32 OscillatorId;\r
	209	SYS_CONFIG_FUNCTION Function;\r
	210	\r
	211	if (ModeNumber >= LcdPlatformGetMaxMode ()) {\r
	212	return EFI_INVALID_PARAMETER;\r
	213	}\r
	214	\r
	215	LcdSite = PL111_CLCD_SITE;\r
	216	\r
	217	switch(LcdSite) {\r
	218	case ARM_VE_MOTHERBOARD_SITE:\r
	219	Function = SYS_CFG_OSC;\r
	220	OscillatorId = PL111_CLCD_MOTHERBOARD_VIDEO_MODE_OSC_ID;\r
	221	break;\r
	222	case ARM_VE_DAUGHTERBOARD_1_SITE:\r
	223	Function = SYS_CFG_OSC_SITE1;\r
5cc45b70	224	OscillatorId = (UINT32)PcdGet32(PcdPL111LcdVideoModeOscId);\r
7d0f2f23	225	break;\r
	226	default:\r
	227	return EFI_UNSUPPORTED;\r
	228	}\r
	229	\r
	230	// Set the video mode oscillator\r
	231	Status = ArmPlatformSysConfigSetDevice (Function, OscillatorId, mResolutions[ModeNumber].OscFreq);\r
	232	if (EFI_ERROR(Status)) {\r
	233	ASSERT_EFI_ERROR (Status);\r
	234	return Status;\r
	235	}\r
	236	\r
1ddb209e	237	// On the ARM Versatile Express Model (RTSM) the value of the SysId is equal to 0x225F500.\r
	238	// Note: The DVI Mode is not modelled on RTSM\r
	239	if (MmioRead32 (ARM_VE_SYS_ID_REG) != 0x225F500) {\r
	240	// Set the DVI into the new mode\r
	241	Status = ArmPlatformSysConfigSet (SYS_CFG_DVIMODE, mResolutions[ModeNumber].Mode);\r
	242	if (EFI_ERROR(Status)) {\r
	243	ASSERT_EFI_ERROR (Status);\r
	244	return Status;\r
	245	}\r
7d0f2f23	246	}\r
	247	\r
	248	// Set the multiplexer\r
	249	Status = ArmPlatformSysConfigSet (SYS_CFG_MUXFPGA, LcdSite);\r
	250	if (EFI_ERROR(Status)) {\r
	251	ASSERT_EFI_ERROR (Status);\r
	252	return Status;\r
	253	}\r
	254	\r
	255	return Status;\r
	256	}\r
	257	\r
	258	EFI_STATUS\r
	259	LcdPlatformQueryMode (\r
	260	IN UINT32 ModeNumber,\r
	261	OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION *Info\r
	262	)\r
	263	{\r
	264	if (ModeNumber >= LcdPlatformGetMaxMode ()) {\r
	265	return EFI_INVALID_PARAMETER;\r
	266	}\r
	267	\r
	268	Info->Version = 0;\r
	269	Info->HorizontalResolution = mResolutions[ModeNumber].HorizontalResolution;\r
	270	Info->VerticalResolution = mResolutions[ModeNumber].VerticalResolution;\r
	271	Info->PixelsPerScanLine = mResolutions[ModeNumber].HorizontalResolution;\r
	272	\r
	273	switch (mResolutions[ModeNumber].Bpp) {\r
	274	case LCD_BITS_PER_PIXEL_24:\r
	275	Info->PixelFormat = PixelRedGreenBlueReserved8BitPerColor;\r
	276	Info->PixelInformation.RedMask = LCD_24BPP_RED_MASK;\r
	277	Info->PixelInformation.GreenMask = LCD_24BPP_GREEN_MASK;\r
	278	Info->PixelInformation.BlueMask = LCD_24BPP_BLUE_MASK;\r
	279	Info->PixelInformation.ReservedMask = LCD_24BPP_RESERVED_MASK;\r
	280	break;\r
	281	\r
	282	case LCD_BITS_PER_PIXEL_16_555:\r
	283	case LCD_BITS_PER_PIXEL_16_565:\r
	284	case LCD_BITS_PER_PIXEL_12_444:\r
	285	case LCD_BITS_PER_PIXEL_8:\r
	286	case LCD_BITS_PER_PIXEL_4:\r
	287	case LCD_BITS_PER_PIXEL_2:\r
	288	case LCD_BITS_PER_PIXEL_1:\r
	289	default:\r
	290	// These are not supported\r
	291	ASSERT(FALSE);\r
	292	break;\r
	293	}\r
	294	\r
	295	return EFI_SUCCESS;\r
	296	}\r
	297	\r
	298	EFI_STATUS\r
	299	LcdPlatformGetTimings (\r
	300	IN UINT32 ModeNumber,\r
	301	OUT UINT32* HRes,\r
	302	OUT UINT32* HSync,\r
	303	OUT UINT32* HBackPorch,\r
	304	OUT UINT32* HFrontPorch,\r
	305	OUT UINT32* VRes,\r
	306	OUT UINT32* VSync,\r
	307	OUT UINT32* VBackPorch,\r
	308	OUT UINT32* VFrontPorch\r
	309	)\r
310	{\r
311	if (ModeNumber >= LcdPlatformGetMaxMode ()) {\r
312	return EFI_INVALID_PARAMETER;\r
313	}\r
314	\r
315	*HRes = mResolutions[ModeNumber].HorizontalResolution;\r
316	*HSync = mResolutions[ModeNumber].HSync;\r
317	*HBackPorch = mResolutions[ModeNumber].HBackPorch;\r
318	*HFrontPorch = mResolutions[ModeNumber].HFrontPorch;\r
319	*VRes = mResolutions[ModeNumber].VerticalResolution;\r
320	*VSync = mResolutions[ModeNumber].VSync;\r
321	*VBackPorch = mResolutions[ModeNumber].VBackPorch;\r
322	*VFrontPorch = mResolutions[ModeNumber].VFrontPorch;\r
323	\r
324	return EFI_SUCCESS;\r
325	}\r
326	\r
327	EFI_STATUS\r
328	LcdPlatformGetBpp (\r
329	IN UINT32 ModeNumber,\r
330	OUT LCD_BPP * Bpp\r
331	)\r
332	{\r
333	if (ModeNumber >= LcdPlatformGetMaxMode ()) {\r
334	return EFI_INVALID_PARAMETER;\r
335	}\r
336	\r
337	*Bpp = mResolutions[ModeNumber].Bpp;\r
338	\r
339	return EFI_SUCCESS;\r
340	}\r