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633724f4 | 1 | /** @file\r |
2 | Header for the MMC Host Protocol implementation for the ARM PrimeCell PL180.\r | |
3 | \r | |
93b429fc | 4 | Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r |
633724f4 | 5 | \r |
6 | This program and the accompanying materials \r | |
7 | are licensed and made available under the terms and conditions of the BSD License \r | |
8 | which accompanies this distribution. The full text of the license may be found at \r | |
9 | http://opensource.org/licenses/bsd-license.php \r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
13 | \r | |
14 | **/\r | |
15 | \r | |
16 | #ifndef __PL180_MCI_H\r | |
17 | #define __PL180_MCI_H\r | |
18 | \r | |
19 | #include <Uefi.h>\r | |
20 | \r | |
21 | #include <Protocol/MmcHost.h>\r | |
22 | \r | |
23 | #include <Library/UefiLib.h>\r | |
24 | #include <Library/DebugLib.h>\r | |
25 | #include <Library/UefiBootServicesTableLib.h>\r | |
26 | #include <Library/IoLib.h>\r | |
27 | #include <Library/TimerLib.h>\r | |
28 | #include <Library/PcdLib.h>\r | |
29 | \r | |
93b429fc | 30 | #define PL180_MCI_DXE_VERSION 0x10\r |
31 | \r | |
32 | #define MCI_SYSCTL FixedPcdGet32 (PcdPL180MciBaseAddress)\r | |
33 | \r | |
34 | #define MCI_POWER_CONTROL_REG (MCI_SYSCTL + 0x000)\r | |
35 | #define MCI_CLOCK_CONTROL_REG (MCI_SYSCTL + 0x004)\r | |
36 | #define MCI_ARGUMENT_REG (MCI_SYSCTL + 0x008)\r | |
37 | #define MCI_COMMAND_REG (MCI_SYSCTL + 0x00C)\r | |
38 | #define MCI_RESPCMD_REG (MCI_SYSCTL + 0x010)\r | |
39 | #define MCI_RESPONSE3_REG (MCI_SYSCTL + 0x014)\r | |
40 | #define MCI_RESPONSE2_REG (MCI_SYSCTL + 0x018)\r | |
41 | #define MCI_RESPONSE1_REG (MCI_SYSCTL + 0x01C)\r | |
42 | #define MCI_RESPONSE0_REG (MCI_SYSCTL + 0x020)\r | |
43 | #define MCI_DATA_TIMER_REG (MCI_SYSCTL + 0x024)\r | |
44 | #define MCI_DATA_LENGTH_REG (MCI_SYSCTL + 0x028)\r | |
45 | #define MCI_DATA_CTL_REG (MCI_SYSCTL + 0x02C)\r | |
46 | #define MCI_DATA_COUNTER (MCI_SYSCTL + 0x030)\r | |
47 | #define MCI_STATUS_REG (MCI_SYSCTL + 0x034)\r | |
48 | #define MCI_CLEAR_STATUS_REG (MCI_SYSCTL + 0x038)\r | |
49 | #define MCI_INT0_MASK_REG (MCI_SYSCTL + 0x03C)\r | |
50 | #define MCI_INT1_MASK_REG (MCI_SYSCTL + 0x040)\r | |
51 | #define MCI_SELECT_REG (MCI_SYSCTL + 0x044)\r | |
52 | #define MCI_FIFOCOUNT_REG (MCI_SYSCTL + 0x048)\r | |
53 | #define MCI_FIFO_REG (MCI_SYSCTL + 0x080)\r | |
54 | \r | |
55 | #define MCI_POWER_OFF 0\r | |
56 | #define MCI_POWER_UP BIT1\r | |
57 | #define MCI_POWER_ON (BIT1 | BIT0)\r | |
58 | #define MCI_POWER_OPENDRAIN BIT6\r | |
59 | #define MCI_POWER_ROD BIT7\r | |
60 | \r | |
61 | #define MCI_CLOCK_ENABLE BIT8\r | |
62 | #define MCI_CLOCK_POWERSAVE BIT9\r | |
63 | #define MCI_CLOCK_BYPASS BIT10\r | |
64 | #define MCI_CLOCK_WIDEBUS BIT11\r | |
65 | \r | |
66 | #define MCI_STATUS_CMD_CMDCRCFAIL BIT0\r | |
67 | #define MCI_STATUS_CMD_DATACRCFAIL BIT1\r | |
68 | #define MCI_STATUS_CMD_CMDTIMEOUT BIT2\r | |
69 | #define MCI_STATUS_CMD_DATATIMEOUT BIT3\r | |
70 | #define MCI_STATUS_CMD_TX_UNDERRUN BIT4\r | |
71 | #define MCI_STATUS_CMD_RXOVERRUN BIT5\r | |
72 | #define MCI_STATUS_CMD_RESPEND BIT6\r | |
73 | #define MCI_STATUS_CMD_SENT BIT7\r | |
74 | #define MCI_STATUS_CMD_DATAEND BIT8\r | |
75 | #define MCI_STATUS_CMD_START_BIT_ERROR BIT9\r | |
76 | #define MCI_STATUS_CMD_DATABLOCKEND BIT10\r | |
77 | #define MCI_STATUS_CMD_ACTIVE BIT11\r | |
78 | #define MCI_STATUS_CMD_TXACTIVE BIT12\r | |
79 | #define MCI_STATUS_CMD_RXACTIVE BIT13\r | |
80 | #define MCI_STATUS_CMD_TXFIFOHALFEMPTY BIT14\r | |
81 | #define MCI_STATUS_CMD_RXFIFOHALFFULL BIT15\r | |
82 | #define MCI_STATUS_CMD_TXFIFOFULL BIT16\r | |
83 | #define MCI_STATUS_CMD_RXFIFOFULL BIT17\r | |
84 | #define MCI_STATUS_CMD_TXFIFOEMPTY BIT18\r | |
85 | #define MCI_STATUS_CMD_RXFIFOEMPTY BIT19\r | |
86 | #define MCI_STATUS_CMD_TXDATAAVAILBL BIT20\r | |
87 | #define MCI_STATUS_CMD_RXDATAAVAILBL BIT21\r | |
88 | \r | |
89 | #define MCI_STATUS_TXDONE (MCI_STATUS_CMD_DATAEND | MCI_STATUS_CMD_DATABLOCKEND)\r | |
90 | #define MCI_STATUS_RXDONE (MCI_STATUS_CMD_DATAEND | MCI_STATUS_CMD_DATABLOCKEND)\r | |
91 | #define MCI_STATUS_READ_ERROR ( MCI_STATUS_CMD_DATACRCFAIL \\r | |
92 | | MCI_STATUS_CMD_DATATIMEOUT \\r | |
93 | | MCI_STATUS_CMD_RXOVERRUN \\r | |
94 | | MCI_STATUS_CMD_START_BIT_ERROR )\r | |
95 | #define MCI_STATUS_WRITE_ERROR ( MCI_STATUS_CMD_DATACRCFAIL \\r | |
96 | | MCI_STATUS_CMD_DATATIMEOUT \\r | |
97 | | MCI_STATUS_CMD_TX_UNDERRUN )\r | |
98 | #define MCI_STATUS_CMD_ERROR ( MCI_STATUS_CMD_CMDCRCFAIL \\r | |
99 | | MCI_STATUS_CMD_CMDTIMEOUT \\r | |
100 | | MCI_STATUS_CMD_START_BIT_ERROR )\r | |
101 | \r | |
102 | #define MCI_CLR_CMD_STATUS ( MCI_STATUS_CMD_RESPEND \\r | |
103 | | MCI_STATUS_CMD_SENT \\r | |
104 | | MCI_STATUS_CMD_ERROR )\r | |
105 | \r | |
106 | #define MCI_CLR_READ_STATUS ( MCI_STATUS_RXDONE \\r | |
107 | | MCI_STATUS_READ_ERROR )\r | |
108 | \r | |
109 | #define MCI_CLR_WRITE_STATUS ( MCI_STATUS_TXDONE \\r | |
110 | | MCI_STATUS_WRITE_ERROR )\r | |
111 | \r | |
112 | #define MCI_CLR_ALL_STATUS (BIT11 - 1)\r | |
113 | \r | |
114 | #define MCI_DATACTL_DISABLE_MASK 0xFE\r | |
115 | #define MCI_DATACTL_ENABLE BIT0\r | |
633724f4 | 116 | #define MCI_DATACTL_CONT_TO_CARD 0\r |
93b429fc | 117 | #define MCI_DATACTL_CARD_TO_CONT BIT1\r |
633724f4 | 118 | #define MCI_DATACTL_BLOCK_TRANS 0\r |
93b429fc | 119 | #define MCI_DATACTL_STREAM_TRANS BIT2\r |
120 | #define MCI_DATACTL_DMA_DISABLED 0\r | |
121 | #define MCI_DATACTL_DMA_ENABLE BIT3\r | |
633724f4 | 122 | \r |
123 | #define INDX_MASK 0x3F\r | |
124 | \r | |
93b429fc | 125 | #define MCI_CPSM_WAIT_RESPONSE BIT6\r |
126 | #define MCI_CPSM_LONG_RESPONSE BIT7\r | |
127 | #define MCI_CPSM_LONG_INTERRUPT BIT8\r | |
128 | #define MCI_CPSM_LONG_PENDING BIT9\r | |
129 | #define MCI_CPSM_ENABLE BIT10\r | |
633724f4 | 130 | \r |
93b429fc | 131 | #define MCI_TRACE(txt) DEBUG ((EFI_D_BLKIO, "ARM_MCI: " txt "\n"))\r |
633724f4 | 132 | \r |
133 | EFI_STATUS\r | |
134 | EFIAPI\r | |
135 | MciGetDriverName (\r | |
136 | IN EFI_COMPONENT_NAME_PROTOCOL *This,\r | |
137 | IN CHAR8 *Language,\r | |
138 | OUT CHAR16 **DriverName\r | |
139 | );\r | |
140 | \r | |
141 | EFI_STATUS\r | |
142 | EFIAPI\r | |
143 | MciGetControllerName (\r | |
144 | IN EFI_COMPONENT_NAME_PROTOCOL *This,\r | |
145 | IN EFI_HANDLE ControllerHandle,\r | |
146 | IN EFI_HANDLE ChildHandle OPTIONAL,\r | |
147 | IN CHAR8 *Language,\r | |
148 | OUT CHAR16 **ControllerName\r | |
149 | );\r | |
150 | \r | |
151 | #endif\r |