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633724f4 | 1 | /** @file\r |
2 | *\r | |
3 | * Copyright (c) 2011, ARM Limited. All rights reserved.\r | |
4 | * \r | |
5 | * This program and the accompanying materials \r | |
6 | * are licensed and made available under the terms and conditions of the BSD License \r | |
7 | * which accompanies this distribution. The full text of the license may be found at \r | |
8 | * http://opensource.org/licenses/bsd-license.php \r | |
9 | *\r | |
10 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
11 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
12 | *\r | |
13 | **/\r | |
14 | \r | |
15 | #include <Library/IoLib.h>\r | |
16 | #include <Library/DebugLib.h>\r | |
17 | \r | |
18 | #define PL301_QOS_TIDEMARK_MI_0 0x400\r | |
19 | #define PL301_QOS_ACCESSCONTROL_MI_0 0x404\r | |
20 | \r | |
21 | #define PL301_QOS_TIDEMARK_MI_1 0x420\r | |
22 | #define PL301_QOS_ACCESSCONTROL_MI_1 0x424\r | |
23 | \r | |
24 | #define PL301_QOS_TIDEMARK_MI_2 0x440\r | |
25 | #define PL301_QOS_ACCESSCONTROL_MI_2 0x444\r | |
26 | \r | |
27 | #define PL301_AR_ARB_MI_0 0x408\r | |
28 | #define PL301_AW_ARB_MI_0 0x40C\r | |
29 | \r | |
30 | #define PL301_AR_ARB_MI_1 0x428\r | |
31 | #define PL301_AW_ARB_MI_1 0x42C\r | |
32 | \r | |
33 | #define PL301_AR_ARB_MI_2 0x448\r | |
34 | #define PL301_AW_ARB_MI_2 0x44C\r | |
35 | \r | |
36 | #define PL301_MI_1_OFFSET 0x20\r | |
37 | #define PL301_MI_2_OFFSET 0x40\r | |
38 | #define PL301_MI_3_OFFSET 0x60\r | |
39 | #define PL301_MI_4_OFFSET 0x80\r | |
40 | #define PL301_MI_5_OFFSET 0xa0\r | |
41 | \r | |
42 | #define V2P_CA9_FAXI_MI0_TIDEMARK_VAL 0x6\r | |
43 | #define V2P_CA9_FAXI_MI0_ACCESSCNTRL_VAL 0x1\r | |
44 | \r | |
45 | #define V2P_CA9_FAXI_MI1_TIDEMARK_VAL 0x6\r | |
46 | #define V2P_CA9_FAXI_MI1_ACCESSCNTRL_VAL 0x1\r | |
47 | \r | |
48 | #define V2P_CA9_FAXI_MI2_TIDEMARK_VAL 0x6\r | |
49 | #define V2P_CA9_FAXI_MI2_ACCESSCNTRL_VAL 0x1\r | |
50 | \r | |
51 | \r | |
52 | #define FAxiWriteReg(reg,val) MmioWrite32(FAxiBase + reg, val)\r | |
53 | #define FAxiReadReg(reg) MmioRead32(FAxiBase + reg)\r | |
54 | \r | |
55 | // IN FAxiBase\r | |
56 | // Initialize PL301 Dynamic Memory Controller\r | |
57 | VOID PL301AxiInit(UINTN FAxiBase) {\r | |
58 | // Configure Tidemark Register for Master Port 0 (MI 0)\r | |
59 | FAxiWriteReg(PL301_QOS_TIDEMARK_MI_0, V2P_CA9_FAXI_MI0_TIDEMARK_VAL);\r | |
60 | \r | |
61 | // Configure the Access Control Register (MI 0)\r | |
62 | FAxiWriteReg(PL301_QOS_ACCESSCONTROL_MI_0, V2P_CA9_FAXI_MI0_ACCESSCNTRL_VAL);\r | |
63 | \r | |
64 | // MP0 \r | |
65 | // Set priority for Read\r | |
66 | FAxiWriteReg(PL301_AR_ARB_MI_0, 0x00000100);\r | |
67 | FAxiWriteReg(PL301_AR_ARB_MI_0, 0x01000200);\r | |
68 | FAxiWriteReg(PL301_AR_ARB_MI_0, 0x02000200);\r | |
69 | FAxiWriteReg(PL301_AR_ARB_MI_0, 0x03000200);\r | |
70 | FAxiWriteReg(PL301_AR_ARB_MI_0, 0x04000200);\r | |
71 | \r | |
72 | // Set priority for Write\r | |
73 | FAxiWriteReg(PL301_AW_ARB_MI_0, 0x00000100);\r | |
74 | FAxiWriteReg(PL301_AW_ARB_MI_0, 0x01000200);\r | |
75 | FAxiWriteReg(PL301_AW_ARB_MI_0, 0x02000200);\r | |
76 | FAxiWriteReg(PL301_AW_ARB_MI_0, 0x03000200);\r | |
77 | FAxiWriteReg(PL301_AW_ARB_MI_0, 0x04000200);\r | |
78 | \r | |
79 | // MP1\r | |
80 | // Set priority for Read\r | |
81 | FAxiWriteReg(PL301_AR_ARB_MI_1, 0x00000100);\r | |
82 | FAxiWriteReg(PL301_AR_ARB_MI_1, 0x01000200);\r | |
83 | FAxiWriteReg(PL301_AR_ARB_MI_1, 0x02000200);\r | |
84 | FAxiWriteReg(PL301_AR_ARB_MI_1, 0x03000200);\r | |
85 | FAxiWriteReg(PL301_AR_ARB_MI_1, 0x04000200);\r | |
86 | \r | |
87 | // Set priority for Write\r | |
88 | FAxiWriteReg(PL301_AW_ARB_MI_1, 0x00000100);\r | |
89 | FAxiWriteReg(PL301_AW_ARB_MI_1, 0x01000200);\r | |
90 | FAxiWriteReg(PL301_AW_ARB_MI_1, 0x02000200);\r | |
91 | FAxiWriteReg(PL301_AW_ARB_MI_1, 0x03000200);\r | |
92 | FAxiWriteReg(PL301_AW_ARB_MI_1, 0x04000200);\r | |
93 | \r | |
94 | // MP2\r | |
95 | // Set priority for Read\r | |
96 | FAxiWriteReg(PL301_AR_ARB_MI_2, 0x00000100);\r | |
97 | FAxiWriteReg(PL301_AR_ARB_MI_2, 0x01000100);\r | |
98 | FAxiWriteReg(PL301_AR_ARB_MI_2, 0x02000100);\r | |
99 | FAxiWriteReg(PL301_AR_ARB_MI_2, 0x03000100);\r | |
100 | FAxiWriteReg(PL301_AR_ARB_MI_2, 0x04000100);\r | |
101 | \r | |
102 | // Set priority for Write\r | |
103 | FAxiWriteReg(PL301_AW_ARB_MI_2, 0x00000100);\r | |
104 | FAxiWriteReg(PL301_AW_ARB_MI_2, 0x01000200);\r | |
105 | FAxiWriteReg(PL301_AW_ARB_MI_2, 0x02000200);\r | |
106 | FAxiWriteReg(PL301_AW_ARB_MI_2, 0x03000200);\r | |
107 | FAxiWriteReg(PL301_AW_ARB_MI_2, 0x04000200);\r | |
108 | }\r |