]>
Commit | Line | Data |
---|---|---|
633724f4 | 1 | //\r |
c54de822 | 2 | // Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r |
633724f4 | 3 | //\r |
3402aac7 RC |
4 | // This program and the accompanying materials\r |
5 | // are licensed and made available under the terms and conditions of the BSD License\r | |
6 | // which accompanies this distribution. The full text of the license may be found at\r | |
7 | // http://opensource.org/licenses/bsd-license.php\r | |
8 | //\r | |
9 | // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
10 | // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
633724f4 | 11 | //\r |
12 | //\r | |
13 | \r | |
14 | #include <AsmMacroIoLib.h>\r | |
15 | #include <Library/PcdLib.h>\r | |
16 | #include <Drivers/PL35xSmc.h>\r | |
17 | #include <AutoGen.h>\r | |
18 | \r | |
19 | INCLUDE AsmMacroIoLib.inc\r | |
3402aac7 | 20 | \r |
c52e2dca | 21 | EXPORT PL35xSmcInitialize\r |
c54de822 | 22 | EXPORT PL35xSmcSetRefresh\r |
633724f4 | 23 | \r |
24 | PRESERVE8\r | |
25 | AREA ModuleInitializeSMC, CODE, READONLY\r | |
3402aac7 | 26 | \r |
c52e2dca | 27 | // IN r1 Smc Base Address\r |
28 | // IN r2 Smc Configuration Start Address\r | |
29 | // IN r3 Smc Configuration End Address\r | |
633724f4 | 30 | // NOTE: This code is been called before any stack has been setup. It means some registers\r |
31 | // could be overwritten (case of 'r0')\r | |
c52e2dca | 32 | PL35xSmcInitialize\r |
33 | // While (SmcConfigurationStart < SmcConfigurationEnd)\r | |
34 | cmp r2, r3\r | |
35 | blxge lr\r | |
36 | \r | |
633724f4 | 37 | // Write to set_cycle register(holding register for NOR 1 cycle register or NAND cycle register)\r |
c52e2dca | 38 | ldr r0, [r2, #0x4]\r |
39 | str r0, [r1, #PL350_SMC_SET_CYCLES_OFFSET]\r | |
40 | \r | |
633724f4 | 41 | // Write to set_opmode register(holding register for NOR 1 opomode register or NAND opmode register)\r |
c52e2dca | 42 | ldr r0, [r2, #0x8]\r |
43 | str r0, [r1, #PL350_SMC_SET_OPMODE_OFFSET]\r | |
633724f4 | 44 | \r |
45 | // Write to direct_cmd register so that the NOR 1 registers(set-cycles and opmode) are updated with holding registers\r | |
c52e2dca | 46 | ldr r0, =PL350_SMC_DIRECT_CMD_ADDR_CMD_UPDATE\r |
47 | ldr r4, [r2, #0x0]\r | |
48 | orr r0, r0, r4\r | |
49 | str r0, [r1, #PL350_SMC_DIRECT_CMD_OFFSET]\r | |
633724f4 | 50 | \r |
c52e2dca | 51 | add r2, #0xC\r |
52 | b PL35xSmcInitialize\r | |
633724f4 | 53 | \r |
c54de822 | 54 | // IN r1 Smc Base Address\r |
55 | // IN r2 Smc Refresh Period 0\r | |
56 | // IN r3 Smc Refresh Period 1\r | |
57 | PL35xSmcSetRefresh\r | |
58 | str r2, [r1, #PL350_SMC_REFRESH_0_OFFSET]\r | |
59 | str r3, [r1, #PL350_SMC_REFRESH_1_OFFSET]\r | |
60 | blx lr\r | |
2575b726 | 61 | \r |
62 | END\r |