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51d191aa | 1 | /** @file\r |
2 | *\r | |
3 | * Copyright (c) 2011, ARM Limited. All rights reserved.\r | |
4 | *\r | |
5 | * This program and the accompanying materials\r | |
6 | * are licensed and made available under the terms and conditions of the BSD License\r | |
7 | * which accompanies this distribution. The full text of the license may be found at\r | |
8 | * http://opensource.org/licenses/bsd-license.php\r | |
9 | *\r | |
10 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | *\r | |
13 | **/\r | |
14 | \r | |
15 | #ifndef L2CACHELIB_H_\r | |
16 | #define L2CACHELIB_H_\r | |
17 | \r | |
18 | #define L2X0_CACHEID 0x000\r | |
19 | #define L2X0_CTRL 0x100\r | |
20 | #define L2X0_AUXCTRL 0x104\r | |
21 | #define L230_TAG_LATENCY 0x108\r | |
22 | #define L230_DATA_LATENCY 0x10C\r | |
23 | #define L2X0_INTCLEAR 0x220\r | |
24 | #define L2X0_CACHE_SYNC 0x730\r | |
25 | #define L2X0_INVWAY 0x77C\r | |
26 | #define L2X0_CLEAN_WAY 0x7BC\r | |
27 | #define L2X0_PFCTRL 0xF60\r | |
28 | #define L2X0_PWRCTRL 0xF80\r | |
29 | \r | |
30 | #define L2X0_CACHEID_IMPLEMENTER_ARM 0x41\r | |
31 | #define L2X0_CACHEID_PARTNUM_PL310 0x03\r | |
32 | \r | |
33 | #define L2X0_CTRL_ENABLED 0x1\r | |
34 | #define L2X0_CTRL_DISABLED 0x0\r | |
35 | \r | |
36 | #define L2X0_AUXCTRL_EXCLUSIVE (1 << 12)\r | |
37 | #define L2X0_AUXCTRL_ASSOCIATIVITY (1 << 16)\r | |
38 | #define L2X0_AUXCTRL_WAYSIZE_MASK (3 << 17)\r | |
39 | #define L2X0_AUXCTRL_WAYSIZE_16KB (1 << 17)\r | |
40 | #define L2X0_AUXCTRL_WAYSIZE_32KB (2 << 17)\r | |
41 | #define L2X0_AUXCTRL_WAYSIZE_64KB (3 << 17)\r | |
42 | #define L2X0_AUXCTRL_WAYSIZE_128KB (4 << 17)\r | |
43 | #define L2X0_AUXCTRL_WAYSIZE_256KB (5 << 17)\r | |
44 | #define L2X0_AUXCTRL_WAYSIZE_512KB (6 << 17)\r | |
45 | #define L2X0_AUXCTRL_EM (1 << 20)\r | |
46 | #define L2X0_AUXCTRL_SHARED_OVERRIDE (1 << 22)\r | |
47 | #define L2x0_AUXCTRL_AW_AWCACHE (0 << 23)\r | |
48 | #define L2x0_AUXCTRL_AW_NOALLOC (1 << 23)\r | |
49 | #define L2x0_AUXCTRL_AW_OVERRIDE (2 << 23)\r | |
50 | #define L2X0_AUXCTRL_SBO (1 << 25)\r | |
51 | #define L2X0_AUXCTRL_NSAC (1 << 27)\r | |
52 | #define L2x0_AUXCTRL_DPREFETCH (1 << 28)\r | |
53 | #define L2x0_AUXCTRL_IPREFETCH (1 << 29)\r | |
54 | #define L2x0_AUXCTRL_EARLY_BRESP (1 << 30)\r | |
55 | \r | |
56 | #define L2x0_LATENCY_1_CYCLE 0\r | |
57 | #define L2x0_LATENCY_2_CYCLES 1\r | |
58 | #define L2x0_LATENCY_3_CYCLES 2\r | |
59 | #define L2x0_LATENCY_4_CYCLES 3\r | |
60 | #define L2x0_LATENCY_5_CYCLES 4\r | |
61 | #define L2x0_LATENCY_6_CYCLES 5\r | |
62 | #define L2x0_LATENCY_7_CYCLES 6\r | |
63 | #define L2x0_LATENCY_8_CYCLES 7\r | |
64 | \r | |
65 | #define PL310_LATENCIES(Write,Read,Setup) (((Write) << 8) | ((Read) << 4) | (Setup))\r | |
66 | #define PL310_TAG_LATENCIES(Write,Read,Setup) PL310_LATENCIES(Write,Read,Setup)\r | |
67 | #define PL310_DATA_LATENCIES(Write,Read,Setup) PL310_LATENCIES(Write,Read,Setup)\r | |
68 | \r | |
69 | VOID\r | |
70 | L2x0CacheInit (\r | |
71 | IN UINTN L2x0Base,\r | |
72 | IN UINT32 L2x0TagLatencies,\r | |
73 | IN UINT32 L2x0DataLatencies,\r | |
74 | IN UINT32 L2x0AuxValue,\r | |
75 | IN UINT32 L2x0AuxMask,\r | |
76 | IN BOOLEAN CacheEnabled\r | |
77 | );\r | |
78 | \r | |
79 | #endif /* L2CACHELIB_H_ */\r |