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f501f5d1 | 1 | /** @file\r |
2 | *\r | |
c54de822 | 3 | * Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r |
f501f5d1 | 4 | *\r |
5 | * This program and the accompanying materials\r | |
6 | * are licensed and made available under the terms and conditions of the BSD License\r | |
7 | * which accompanies this distribution. The full text of the license may be found at\r | |
8 | * http://opensource.org/licenses/bsd-license.php\r | |
9 | *\r | |
10 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | *\r | |
13 | **/\r | |
14 | \r | |
c52e2dca | 15 | #ifndef PL35xSMC_H_\r |
16 | #define PL35xSMC_H_\r | |
f501f5d1 | 17 | \r |
c54de822 | 18 | #define PL350_SMC_DIRECT_CMD_OFFSET 0x10\r |
19 | #define PL350_SMC_SET_CYCLES_OFFSET 0x14\r | |
20 | #define PL350_SMC_SET_OPMODE_OFFSET 0x18\r | |
21 | #define PL350_SMC_REFRESH_0_OFFSET 0x20\r | |
22 | #define PL350_SMC_REFRESH_1_OFFSET 0x24\r | |
f501f5d1 | 23 | \r |
c52e2dca | 24 | #define PL350_SMC_DIRECT_CMD_ADDR(addr) ((addr) & 0xFFFFF)\r |
25 | #define PL350_SMC_DIRECT_CMD_ADDR_SET_CRE (1 << 20)\r | |
26 | #define PL350_SMC_DIRECT_CMD_ADDR_CMD_MODE_UPDATE (3 << 21)\r | |
27 | #define PL350_SMC_DIRECT_CMD_ADDR_CMD_UPDATE (2 << 21)\r | |
28 | #define PL350_SMC_DIRECT_CMD_ADDR_CMD_MODE (1 << 21)\r | |
29 | #define PL350_SMC_DIRECT_CMD_ADDR_CMD_UPDATE_AXI (0 << 21)\r | |
30 | #define PL350_SMC_DIRECT_CMD_ADDR_CS_INTERF(interf,chip) (((interf) << 25) | ((chip) << 23))\r | |
31 | #define PL350_SMC_DIRECT_CMD_ADDR_CS(ChipSelect) (((ChipSelect) & 0x7) << 23)\r | |
f501f5d1 | 32 | \r |
c52e2dca | 33 | #define PL350_SMC_SET_OPMODE_MEM_WIDTH_8 (0 << 0)\r |
34 | #define PL350_SMC_SET_OPMODE_MEM_WIDTH_16 (1 << 0)\r | |
35 | #define PL350_SMC_SET_OPMODE_MEM_WIDTH_32 (2 << 0)\r | |
36 | #define PL350_SMC_SET_OPMODE_SET_RD_SYNC (1 << 2)\r | |
37 | #define PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_1 (0 << 3)\r | |
38 | #define PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_4 (1 << 3)\r | |
39 | #define PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_8 (2 << 3)\r | |
40 | #define PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_16 (3 << 3)\r | |
41 | #define PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_32 (4 << 3)\r | |
42 | #define PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT (5 << 3)\r | |
43 | #define PL350_SMC_SET_OPMODE_SET_WR_SYNC (1 << 6)\r | |
44 | #define PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_1 (0 << 7)\r | |
45 | #define PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_4 (1 << 7)\r | |
46 | #define PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_8 (2 << 7)\r | |
47 | #define PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_16 (3 << 7)\r | |
48 | #define PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_32 (4 << 7)\r | |
49 | #define PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT (5 << 7)\r | |
50 | #define PL350_SMC_SET_OPMODE_SET_BAA (1 << 10)\r | |
51 | #define PL350_SMC_SET_OPMODE_SET_ADV (1 << 11)\r | |
52 | #define PL350_SMC_SET_OPMODE_SET_BLS (1 << 12)\r | |
53 | #define PL350_SMC_SET_OPMODE_SET_BURST_ALIGN_ANY (0 << 13)\r | |
54 | #define PL350_SMC_SET_OPMODE_SET_BURST_ALIGN_32 (1 << 13)\r | |
55 | #define PL350_SMC_SET_OPMODE_SET_BURST_ALIGN_64 (2 << 13)\r | |
56 | #define PL350_SMC_SET_OPMODE_SET_BURST_ALIGN_128 (3 << 13)\r | |
57 | #define PL350_SMC_SET_OPMODE_SET_BURST_ALIGN_256 (4 << 13)\r | |
f501f5d1 | 58 | \r |
c52e2dca | 59 | #define PL350_SMC_SET_CYCLE_NAND_T_RC(t) (((t) & 0xF) << 0)\r |
60 | #define PL350_SMC_SET_CYCLE_NAND_T_WC(t) (((t) & 0xF) << 4)\r | |
61 | #define PL350_SMC_SET_CYCLE_NAND_T_REA(t) (((t) & 0x7) << 8)\r | |
62 | #define PL350_SMC_SET_CYCLE_NAND_T_WP(t) (((t) & 0x7) << 11)\r | |
63 | #define PL350_SMC_SET_CYCLE_NAND_T_CLR(t) (((t) & 0x7) << 14)\r | |
64 | #define PL350_SMC_SET_CYCLE_NAND_T_AR(t) (((t) & 0x7) << 17)\r | |
65 | #define PL350_SMC_SET_CYCLE_NAND_T_RR(t) (((t) & 0x7) << 20)\r | |
66 | \r | |
67 | #define PL350_SMC_SET_CYCLE_SRAM_T_RC(t) (((t) & 0xF) << 0)\r | |
68 | #define PL350_SMC_SET_CYCLE_SRAM_T_WC(t) (((t) & 0xF) << 4)\r | |
69 | #define PL350_SMC_SET_CYCLE_SRAM_T_CEOE(t) (((t) & 0x7) << 8)\r | |
70 | #define PL350_SMC_SET_CYCLE_SRAM_T_WP(t) (((t) & 0x7) << 11)\r | |
71 | #define PL350_SMC_SET_CYCLE_SRAM_T_PC(t) (((t) & 0x7) << 14)\r | |
72 | #define PL350_SMC_SET_CYCLE_SRAM_T_TR(t) (((t) & 0x7) << 17)\r | |
73 | #define PL350_SMC_SET_CYCLE_SRAM_WE_TIME (1 << 20)\r | |
f501f5d1 | 74 | \r |
75 | #endif\r |